Allow -numa without initiator value when hmat=on so that we may
build more complex topologies, e.g. NUMA nodes whose best initiators
are not just another single node.
changes v3->v4
* use -numa cpu instead of legacy cpus=
changes v2->v3:
* improve messages for patches 0/4 and 3/4
changes v1->v2:
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by having multiple best
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/FACP.acpihmat-noinitia
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6]
Build a machine with 2 sockets with 2 cores each,
and 3 NUMA nodes.
1st NUMA is local to socket #0 (cores #0-1).
2nd NUMA is local to socket #1 (cores #2-3).
3rd NUMA has no initiator.
HMAT SLLB says memory access performance of 3rd NUMA is lower,
but it's identical for both sockets
hence all core
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
v3:
- hw/i2c/pmbus_device:
- Removed commit that resets the out buf.
- Removed IC_DEVICE_ID
- Added commit to allow devices to move to an idle state that
avoids enqueuing excess data into the out buf.
- hw/sensor/isl
On Wed, Jun 29, 2022 at 07:37:01PM +, Dionna Glaze wrote:
> For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
> v2.9 memory type. In order for OVMF to be able to avoid pre-validating
> potentially hundreds of gibibytes of data before booting, it needs to
> know if the guest O
On Wed, Jun 29, 2022 at 07:54:08PM -0400, John Snow wrote:
> On Tue, Jun 28, 2022 at 10:17 AM Daniel P. Berrangé
> wrote:
> >
> > On Tue, Jun 28, 2022 at 05:49:39PM +0400, marcandre.lur...@redhat.com wrote:
> > > From: Marc-André Lureau
> > >
> > > QMP accept is currently synchronous. If qemu di
Hi Richard,
Richard Henderson writes:
> When EXECUTE sets ex_value to interrupt the constructed instruction,
> we implicitly disable interrupts so that the value is not corrupted.
> Exit to the main loop after execution, so that we re-evaluate any
> pending interrupts.
>
> Reported-by: Sven Schn
On 6/29/22 20:24, Alex Bennée wrote:
Cédric Le Goater writes:
On 6/29/22 16:14, Alex Bennée wrote:
Cédric Le Goater writes:
On 6/24/22 18:50, Cédric Le Goater wrote:
On 6/23/22 20:43, Peter Delevoryas wrote:
On Jun 23, 2022, at 8:09 AM, Cédric Le Goater wrote:
On 6/23/22 12:26, Pet
We allocate VuVirtqElement with g_malloc() in
virtqueue_alloc_element(), but free it with free() in
vhost-user-blk.c. Harmless, but use g_free() anyway.
One of the calls is guarded by a "not null" condition. Useless,
because it cannot be null (it's dereferenced right before), and even
it it coul
> On Jun 22, 2022, at 5:15 PM, Lei He wrote:
>
> This patch introduced ECDSA algorithm for crypto.
>
> V1 -> V2:
> - The reserved function prefix '_' is no longer used.
> - When parsing ECDSA key: 1) set errp as early as possible,
> 2) use g_autoptr to avoid manually freeing memory, 3) simplifie
On Wed, 29 Jun 2022 at 16:56, Jason A. Donenfeld wrote:
> On Wed, Jun 29, 2022 at 04:24:20PM +0100, Alex Bennée wrote:
> > Given the use case for the dtb-kaslr-seed knob I wonder if we should
> > have a common property and deprecate the kaslr one? As of this patch
> > existing workflows will break
* Laurent Vivier (lviv...@redhat.com) wrote:
> Signed-off-by: Laurent Vivier
> Reviewed-by: Stefano Brivio
> ---
> net/stream.c| 106 +---
> qemu-options.hx | 1 +
> 2 files changed, 102 insertions(+), 5 deletions(-)
>
> diff --git a/net/stream.
On Wed, Jun 22, 2022 at 05:15:46PM +0800, Lei He wrote:
> Add ECDSA key parser and ECDSA signature parser.
>
> Signed-off-by: lei he
> ---
> crypto/ecdsakey-builtin.c.inc | 248
> ++
> crypto/ecdsakey.c | 118
> crypto/ecd
* Laurent Vivier (lviv...@redhat.com) wrote:
> Format a string URI from a SocketAddress.
>
> Original code from hmp-cmds.c:SocketAddress_to_str()
>
> Replace 'tcp:' by 'inet:' (because 'inet' can be also 'udp').
I think that's OK, it'll look a little odd in migration where
the syntax for a migra
According to the architecture, SET PREFIX must try to access the new
prefix area and recognize an addressing exception if the area is not
accessible.
For qemu this check prevents a crash in cpu_map_lowcore after an
inaccessible prefix area has been set.
Signed-off-by: Janis Schoetterl-Glausch
Rev
Cédric Le Goater writes:
> On 6/29/22 20:24, Alex Bennée wrote:
>> Cédric Le Goater writes:
>>
>>> On 6/29/22 16:14, Alex Bennée wrote:
Cédric Le Goater writes:
> On 6/24/22 18:50, Cédric Le Goater wrote:
>> On 6/23/22 20:43, Peter Delevoryas wrote:
>>>
>>>
On Tue, 28 Jun 2022 at 10:35, Sam Li wrote:
>
> Stefan Hajnoczi 于2022年6月28日周二 16:20写道：
> >
> > On Mon, Jun 27, 2022 at 08:19:17AM +0800, Sam Li wrote:
> > > diff --git a/tests/qemu-iotests/tests/zoned.sh
> > > b/tests/qemu-iotests/tests/zoned.sh
> > > new file mode 100755
> > > index 00.
On 6/9/22 14:52, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
>> On Thu, Jun 09, 2022 at 12:07:31PM +0200, Claudio Fontana wrote:
>>> Hello all,
>>>
>>> it would be really good to be able to rely on this command or something
>>> similar,
>>> to be able to know
On Thu, Jun 30, 2022 at 12:14:36PM +0200, Claudio Fontana wrote:
> On 6/9/22 14:52, Dr. David Alan Gilbert wrote:
> > * Daniel P. Berrangé (berra...@redhat.com) wrote:
> >> On Thu, Jun 09, 2022 at 12:07:31PM +0200, Claudio Fontana wrote:
> >>> Hello all,
> >>>
> >>> it would be really good to be ab
On Thu, Jun 30, 2022 at 10:15:29AM +0100, Peter Maydell wrote:
> On Wed, 29 Jun 2022 at 16:56, Jason A. Donenfeld wrote:
> > On Wed, Jun 29, 2022 at 04:24:20PM +0100, Alex Bennée wrote:
> > > Given the use case for the dtb-kaslr-seed knob I wonder if we should
> > > have a common property and depr
In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the
kaslr-seed property was added, but the equally as important rng-seed
property was forgotten about, which has identical semantics for a
similar purpose. This commit implements it in exactly the same way as
kaslr-seed. It then changes th
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
The fby35 machine includes 4 server boards, each of which has a "bridge
interconnect" (BIC). This chip abstracts the pinout for the server board
into a single endpoint that the baseboard management controller (BMC)
can talk to usi
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
The Intel Management Engine is an IPMI endpoint that responds to various
IPMI commands.
Have you looked at the ipmi-bmc-sim device ? It is relatively easy
to attach to a bus.
In this commit, I've added some very basic functio
From: Iris Chen
Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
Message-Id: <20220621202427.2680413-1-irische...@fb.com>
Signed-off-by: Cédric Le Goater
---
hw/block/m25p80.c | 82 ++-
1 file changed, 67 insertions(+), 15 deletions(-)
diff
Currently, the Aspeed machines allocate a ram container region in
which the machine ram region is mapped. See commit ad1a9782186d
("aspeed: add a RAM memory region container"). An extra region is
mapped after ram in the ram container to catch invalid access done by
FW. That's how FW determines the
qemu/ tags/pull-aspeed-20220630
for you to fetch changes up to 55c57023b740c29151d42600af9ac43ba00e56cc:
hw/misc/aspeed: Add PECI controller (2022-06-30 09:21:14 +0200)
aspeed queue:
* m25p80 improvements (Iris)
* Code cleanup in p
From: Maheswara Kurapati
Add Thermal Diodes for Firework machine.
Signed-off-by: Maheswara Kurapati
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Cédric Le Goater
Message-Id: <20220627154703.148943-7-quic_jaeh...@quicinc.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1
From: Maheswara Kurapati
Add MAX31785 fan controllers in machines so that the Linux driver
populates the sysfs interface.
Firework has two MAX31785 Fan controllers at 0x52, and 0x54 on bus 9.
Witherspoon has one at 0x52 on bus 3.
Rainier has one at 0x52 on bus 7.
Signed-off-by: Maheswara Kurapa
From: Peter Delevoryas
sysbus_mmio_map maps devices into "get_system_memory()".
With the new SoC memory attribute, we want to make sure that each device is
mapped into the SoC memory.
In single SoC machines, the SoC memory is the same as "get_system_memory()",
but in multi SoC machines it will
From: Iris Chen
Signed-off-by: Iris Chen
Message-Id: <20220624183016.2125264-1-irische...@fb.com>
Signed-off-by: Cédric Le Goater
---
tests/qtest/aspeed_smc-test.c | 62 +++
1 file changed, 62 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qte
From: Peter Delevoryas
Very minor, doesn't effect functionality, but this is supposed to be
R_I2CC_FUN_CTRL (new-mode, not old-mode).
Fixes: ba2cccd64e9 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas
Message-Id: <20220630045133.32251-2...@pjd.dev>
Reviewed-by: Cédric Le G
From: Jae Hyun Yoo
Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework
machine.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Cédric Le Goater
Message-Id: <20220627154703.148943-8-quic_jaeh...@quicinc.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 +-
1 fil
From: Peter Delevoryas
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Message-Id: <20220624003701.1363500-5-p...@fb.com>
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 9 +
hw/arm/aspeed_ast10x0.c | 16 ++--
hw/arm/aspeed_ast2600.c
Reviewed-by: Peter Delevoryas
Message-Id: <20220628154740.1117349-2-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/misc/aspeed_scu.c | 2 ++
hw/misc/trace-events | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 19b03471fc4e..8335364906
From: Peter Delevoryas
aspeed_i2c_bus_is_master is checking if master mode is enabled in the I2C
bus controller's function-control register, not that slave mode is enabled
or something. The error here is that the guest is trying to trigger an I2C
master mode command while master mode is not enab
From: Peter Delevoryas
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I
Using a 'stop' string seems more appropriate than 'normal'.
Reviewed-by: Peter Delevoryas
Message-Id: <20220628154740.1117349-3-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/
From: Peter Delevoryas
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.
This is particularly useful for testing IPMB exchange
From: Joel Stanley
While the HMAC mode is not modelled, the accumulative mode is.
Accumulative mode is enabled by setting one of the bits in the HMAC
engine command mode part of the register, so fix the unimplemented check
to only look at the upper of the two bits.
Fixes: 5cd7d8564a8b ("aspeed/
From: Klaus Jensen
Add slave mode functionality for the Aspeed I2C controller in old
register mode. This is implemented by realizing an I2C slave device
owned by the I2C controller and attached to its own bus.
The I2C slave device only implements asynchronous sends on the bus, so
slaves not supp
From: Peter Delevoryas
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to indicate the command is done. This helps avoid getting
hit with constant errors if the driver continuously attempts to s
From: Klaus Jensen
Add an asynchronous version of i2c_send() that requires the slave to
explicitly acknowledge on the bus with i2c_ack().
The current master must use the new i2c_start_send_async() to indicate
that it wants to do an asynchronous transfer. This allows the i2c core
to check if the
Coverity warns that "ssi_transfer(s->spi, 0U) << 8 * i" might overflow
because the expression is evaluated using 32-bit arithmetic and then
used in a context expecting a uint64_t.
Fixes: Coverity CID 1487244
Message-Id: <20220628165512.1133590-1-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
From: Peter Delevoryas
Signed-off-by: Peter Delevoryas
Message-Id: <20220624003701.1363500-2-p...@fb.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 2 ++
hw/arm/aspeed_soc.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_a
Tiny machines optimized for fast boot time generally don't use EFI,
which means a random seed has to be supplied some other way, in this
case by the e820 setup table, which supplies a place for one. This
commit adds passing this random seed via the table. It is confirmed to
be working with the Linu
From: Peter Delevoryas
Multi-SoC machines can use this property to specify a memory container
for each SoC. Single SoC machines will just specify get_system_memory().
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Message-Id: <20220624003701.1363500-3-p...@fb.com>
Signed-off-by:
From: Peter Delevoryas
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Message-Id: <20220624003701.1363500-6-p...@fb.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/
From: Jae Hyun Yoo
Add qcom-dc-scm-v1 board support.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Cédric Le Goater
Message-Id: <20220627154703.148943-2-quic_jaeh...@quicinc.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 35 +++
1 file changed, 35 inser
From: Graeme Gregory
Add base for Qualcomm Firework BMC machine.
Signed-off-by: Graeme Gregory
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Cédric Le Goater
Message-Id: <20220627154703.148943-3-quic_jaeh...@quicinc.com>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 34 ++
From: Maheswara Kurapati
Current implementation of the pmbus core driver treats the read request
for page 255 as invalid request and sets the invalid command bit (bit 7)
in the STATUS_CML register. As per the PMBus specification it is a valid
request.
Refer to the PMBus specification, revision 1
From: Maheswara Kurapati
MAX31785 is a PMBus compliant 6-Channel fan controller. It supports 6 fan
channels, 11 temperature sensors, and 6-Channel ADC to measure the remote
voltages. Datasheet can be found here:
https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf
This initial version of th
From: Klaus Jensen
Allow slaves to master the bus by registering a bottom halve. If the bus
is busy, the bottom half is queued up. When a slave has succesfully
mastered the bus, the bottom half is scheduled.
Signed-off-by: Klaus Jensen
[ clg : - fixed typos in commit log ]
Message-Id: <20220601
On Thu, 30 Jun 2022 09:36:47 +0200
Brice Goglin wrote:
> Allow -numa without initiator value when hmat=on so that we may
> build more complex topologies, e.g. NUMA nodes whose best initiators
> are not just another single node.
>
patches looks fine code-wise,
however something wrong with them, i
From: Marc-André Lureau
When no monitor address is given, establish the QMP communication through
a socketpair() (API is also supported on Windows since Python 3.5)
Signed-off-by: Marc-André Lureau
---
python/qemu/machine/machine.py | 24
1 file changed, 16 insertions(
From: Marc-André Lureau
Hi,
As reported earlier by Richard Henderson ("virgl avocado hang" thread), avocado
tests may hang when QEMU exits before the QMP connection is established.
v2:
- use a socketpair() for QMP (instead of async concurrent code from v1) as
suggested by Daniel Berrange.
From: Marc-André Lureau
Instead of listening for incoming connections with a SocketAddr, add a
new method open_with_socket() that accepts an existing socket.
Signed-off-by: Marc-André Lureau
---
python/qemu/qmp/protocol.py | 25 -
1 file changed, 20 insertions(+), 5 del
From: Marc-André Lureau
Teach QEMUMonitorProtocol to accept an exisiting socket.
Signed-off-by: Marc-André Lureau
---
python/qemu/qmp/legacy.py | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/python/qemu/qmp/legacy.py b/python/qemu/qmp/legacy.py
index 03
Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
On Thu, 30 Jun 2022 09:36:47 +0200
Brice Goglin wrote:
Allow -numa without initiator value when hmat=on so that we may
build more complex topologies, e.g. NUMA nodes whose best initiators
are not just another single node.
patches looks fine cod
On Thu, 30 Jun 2022 14:40:13 +0200
Brice Goglin wrote:
> Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > On Thu, 30 Jun 2022 09:36:47 +0200
> > Brice Goglin wrote:
> >
> >> Allow -numa without initiator value when hmat=on so that we may
> >> build more complex topologies, e.g. NUMA nodes wh
On 6/30/22 12:20, Daniel P. Berrangé wrote:
> On Thu, Jun 30, 2022 at 12:14:36PM +0200, Claudio Fontana wrote:
>> On 6/9/22 14:52, Dr. David Alan Gilbert wrote:
>>> * Daniel P. Berrangé (berra...@redhat.com) wrote:
On Thu, Jun 09, 2022 at 12:07:31PM +0200, Claudio Fontana wrote:
> Hello al
Hi, Richard
On 2022/6/24 上午11:10, Song Gao wrote:
Hi All,
This series adds support linux-user emulation.
As the LoongArch kernel had merged into 5.19-rc1,
you can see the latest kernel at https://kernel.org
Need review patch:
0002-linux-user-Add-LoongArch-signal-support.patch
V20:
- Up
On 24.06.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
That's the first part of
"[PATCH v5 00/45] Transactional block-graph modifying API",
updated and almost reviewed.
On commit (15) is added to original scope of
"block: cleanup backing and file handling", as it's related.
01: add Han
On Thu, Jun 30, 2022 at 09:40:19AM +0200, Brice Goglin wrote:
...
>
> Before this patch, we had to add ",initiator=X" to "-numa
> node,nodeid=2,memdev=ram2".
> The lstopo output difference between initiator=1 and no initiator is:
> @@ -1,10 +1,10 @@
> Machine (2966MB total) + Package P#0
> +
On Thu, Jun 30, 2022 at 02:56:16PM +0200, Igor Mammedov wrote:
> On Thu, 30 Jun 2022 14:40:13 +0200
> Brice Goglin wrote:
>
> > Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > > On Thu, 30 Jun 2022 09:36:47 +0200
> > > Brice Goglin wrote:
> > >
> > >> Allow -numa without initiator value whe
On Thu, Jun 30, 2022 at 02:40:13PM +0200, Brice Goglin wrote:
>
> Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > On Thu, 30 Jun 2022 09:36:47 +0200
> > Brice Goglin wrote:
> >
> > > Allow -numa without initiator value when hmat=on so that we may
> > > build more complex topologies, e.g. NUMA
Leandro Lupori writes:
> Check if the number and size of Radix levels are valid on
> POWER9/POWER10 CPUs, according to the supported Radix Tree
> Configurations described in their User Manuals.
>
> Signed-off-by: Leandro Lupori
Reviewed-by: Fabiano Rosas
> ---
> target/ppc/mmu-radix64.c | 49
Hi,
(Thanks for the patch!)
On 27.06.22 18:44, Felix xq Queißner wrote:
The patch adds "show_tabs" command line option for GTK ui similar to
"grab_on_hover". This option allows tabbed view mode to not have to be enabled by hand at
each start of the VM.
I’m not sure we have a hard rule on it
On 30.06.22 16:09, Hanna Reitz wrote:
Hi,
(Thanks for the patch!)
On 27.06.22 18:44, Felix xq Queißner wrote:
The patch adds "show_tabs" command line option for GTK ui similar to
"grab_on_hover". This option allows tabbed view mode to not have to
be enabled by hand at each start of the VM.
* Juan Quintela (quint...@redhat.com) wrote:
> We used to synchronize all channels at the end of each RAM section
> sent. That is not needed, so preparing to only synchronize once every
> full round in latests patches.
>
> Notice that we initialize the property as true. We will change the
> defa
On 6/30/22 03:14, Daniel P. Berrangé wrote:
On Wed, Jun 29, 2022 at 07:37:01PM +, Dionna Glaze wrote:
For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
v2.9 memory type. In order for OVMF to be able to avoid pre-validating
potentially hundreds of gibibytes of data before b
Hanna Reitz writes:
> Hi,
>
> (Thanks for the patch!)
>
> On 27.06.22 18:44, Felix xq Queißner wrote:
>> The patch adds "show_tabs" command line option for GTK ui similar to
>> "grab_on_hover". This option allows tabbed view mode to not have to be
>> enabled by hand at each start of the VM.
>
>
Dongwon Kim writes:
> Detaching any addtional guest displays in case multiple displays are
> assigned to the guest OS (e.g. max_outputs=n) so that all of them are
> visible upon lauching.
>
> v2: - making sure type of VC is GD_VC_GFX before qemu_console_is_graphic
> (Gerd Hoffman)
> - v
On 29/06/2022 13:20, Markus Armbruster wrote:
Laurent Vivier writes:
Copied from socket netdev file and modified to use SocketAddress
to be able to introduce new features like unix socket.
"udp" and "mcast" are squashed into dgram netdev, multicast is detected
according to the IP address type
Dongwon Kim writes:
> New integer array parameter, 'monitor' is for specifying the target
> monitors where individual GTK windows are placed upon launching.
>
> Monitor numbers in the array are associated with virtual consoles
> in the order of [VC0, VC1, VC2 ... VCn].
>
> Every GTK window contai
On 30.06.22 03:01, Dominique Martinet wrote:
sqeq.off here is the offset to read within the disk image, so obviously
not 'nread' (the amount we just read), but as the author meant to write
its current value incremented by the amount we just read.
Normally recent versions of linux will not issue
On Wed, Jun 29, 2022 at 11:34 AM Peter Delevoryas wrote:
>
>
> > On Jun 29, 2022, at 11:04 AM, Titus Rwantare wrote:
> >
> > On Tue, 28 Jun 2022 at 20:36, Peter Delevoryas
> > wrote:
> >>
> >> Signed-off-by: Peter Delevoryas
> >> ---
> >
> >> --- a/hw/i2c/pmbus_device.c
> >> +++ b/hw/i2c/pmbus
On Thu, Jun 30, 2022 at 10:01:37AM +0900, Dominique Martinet wrote:
sqeq.off here is the offset to read within the disk image, so obviously
not 'nread' (the amount we just read), but as the author meant to write
its current value incremented by the amount we just read.
Normally recent versions o
On Wed, Jun 29 2022, Eric Auger wrote:
> Hi Connie,
>
> On 6/14/22 10:40, Cornelia Huck wrote:
>> On Fri, Jun 10 2022, Eric Auger wrote:
>>
>>> Hi Connie,
>>> On 5/12/22 15:11, Cornelia Huck wrote:
We need to disable migration, as we do not yet have a way to migrate
the tags as well.
On Wed, Jun 29 2022, Eric Auger wrote:
> Hi Connie,
>
> On 6/13/22 18:02, Cornelia Huck wrote:
>> On Fri, Jun 10 2022, Eric Auger wrote:
>>
>>> Hi Connie,
>>>
>>> On 5/12/22 15:11, Cornelia Huck wrote:
This series enables MTE for kvm guests, if the kernel supports it.
Lightly tested w
> > The most recent patches I recall for SEV-SNP introduced a new
> > 'sev-snp-guest' object instead of overloading the existing
> > 'sev-guest' object:
> >
> >https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg04757.html
> >
>
> Correct, the SNP support for Qemu is only RFC at this point
On Thu, Jun 30, 2022 at 01:02:54PM +0200, Cédric Le Goater wrote:
> On 6/30/22 06:51, Peter Delevoryas wrote:
> > From: Peter Delevoryas
> >
> > The fby35 machine includes 4 server boards, each of which has a "bridge
> > interconnect" (BIC). This chip abstracts the pinout for the server board
> >
On Thu, Jun 30, 2022 at 01:09:09PM +0200, Cédric Le Goater wrote:
> On 6/30/22 06:51, Peter Delevoryas wrote:
> > From: Peter Delevoryas
> >
> > The Intel Management Engine is an IPMI endpoint that responds to various
> > IPMI commands.
>
> Have you looked at the ipmi-bmc-sim device ? It is rela
On 6/30/22 18:15, Peter Delevoryas wrote:
On Thu, Jun 30, 2022 at 01:02:54PM +0200, Cédric Le Goater wrote:
On 6/30/22 06:51, Peter Delevoryas wrote:
From: Peter Delevoryas
The fby35 machine includes 4 server boards, each of which has a "bridge
interconnect" (BIC). This chip abstracts the pin
On some architectures mmap() arguments are passed via an in-memory
array, and qemu's strace support does not recognize that. Fix by
sharing the argument fetching logic between mmap() implementation and
tracing.
An alternative approach would be to fetch arguments only once at the
beginning of do_sy
Il ven 24 giu 2022, 17:57 Richard Henderson
ha scritto:
> But then the i386 cross-compiler isn't used:
>
Yeah, that was intentional. In theory a softmmu target is freestanding and
does not need anything beyond the compiler install, so configure defaults
to the native compiler, which is biarch. T
On Thu, 30 Jun 2022 at 18:14, Paolo Bonzini wrote:
>
>
>
> Il ven 24 giu 2022, 17:57 Richard Henderson ha
> scritto:
>>
>> But then the i386 cross-compiler isn't used:
>
>
> Yeah, that was intentional. In theory a softmmu target is freestanding and
> does not need anything beyond the compiler i
> Is there any hardware documentation that says whether QEMU or
> the DTB is correct? The device tree is at best a secondary source...
No. It should have been in the "BCM2835 ARM Peripherals" datasheet but the
appropriate "ARM peripherals interrupt table" there is nearly empty.
> You can't con
It still happens to me when I try to run Haiku builds on my macos 10.14.
* QEMU emulator version 7.0.0
Command line:
qemu-system-x86_64 -machine q35,accel=hvf -cpu host -smp 4 -m 2048 -vga vmware
-boot menu=on -drive file="haiku-minimum.mmc",if=none,format=raw,id=x0 -device
ide-hd,drive=x0,bus=i
On Thu, Jun 30, 2022 at 06:42:52PM +0200, Cédric Le Goater wrote:
> On 6/30/22 18:15, Peter Delevoryas wrote:
> > On Thu, Jun 30, 2022 at 01:02:54PM +0200, Cédric Le Goater wrote:
> > > On 6/30/22 06:51, Peter Delevoryas wrote:
> > > > From: Peter Delevoryas
> > > >
> > > > The fby35 machine incl
...
> > > /*
> > > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> > > index afe18d70ece7..e18460e0d743 100644
> > > --- a/arch/x86/kvm/mmu/mmu.c
> > > +++ b/arch/x86/kvm/mmu/mmu.c
> > > @@ -2899,6 +2899,9 @@ int kvm_mmu_max_mapping_level(struct kvm *kvm,
> > > if (max_level
On Wed, 29 Jun 2022 at 23:30, Cédric Le Goater wrote:
>
> On 6/30/22 06:51, Peter Delevoryas wrote:
> > From: Peter Delevoryas
> >
> > This adds the ISL69259, using all the same functionality as the existing
> > ISL69260 but overriding the IC_DEVICE_ID.
> >
> > Signed-off-by: Peter Delevoryas
>
On Wed, 29 Jun 2022 at 21:52, Peter Delevoryas wrote:
>
> From: Peter Delevoryas
>
> This adds the ISL69259, using all the same functionality as the existing
> ISL69260 but overriding the IC_DEVICE_ID.
>
> Signed-off-by: Peter Delevoryas
> ---
> hw/sensor/isl_pmbus_vr.c | 28 +++
On Wed, 29 Jun 2022 at 21:52, Peter Delevoryas wrote:
>
> From: Peter Delevoryas
>
> Signed-off-by: Peter Delevoryas
> ---
> hw/i2c/pmbus_device.c | 9 +
> include/hw/i2c/pmbus_device.h | 7 +++
> 2 files changed, 16 insertions(+)
>
> diff --git a/hw/i2c/pmbus_device.c b/hw/
On Wed, 29 Jun 2022 at 21:52, Peter Delevoryas wrote:
>
> From: Peter Delevoryas
>
> This commit adds a passthrough for PMBUS_IC_DEVICE_ID to allow Renesas
> voltage regulators to return the integrated circuit device ID if they
> would like to.
>
> The behavior is very device specific, so it hasn
Before moving debug system register helper functions to a
different file, fix the code style issues (mostly block
comment syntax) so checkpatch doesn't complain about the
code-motion patch.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 58 +
1
Continuing in my series of filling in bits of the architecture
that probably nobody much cares about, this series fixes up
Feat_DoubleLock. DoubleLock is a part of the debug architecture
which allows a guest OS to suppress debug exceptions while
it is powering down a CPU so that they don't cause up
The "OS Lock" in the Arm debug architecture is a way for software
to suppress debug exceptions while it is trying to power down
a CPU and save the state of the breakpoint and watchpoint
registers. In QEMU we implemented the support for writing
the OS Lock bit via OSLAR_EL1 and reading it via OSLSR_
Starting with v7 of the debug architecture, there are three extra
ID registers that add information on top of that provided in
DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the
v7 debug architecture, DBGDEVID is optional, present only of
DBGDIDR.DEVID_imp is set. In v7.1 all three must b
1 - 100 of 149 matches
Mail list logo
