On Thu, Jun 9, 2022 at 3:03 AM Eugenio Perez Martin wrote:
>
> On Wed, Jun 8, 2022 at 6:14 AM Jason Wang wrote:
> >
> >
> > 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > > Enable SVQ to not to forward the descriptor translating its address to
> > > qemu's IOVA but copying to a region outside of the gu
On Thu, Jun 9, 2022 at 3:22 AM Eugenio Perez Martin wrote:
>
> On Wed, Jun 8, 2022 at 6:25 AM Jason Wang wrote:
> >
> >
> > 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > > CVQ needs to be in its own group, not shared with any data vq. Enable
> > > the checking of it here, before introducing address sp
Richard Henderson writes:
> In arm-compat-semi.c, we have more advanced treatment of
> guest file descriptors than we do in other implementations.
> Split out GuestFD and related functions to a new file so
> that they can be shared.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Hende
On Wed, Jun 08, 2022 at 12:06:17PM -0400, Michael S. Tsirkin wrote:
> On Fri, Jun 03, 2022 at 10:59:20AM +0200, Gerd Hoffmann wrote:
> > The pcie host bridge has no io window on microvm,
> > so io reservations will not work.
> >
> > Signed-off-by: Gerd Hoffmann
>
> I don't much like overriding u
+Alex
On 06/09/22 04:00, Kevin Locke wrote:
> ioport access is required for VESA BIOS Extensions (VBE). Since ioport
> access is not forwarded over PCI(e) bridges, graphics adapters must be
> attached directly to the Root Complex in order for the BIOS to provide
> VBE modes. I'm very grateful to
On 06/09/22 09:45, Laszlo Ersek wrote:
> +Alex
>
> On 06/09/22 04:00, Kevin Locke wrote:
> *In theory*, scenario (b) applies to "bochs-display" and
> "virtio-gpu-pci" when you plug them into a legacy PCI slot:
>
>> Plugging a PCI Express device into a PCI slot will hide the Extended
>> Configura
On Thu, Jun 9, 2022 at 9:13 AM Jason Wang wrote:
>
> On Thu, Jun 9, 2022 at 3:22 AM Eugenio Perez Martin
> wrote:
> >
> > On Wed, Jun 8, 2022 at 6:25 AM Jason Wang wrote:
> > >
> > >
> > > 在 2022/5/20 03:12, Eugenio Pérez 写道:
> > > > CVQ needs to be in its own group, not shared with any data vq
On Wed, Jun 08, 2022 at 06:04:02PM -0300, Leonardo Bras wrote:
> During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs were
> introduced, particularly at qio_channel_socket_writev().
>
> Rewrite some of those changes so it's easier to read.
>
This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI
Signed-off-by: Pavel Dovgalyuk
--
v2 changes:
- Using existing tcg instructions for exts, cins, pop
(suggested by Richard Henderson)
---
target/mips/t
The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions
v2 changes:
- simplified instruction decoding and translation (suggested
This patch adds Cavium Octeon vCPU for providing
Octeon-specific instructions.
Signed-off-by: Pavel Dovgalyuk
--
v2 changes:
- vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
target/mips/cpu-defs.c.inc | 28
target/mips/mips-defs.h|1
This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.
Signed-off-by: Pavel Dovgalyuk
--
v2 changes:
- Changed insn field description and simplified the jumps
(suggested by Richard Henderson)
---
target/mips/tcg/meson.build|2 ++
t
Don't skip next leve page table for pdpe/pde when the
PG_PRESENT_MASK is set.
This fixs the issue that no mapping information was
collected from "info mem" for guest with LA57 enabled.
Signed-off-by: Yuan Yao
---
target/i386/monitor.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
On Sat, May 14, 2022 at 12:11:03PM +0800, Longpeng(Mike) wrote:
> From: Longpeng
>
> Hi guys,
>
> With the generic vDPA device, QEMU won't need to touch the device
> types any more, such like vfio.
>
> We can use the generic vDPA device as follow:
> -device vhost-vdpa-device-pci,vhostdev=/dev
Hi,
> I find this too general; a PCI Express device is supposed to work
> without IO resources. Graphics cards with legacy VGA compatibility are
> the exception AIUI (see again Alex's blog about VGA arbitration), so we
> should spell that out.
Yes, it's an exception specifically for VGA ports.
On 08/06/2022 17.51, Paolo Bonzini wrote:
On 6/3/22 19:35, Thomas Huth wrote:
On 03/06/2022 19.26, Claudio Fontana wrote:
On 6/3/22 18:42, Thomas Huth wrote:
The disassembly via capstone should be superiour to our old vixl
sources nowadays, so let's finally cut this old disassembler out
of the
On Thu, Jun 09, 2022 at 10:47:24AM +0200, Thomas Huth wrote:
> On 08/06/2022 17.51, Paolo Bonzini wrote:
> > On 6/3/22 19:35, Thomas Huth wrote:
> > > On 03/06/2022 19.26, Claudio Fontana wrote:
> > > > On 6/3/22 18:42, Thomas Huth wrote:
> > > > > The disassembly via capstone should be superiour t
From: Richard Henderson
This function has one private helper, v8m_is_sau_exempt,
so move that at the same time.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-12-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c |
mu-arm.git
tags/pull-target-arm-20220609
for you to fetch changes up to 414c54d515dba16bfaef643a8acec200c05f229a:
target/arm: Add ID_AA64SMFR0_EL1 (2022-06-08 19:38:59 +0100)
target-arm queue:
* target/arm: Declare support for FE
The FEAT_DoubleFault extension adds the following:
* All external aborts on instruction fetches and translation table
walks for instruction fetches must be synchronous. For QEMU this
is already true.
* SCR_EL3 has a new bit NMEA which disables the masking of SError
interrupts by PSTAT
From: Sai Pavan Boddu
Add a periodic timer which raises vblank at a frequency of 30Hz.
Note that this is a migration compatibility break for the
xlnx-zcu102 board type.
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
Acked-by: Alistair Francis
The architectural feature RASv1p1 introduces the following new
features:
* new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1
* new bits in the fine-grained trap registers that control traps
for these new registers
* new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps
fo
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 11 +--
target/arm/helper.c | 161 +---
target/a
From: Frederic Konrad
The core and the vblend registers size are wrong, they should respectively be
0x3B0 and 0x1E0 according to:
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.
Let's fix that and use macros when creating the mmio region.
Fixes: 58ac48
We have about 30 instances of the typo/variant spelling 'writeable',
and over 500 of the more common 'writable'. Standardize on the
latter.
Change produced with:
sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep
-il writeable)
and then hand-undoing the instance in
From: Sai Pavan Boddu
Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
Acked-by: Alistair Francis
Message-id: 20220601172353.3220232-4-fkon...@xilinx.com
Signed-off-b
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-6-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 4 ---
target/arm/helper.c | 85 -
target/ar
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-4-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 15 +++--
target/arm/helper.c | 137 +++-
target
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-22-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 3 ---
target/arm/helper.c | 64 -
target/a
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-9-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 5 ---
target/arm/helper.c | 75 ---
target/arm/
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-7-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 3 +++
target/arm/helper.c | 41 -
target/arm/pt
From: Richard Henderson
With SME, the vector length does not only come from ZCR_ELx.
Comment that this is either NVL or SVL, like the pseudocode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-2-richard.hender...@linaro.org
Signed-off-by: Peter Ma
From: Richard Henderson
Move the decl from ptw.h to internals.h. Provide an inline
version for user-only, just as we do for arm_stage1_mmu_idx.
Move an endif down to make the definition in helper.c be
system only.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-2-richard.hen
From: Frederic Konrad
When the display port has been initially implemented the device
driver wasn't using interrupts. Now that the display port driver
waits for vblank interrupt it has been noticed that the irq mapping
is wrong. So use the value from the linux device tree and the
ultrascale+ re
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-13-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 3 ---
target/arm/helper.c | 15 ---
target/arm/ptw.c| 16 +
From: Richard Henderson
Instead of checking these bits in fp_exception_el and
also in sve_exception_el, document that we must compare
the results. The only place where we have not already
checked that FP EL is zero is in rebuild_hflags_a64.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hen
From: Richard Henderson
There are a handful of helpers for combine_cacheattrs
that we can move at the same time as the main entry point.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-15-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
-
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-16-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 10 ++
target/arm/helper.c | 416 +---
target/a
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-20-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 3 --
target/arm/helper.c | 128
target/a
From: Richard Henderson
Begin moving all of the page table walking functions
out of helper.c, starting with get_phys_addr().
Create a temporary header file, "ptw.h", in which to
share declarations between the two C files while we
are moving functions.
Move a few declarations to "internals.h", w
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-23-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 10 --
target/arm/helper.c | 77 --
target/a
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-19-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 25 -
target/arm/ptw.c| 25
From: Richard Henderson
We don't need to constrain the value set in zcr_el[1],
because it will be done by sve_zcr_len_for_el.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/
From: Richard Henderson
This is the final user of get_phys_addr_pmsav7_default
within helper.c, so make it static within ptw.c.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-10-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
targe
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-27-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 26 --
target/arm/ptw.c| 24
2 file
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-21-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 70 -
target/ar
From: Richard Henderson
This function is used only once, and will need modification
for Streaming SVE mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.h |
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-11-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 19 ---
target/arm/ptw.c| 21 ++
From: Richard Henderson
The use of ARM_CPU to recover env from cs calls
object_class_dynamic_cast, which shows up on the profile.
This is pointless, because all callers already have env, and
the reverse operation, env_cpu, is only pointer arithmetic.
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
We handle this routing in raise_exception. Promoting the value early
means that we can't directly compare FPEXC_EL and SVEEXC_EL.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-4-richard.hender...@linaro.org
Signed-off-by:
From: Richard Henderson
Begin creation of sve_ldst_internal.h by moving the primitives
that access host and tlb memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/sv
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-8-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 10 +--
target/arm/helper.c | 194 +---
target/a
From: Richard Henderson
This check is buried within arm_hcr_el2_eff(), but since we
have to have the explicit check for CPTR_EL2.TZ, we might as
well just check it once at the beginning of the block.
Once this is done, we can test HCR_EL2.{E2H,TGE} directly,
rather than going through arm_hcr_el2
From: Richard Henderson
Put the inline function near the array declaration.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vec_internal.h | 8 +++-
target/arm/sve_he
From: Richard Henderson
The bitmap need only hold 15 bits; bitmap is over-complicated.
We can simplify operations quite a bit with plain logical ops.
The introduction of SVE_VQ_POW2_MAP eliminates the need for
looping in order to search for powers of two. Simply perform
the logical ops and use
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-14-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 4 ++--
target/arm/helper.c | 26 +-
target/arm/ptw.c| 23 +
From: Richard Henderson
This will be used for both Normal and Streaming SVE, and the value
does not necessarily come from ZCR_ELx. While we're at it, emphasize
the units in which the value is returned.
Patch produced by
git grep -l sve_zcr_len_for_el | \
xargs -n1 sed -i 's/sve_zcr_len_
From: Richard Henderson
Move the data to vec_helper.c and the inline to vec_internal.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vec_internal.h | 7 +++
targe
From: Richard Henderson
Move the ptw load functions, plus 3 common subroutines:
S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian.
This also allows get_phys_addr_lpae to become static again.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-17-richard.he
Call virtio_bus_reset instead of virtio_reset, so that the function
need not receive the VirtIODevice.
Signed-off-by: Paolo Bonzini
---
hw/s390x/virtio-ccw.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 15b458
From: Richard Henderson
Export all of the support functions for performing bulk
fault analysis on a set of elements at contiguous addresses
controlled by a predicate.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-15-richard.hender...@linaro.org
S
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-25-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 1 -
target/arm/helper.c | 16
target/arm/ptw.c| 16 ++
From: Richard Henderson
We will need this over in sme_helper.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vec_internal.h | 13 +
target/arm/vec_helper.c
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-26-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 17
target/arm/helper.c | 47 --
From: Richard Henderson
This (newish) ARM pseudocode function is easier to work with
than open-coded tests for HCR_E2H etc. Use of the function
will be staged into the code base in parts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-6-richard.h
Patches 1, 3 and 4 are cleanups with no functional changes (intended, at
least). Patch 2 is a small fix to legacy virtio-mmio reset, whose
behavior differed slightly compared to zeroing the status of the device.
Paolo
Paolo Bonzini (4):
s390x: simplify virtio_ccw_reset_virtio
virtio-mmio: st
On Sun, May 29, 2022 at 12:45:06PM +0200, Philippe Mathieu-Daudé wrote:
> On 29/5/22 10:25, Akihiko Odaki wrote:
> > Signed-off-by: Akihiko Odaki
> > ---
> > ui/cocoa.m | 6 +-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/ui/cocoa.m b/ui/cocoa.m
> > index 09a6281
If the queue PFN is set to zero on a virtio-mmio device, the device is reset.
In that case however the virtio_bus_stop_ioeventfd function was not
called; add it so that the behavior is similar to when status is set to 0.
Signed-off-by: Paolo Bonzini
---
hw/virtio/virtio-mmio.c | 1 +
1 file chan
On Wed, 8 Jun 2022 09:53:05 -0400
Igor Mammedov wrote:
> Changelog:
> since v1:
> * add tis 2.0 clarification to commit message (Ani Sinha)
> * rebase on top of pci tree
> * pick up acks
tests fail due to new cxl testcase,
so I need to fixup whitelisting/blob updating patches and
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-24-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/ptw.h| 1 -
target/arm/helper.c | 24
target/arm/ptw.c| 22 ++
From: Richard Henderson
This will be used for implementing FEAT_SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
dif
From: Richard Henderson
These functions are used for both page table walking and for
deciding what format in which to deliver exception results.
Since ptw.c is only present for system mode, put the functions
into tlb_helper.c.
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-1
All calls to virtio_bus_reset are preceded by virtio_bus_stop_ioeventfd,
move the call in virtio_bus_reset: that makes sense and clarifies
that the vdc->reset function is called with ioeventfd already stopped.
Signed-off-by: Paolo Bonzini
---
hw/s390x/virtio-ccw.c | 1 -
hw/virtio/virtio-bus.c
On Mon, Mar 14, 2022 at 09:36:54AM -0400, Emanuele Giuseppe Esposito wrote:
> In preparation to the job_lock/unlock usage, create _locked
> duplicates of some functions, since they will be sometimes called with
> job_mutex held (mostly within job.c),
> and sometimes without (mostly from JobDrivers
From: Richard Henderson
Use the function instead of the array directly.
Because the function performs its own masking, via the uint8_t
parameter, we need to do nothing extra within the users: the bits
above the first 2 (_uh) or 4 (_uw) will be discarded by assignment
to the local bmask variables
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220604040607.269301-28-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 32
target/arm/ptw.c| 28 ++
Make virtio_mmio_soft_reset reset the virtio device, which is performed by
both the "soft" and the "hard" reset; and then call virtio_mmio_soft_reset
from virtio_mmio_reset to emphasize that the latter is a superset of the
former.
Signed-off-by: Paolo Bonzini
---
hw/virtio/virtio-mmio.c | 17 +++
From: Richard Henderson
Add an interface function to extract the digested vector length
rather than the raw zcr_el[1] value. This fixes an incorrect
return from do_prctl_set_vl where we didn't take into account
the set of vector lengths supported by the cpu.
Reviewed-by: Peter Maydell
Signed-o
On Mon, Mar 14, 2022 at 09:36:52AM -0400, Emanuele Giuseppe Esposito wrote:
> job_event_* functions can all be static, as they are not used
> outside job.c.
>
> Same applies for job_txn_add_job().
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> include/qemu/job.h | 18 --
>
From: Richard Henderson
The ARM pseudocode function NVL uses this predicate now,
and I think it's a bit clearer. Simplify the pseudocode
condition by noting that IsInHost is always false for EL1.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-7-r
On Mon, Mar 14, 2022 at 09:37:02AM -0400, Emanuele Giuseppe Esposito wrote:
> /**
> * @job: The job to enter.
> + * Called with job_mutex *not* held.
> *
> * Continue the specified job by entering the coroutine.
> + * Called with job_mutex lock *not* held.
A similar comment was added just a
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> This renames the following QEMUFile fields
>
> * bytes_xfer -> rate_limit_used
> * xfer_limit -> rate_limit_max
>
> The intent is to make it clear that 'bytes_xfer' is specifically related
> to rate limiting of data and applies to data queued,
From: Richard Henderson
The ARM pseudocode function CheckNormalSVEEnabled uses this
predicate now, and I think it's a bit clearer.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
tar
On Mon, Mar 14, 2022 at 09:37:01AM -0400, Emanuele Giuseppe Esposito wrote:
> @@ -135,32 +137,37 @@ void block_job_remove_all_bdrv(BlockJob *job);
> bool block_job_has_bdrv(BlockJob *job, BlockDriverState *bs);
>
> /**
> - * block_job_set_speed:
> + * block_job_set_speed_locked:
> * @job: The
On Sun, Jun 05, 2022 at 10:50:28AM +0200, Volker Rümelin wrote:
> The first patch fixes a GL context leak.
>
> The second patch fixes a black guest screen on Wayland with OpenGL
> accelerated QEMU graphics devices. This bug doesn't seem to be related to
> issues #910, #865, #671 or #298.
Both que
From: Richard Henderson
This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220607203306.657998-21-richard.hender...@linaro.org
Signed-off-by: Pet
On Tue, May 31, 2022 at 01:23:27PM -0700, Dongwon Kim wrote:
> New integer array parameter, 'monitor' is for specifying the target
> displays where individual QEMU windows are placed upon launching.
>
> The array contains a series of numbers representing the monitor where
> QEMU windows are placed
On Thu, May 26, 2022 at 07:08:14AM +, Wen, Jianxian wrote:
> The update makes it easier to find and specify devices.
> They can only be found by device type name without the id field,
> for example, devices of the same type have the same label.
> The update also adds a head field,
> which is us
On Mon, Mar 14, 2022 at 09:36:59AM -0400, Emanuele Giuseppe Esposito wrote:
> @@ -530,20 +540,24 @@ void job_enter(Job *job)
> job_enter_cond(job, NULL);
> }
>
> -/* Yield, and schedule a timer to reenter the coroutine after @ns
> nanoseconds.
> +/*
> + * Yield, and schedule a timer to ree
On 2022/6/9 10:42, Song Gao wrote:
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
- target_resource.h
- target_structs.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user
On Mon, Mar 14, 2022 at 09:37:00AM -0400, Emanuele Giuseppe Esposito wrote:
> /**
> - * Release a reference that was previously acquired with job_ref() or
> + * Release a reference that was previously acquired with job_ref_locked() or
> * job_create(). If it's the last reference to the object, i
On Thu, May 19, 2022 at 08:39:38PM +0800, Hongren (Zenithal) Zheng wrote:
> Signed-off-by: Hongren (Zenithal) Zheng
> ---
> docs/system/device-emulation.rst | 1 +
> docs/system/devices/canokey.rst | 168 +++
> 2 files changed, 169 insertions(+)
> create mode 10064
On 2022/6/9 10:42, Song Gao wrote:
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
I'm not sure why this is necessary, is this for building on 32-bit where
__BITS_PER_LONG are (incorrectly) reflecting the host bitness?
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> This makes the field name align with the newly introduced method
> names in the previous commit.
I think that's the method in the following commits?
tbh I'm not sure about this; 'pos' is still passed to writev_buffer
and get_buffer to say where
On Tue, May 31, 2022 at 01:23:27PM -0700, Dongwon Kim wrote:
> New integer array parameter, 'monitor' is for specifying the target
> displays where individual QEMU windows are placed upon launching.
>
> The array contains a series of numbers representing the monitor where
> QEMU windows are placed
On Thu, Jun 9, 2022, at 12:09, Gerd Hoffmann wrote:
> Hi,
>
> > if (cpage > 4) {
> > fprintf(stderr, "cpage out of range (%u)\n", cpage);
> > +bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
> > +offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
> >
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> On Thu, Jun 09, 2022 at 10:51:27AM +0100, Dr. David Alan Gilbert wrote:
> > * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > > This makes the field name align with the newly introduced method
> > > names in the previous commit.
> >
> > I thi
On Thu, Jun 09, 2022 at 10:51:27AM +0100, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > This makes the field name align with the newly introduced method
> > names in the previous commit.
>
> I think that's the method in the following commits?
Opps, yeah, I
On Tue, May 31, 2022 at 01:23:26PM -0700, Dongwon Kim wrote:
> Detaching any addtional guest displays in case there are multiple
> displays assigned to the guest OS (e.g. max_outputs=n) so that
> all of them are visible upon lauching.
>
> Cc: Daniel P. Berrangé
> Cc: Markus Armbruster
> Cc: Phil
On Sun, May 08, 2022 at 05:32:22PM +0200, Arnout Engelen wrote:
> The 'active' bit passes control over a qTD between the guest and the
> controller: set to 1 by guest to enable execution by the controller,
> and the controller sets it to '0' to hand back control to the guest.
>
> ehci_state_writeb
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