Re: [PATCH] hw/arm/aspeed: Add i2c devices for AST2600 EVB

On 5/25/22 12:00, Howard Chiu wrote: Add EEPROM and LM75 temperature sensor according to hardware schematic Signed-off-by: Howard Chiu Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/arm/

[PATCH v5 06/15] qga: use qga_open_cloexec() for safe_open_or_create()

From: Marc-André Lureau The function takes care of setting CLOEXEC. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster --- qga/commands-posix.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/qga/commands-posix.c b/qga/commands-posix.c index 8ee149e550.

[PATCH v5 14/15] qga/wixl: replace QEMU_GA_MSI_MINGW_BIN_PATH with glib bindir

From: Marc-André Lureau Use more conventional variables to set the location of pre-built DLL/bin. Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- configure | 9 ++--- meson.build | 5 - qga/installer/qemu-ga.wxs | 24 ---

[PATCH v5 11/15] qga/wixl: prefer variables over environment

From: Marc-André Lureau No need to setup an environment or to check if the variable is undefined manually. Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- qga/installer/qemu-ga.wxs | 30 +- qga/meson.build | 9 - 2 files chan

Re: [PATCH] aio_wait_kick: add missing memory barrier

On Tue, May 24, 2022 at 01:30:54PM -0400, Emanuele Giuseppe Esposito wrote: > It seems that aio_wait_kick always required a memory barrier > or atomic operation in the caller, but nobody actually > took care of doing it. > > Let's put the barrier in the function instead, and pair it > with another

[PATCH v5 00/15] Misc cleanups

From: Marc-André Lureau Hi, More preliminary cleanups before a series to make qemu-ga a meson subproject(). v5: - drop Error argument from qga_open_cloexec() - add r-b tags v4: - remove some unnecessary ERRP_GUARD() - open-code some g_clear_pointer() - don't export qemu_open_cloexec, introduce

[PATCH v5 15/15] test/qga: use g_auto wherever sensible

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- tests/unit/test-qga.c | 121 +++--- 1 file changed, 43 insertions(+), 78 deletions(-) diff --git a/tests/unit/test-qga.c b/tests/unit/test-qga.c index ab0b12a2dd..5

[PATCH v5 02/15] util/win32: simplify qemu_get_local_state_dir()

From: Marc-André Lureau SHGetFolderPath() is a deprecated API: https://docs.microsoft.com/en-us/windows/win32/api/shlobj_core/nf-shlobj_core-shgetfolderpatha It is a wrapper for SHGetKnownFolderPath() and CSIDL_COMMON_PATH is mapped to FOLDERID_ProgramData: https://docs.microsoft.com/en-us/windo

[PATCH v5 09/15] qga: make build_fs_mount_list() return a bool

From: Marc-André Lureau Change build_fs_mount_list() to return bool, in accordance with the guidance under = Rules = in include/qapi/error.h Signed-off-by: Marc-André Lureau Suggested-by: Markus Armbruster --- qga/commands-posix.c | 25 ++--- 1 file changed, 10 insertions(

[PATCH v5 08/15] qga: replace qemu_open_old() with qga_open_cloexec()

From: Marc-André Lureau qemu_open_old() uses qemu_open_internal() which handles special "/dev/fdset/" path for monitor fd sets, set CLOEXEC, and uses Error reporting (and some O_DIRECT special error casing). The monitor fdset handling is unnecessary for qga, use qga_open_cloexec() instead. Sign

[PATCH v5 04/15] qga: flatten safe_open_or_create()

From: Marc-André Lureau There is a bit too much nesting in the function, this can be simplified a bit to improve readability. This also helps with the following error handling changes. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster --- qga/commands-posix.c | 120

[PATCH v5 13/15] qga/wixl: simplify some pre-processing

From: Marc-André Lureau Sadly, wixl doesn't have 'elif'. Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- qga/installer/qemu-ga.wxs | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/qga/installer/qemu-ga.wxs b/qga/installer/qemu-ga.w

Re: [PATCH v10 04/14] vfio-user: build library

On Tue, May 24, 2022 at 11:30:23AM -0400, Jagannathan Raman wrote: > add the libvfio-user library as a submodule. build it as a meson > subproject. > > libvfio-user is distributed with BSD 3-Clause license and > json-c with MIT (Expat) license > > Signed-off-by: Elena Ufimtseva > Signed-off-by:

[PATCH v5 03/15] tests: make libqmp buildable for win32

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Reviewed-by: Thomas Huth --- tests/qtest/libqmp.h | 2 ++ tests/qtest/libqmp.c | 34 +- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/tests/qtest/libqmp.h b/tests/qtest/libqmp.h index 5c

Re: [PATCH v10 00/14] vfio-user server in QEMU

On Tue, May 24, 2022 at 11:30:19AM -0400, Jagannathan Raman wrote: > Hi, > > This is v10 of the server side changes to enable vfio-user in QEMU. > > Thank you for reviewing and sharing your feedback for the previous > revision. We have addressed your comments in this revision. > > We have droppe

[PATCH v5 01/15] include: move qemu_*_exec_dir() to cutils

From: Marc-André Lureau The function is required by get_relocated_path() (already in cutils), and used by qemu-ga and may be generally useful. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster --- include/qemu/cutils.h| 7 ++ include/qemu/osdep.h

[PATCH v5 12/15] qga/wixl: require Mingw_bin

From: Marc-André Lureau No clear reason to make guesses here. Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- qga/installer/qemu-ga.wxs | 9 - 1 file changed, 9 deletions(-) diff --git a/qga/installer/qemu-ga.wxs b/qga/installer/qemu-ga.wxs index 8a19aa1656..651d

[PATCH] MAINTAINERS: Update s390 vhost entries

Commit 7a523d96a0 ("virtio-ccw: move vhost_ccw_scsi to a separate file") introduced a new file hw/s390x/vhost-scsi-ccw.c, which received a couple comments [1][2] to update MAINTAINERS that were missed. Fix that by making the vhost CCW entries a wildcard. [1] https://lore.kernel.org/r/d8d2bbd5021

[PATCH v5 10/15] test/qga: use G_TEST_DIR to locate os-release test file

From: Marc-André Lureau This a more accurate way to lookup the test data, and will allow to move the test in a subproject. Signed-off-by: Marc-André Lureau Reviewed-by: Konstantin Kostiuk --- tests/unit/test-qga.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a

[PATCH v5 07/15] qga: throw an Error in ga_channel_open()

From: Marc-André Lureau Allow for a single point of error reporting, and further refactoring. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster --- qga/channel-posix.c | 42 +- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git

[PATCH v5 05/15] qga: add qga_open_cloexec() helper

From: Marc-André Lureau QGA calls qemu_open_old() in various places. Calling qemu_open() instead isn't a great alternative, as it has special "/dev/fdset" handling and depends on QEMU internal monitor data structures. Instead, provide a simple helper for QGA needs, with Error* support. The follo

[PATCH v2.1 2/3] target/riscv: Make CPU property names lowercase

Many CPU properties for RISC-V are in lowercase except those with "capitalized" (or CamelCase) names: - Counters - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit makes lowercase names primary but keeps capitalized names as aliases (for backward compatibility, but with

Re: [PATCH v10 13/14] vfio-user: handle device interrupts

On Tue, May 24, 2022 at 11:30:32AM -0400, Jagannathan Raman wrote: > Forward remote device's interrupts to the guest > > Signed-off-by: Elena Ufimtseva > Signed-off-by: John G Johnson > Signed-off-by: Jagannathan Raman > --- > include/hw/pci/pci.h | 13 > include/hw/remote/v

Re: [PATCH v9 08/12] target/hexagon: import flex/bison to docker files

On 5/25/22 05:29, Anton Johansson wrote: For clarity's sake, here are the exact steps taken to produce this patch:     1. Update QEMU's libvirt-ci to the commit https://gitlab.com/libvirt/libvirt-ci/-/commit/43927ff508e8ecb1ac225dabbc95b37c890db917    which adds flex/bison, and a native

Re: [PATCH v7 13/14] tests: Add postcopy tls recovery migration test

* Peter Xu (pet...@redhat.com) wrote: > It's easy to build this upon the postcopy tls test. Rename the old > postcopy recovery test to postcopy/recovery/plain. > > Signed-off-by: Peter Xu Reviewed-by: Dr. David Alan Gilbert > --- > tests/qtest/migration-test.c | 38 ++

Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase

On 2022/05/25 21:10, Víctor Colombo wrote: > On 25/05/2022 06:54, Tsukasa OI wrote: >> Many CPU properties for RISC-V are in lowercase except those with >> "capitalized" (or CamelCase) names: >> >> -   Counters >> -   Zifencei >> -   Zicsr >> -   Zfh >> -   Zfhmin >> -   Zve32f >> -   Zve64f >> >>

Re: [PATCH v2 1/1] hw/arm/aspeed: Add fby35 machine type

> On May 25, 2022, at 1:41 AM, Cédric Le Goater wrote: > > Hello Peter, > >> On 5/4/22 00:59, Peter Delevoryas wrote: >> Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace >> i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. >> Reference images

Re: [PATCH v17 6/8] softmmu/dirtylimit: Implement virtual CPU throttle

在 2022/5/24 0:44, manish.mishra 写道: On 17/05/22 1:49 pm, Hyman Huang wrote: Thanks Manish for the comment, i'll give my explanation and any supplement are welcomed. Really sorry for such late reply Hyman, this slipped my mind. 在 2022/5/17 1:13, manish.mishra 写道: Hi Hyman Huang, I had fe

Re: [PATCH v17 6/8] softmmu/dirtylimit: Implement virtual CPU throttle

On Wed, May 25, 2022 at 11:38:26PM +0800, Hyman Huang wrote: > > 2. Also this algorithm only control or limits dirty rate by guest > > writes. There can be some memory dirtying done by virtio based devices > > which is accounted only at qemu level so may not be accounted through > > dirty rings so

Re: Accelerating non-standard disk types

On Thu, May 19, 2022 at 06:39:39PM +, Raphael Norwitz wrote: > On Tue, May 17, 2022 at 03:53:52PM +0200, Paolo Bonzini wrote: > > On 5/16/22 19:38, Raphael Norwitz wrote: > > > [1] Keep using the SCSI translation in QEMU but back vDisks with a > > > vhost-user-scsi or vhost-user-blk backend dev

[PULL 03/15] docs: aspeed: Add fby35 board

From: Peter Delevoryas Add fby35 to the list of Aspeed boards. Signed-off-by: Peter Delevoryas Message-Id: <20220506193354.990532-2-p...@fb.com> Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/aspeed.rst b/docs

[PULL 04/15] hw: m25p80: allow write_enable latch get/set

From: Iris Chen The write_enable latch property is not currently exposed. This commit makes it a modifiable property. Signed-off-by: Iris Chen Acked-by: Thomas Huth Reviewed-by: Cédric Le Goater Reviewed-by: Francisco Iglesias Message-Id: <20220513055022.951759-1-irische...@fb.com> Signed-of

[PULL 00/15] aspeed queue

The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d: Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspee

[PULL 08/15] hw: aspeed: Ensure AST1030 respects uart-default

From: Peter Delevoryas The AST1030 machine initialization was not respecting the Aspeed SoC property "uart-default", which specifies which UART should be connected to the first serial device, it was just always connecting UART5. This doesn't change any behavior, because the default value for "uar

[PULL 01/15] docs: add minibmc section in aspeed document

From: Jamin Lin Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220506031521.13254-2-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 61 ++ 1 file changed, 61 insertions(+) diff --git a/docs/

[PULL 09/15] hw: aspeed: Introduce common UART init function

From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Message-Id: <20220516062328.298336-5-p...@fb.com> Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast10x0.c | 7 ++- hw/arm/aspeed_ast2600.c | 7 ++- hw

[PULL 05/15] aspeed: Introduce a get_irq AspeedSoCClass method

and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code. Cc: Jamin Lin Cc: Peter Delevoryas Reviewed-by: Peter Delevoryas Signed-off-by: Cédric Le Goater Message-Id: <20220516055620.2380197-1-...@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/arm

[PULL 07/15] hw: aspeed: Add uarts_num SoC attribute

From: Peter Delevoryas AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13. Signed-off-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Message-Id: <20220516062328.298336-3-p...@fb.com> Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspee

[PULL 10/15] hw: aspeed: Init all UART's with serial devices

From: Peter Delevoryas Background: AspeedMachineClass.uart_default specifies the serial console UART, which usually corresponds to the "stdout-path" in the device tree. The default value is UART5, since most boards use UART5 for this: amc->uart_default = ASPEED_DEV_UART5; Users can overri

[PULL 12/15] hw/gpio: Add ASPEED GPIO model for AST1030

From: Jamin Lin AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message

[PULL 14/15] hw/gpio: replace HWADDR_PRIx with PRIx64

From: Jamin Lin 1. replace HWADDR_PRIx with PRIx64 2. fix indent issue Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220525053444.27228-5-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- include/hw/gpio/aspeed_gpio.h | 2 +- hw/gpio/aspeed_gpio.c

[PULL 02/15] hw/arm/aspeed: Add fby35 machine type

From: Peter Delevoryas Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. Reference images can be found in Facebook OpenBMC Github Release assets as "fby35.mtd". [3] You can boot the reference imag

Re: [RFC PATCH] python: add qmp-send program to send raw qmp commands to qemu

On Wed, Mar 16, 2022 at 10:54:55AM +0100, Damien Hedde wrote: > +def raw_load(file: TextIO) -> List[QMPMessage]: > +"""parse a raw qmp command file. > + > +JSON formatted commands can expand on several lines but must > +be separated by an end-of-line (two commands can not share the >

Re: [PATCH v2 02/15] include/hw/virtio: more comment for VIRTIO_F_BAD_FEATURE

On Tue, May 24, 2022 at 04:40:43PM +0100, Alex Bennée wrote: > When debugging a new vhost user you may be surprised to see > VHOST_USER_F_PROTOCOL getting squashed in the maze of > backend_features, acked_features and guest_features. Expand the > description here to help the next poor soul trying t

[PULL 06/15] hw: aspeed: Add missing UART's

From: Peter Delevoryas This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030. This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical.

Re: [PATCH v2 00/15] virtio-gpio and various virtio cleanups

On Tue, May 24, 2022 at 04:40:41PM +0100, Alex Bennée wrote: > Hi, > > This series ostensibly adds virtio-user-gpio stubs to the build for > use with an external vhost-user daemon. We've been testing it with our > rust daemons from: > > https://github.com/rust-vmm/vhost-device > > Getting the

Re: [PATCH v2 15/15] tests/qtest: enable tests for virtio-gpio

On Tue, May 24, 2022 at 04:40:56PM +0100, Alex Bennée wrote: > We don't have a virtio-gpio implementation in QEMU and only > support a vhost-user backend. The QEMU side of the code is minimal so > it should be enough to instantiate the device and pass some vhost-user > messages over the control soc

[PULL 11/15] hw/gpio Add GPIO read/write trace event.

From: Jamin Lin Add GPIO read/write trace event for aspeed model. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220525053444.27228-2-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- hw/gpio/aspeed_gpio.c | 54 +++ h

[PULL 13/15] hw/gpio support GPIO index mode for write operation.

From: Jamin Lin It did not support GPIO index mode for read operation. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220525053444.27228-4-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- include/hw/gpio/aspeed_gpio.h | 14 +++ hw/gpio/aspeed_gpio.c

Re: [PULL v2 0/4] qemu-ga patches

On 5/25/22 02:29, Konstantin Kostiuk wrote: The following changes since commit 0cac736e73723850a99e5142e35d14d8f8efb232: Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into staging (2022-05-24 15:55:12 -0700) are available in the Git repository

Re: [PATCH v2 0/1] tests: Bump Fedora image version for cross-compilation

Konstantin Kostiuk writes: > v1 -> v2: Fix spelling in the commit message > v1: https://patchew.org/QEMU/2022052418.922031-1-kkost...@redhat.com/ > > Konstantin Kostiuk (1): > tests: Bump Fedora image version for cross-compilation Queued to testing/next, thanks. -- Alex Bennée

[PULL 15/15] hw/arm/aspeed: Add i2c devices for AST2600 EVB

From: Howard Chiu Add EEPROM and LM75 temperature sensor according to hardware schematic Signed-off-by: Howard Chiu Reviewed-by: Cédric Le Goater Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.

Re: [PATCH v2 01/15] contrib/vhost-user-blk: fix 32 bit build and enable

On Tue, May 24, 2022 at 04:40:42PM +0100, Alex Bennée wrote: > We were not building the vhost-user-blk server due to 32 bit > compilation problems. The problem was due to format string types so > fix that and then enable the build. Tweak the rule to follow the same > rules as other vhost-user daemo

Re: [PATCH v9 08/12] target/hexagon: import flex/bison to docker files

Richard Henderson writes: > On 5/25/22 05:29, Anton Johansson wrote: >> For clarity's sake, here are the exact steps taken to produce this patch: >>     1. Update QEMU's libvirt-ci to the commit >> https://gitlab.com/libvirt/libvirt-ci/-/commit/43927ff508e8ecb1ac225dabbc95b37c890db917 >>

Re: [PATCH v2 03/15] include/hw/virtio: document vhost_get_features

On Tue, May 24, 2022 at 04:40:44PM +0100, Alex Bennée wrote: > Signed-off-by: Alex Bennée > --- > include/hw/virtio/vhost.h | 11 +++ > 1 file changed, 11 insertions(+) Reviewed-by: Stefan Hajnoczi signature.asc Description: PGP signature

Re: [PATCH v2 04/15] include/hw/virtio: document vhost_ack_features

On Tue, May 24, 2022 at 04:40:45PM +0100, Alex Bennée wrote: > Signed-off-by: Alex Bennée > --- > include/hw/virtio/vhost.h | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Stefan Hajnoczi signature.asc Description: PGP signature

[PATCH v3 0/6] hw/acpi/viot: generate stable VIOT ACPI tables

I was working away at some improvements for PS2 devices when I noticed that one small change to the instantiation of a PS2 mouse device caused a regression in tests/qtest/bios-tables-test, specifically the /x86_64/acpi/q35/viot subtest. Closer examination of the failed test output showed the probl

[PATCH v3 3/6] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table

Perform the generation of the VIOT ACPI table in 2 separate passes: the first pass enumerates all of the PCI host bridges and adds the min_bus and max_bus information to an array. Once this is done the VIOT table header is generated using the size of the array to calculate the node count, which

[PATCH v3 6/6] tests/acpi: virt: update golden masters for VIOT

Differences between disassembled ASL files for VIOT: +++ /tmp/asl-V69GM1.dsl 2022-05-18 10:22:27.239796759 +0100 @@ -36,11 +36,11 @@ [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 -[044h 0068 4] Endpoint start : 3000 +[0

[PATCH v3 5/6] hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus

This ensures that the VIOT ACPI table output is always stable for a given PCI topology by ensuring that entries are ordered according to min_bus. Signed-off-by: Mark Cave-Ayland Reviewed-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé --- hw/acpi/viot.c | 17 + 1 file changed

[PATCH v3 1/6] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges()

This is in preparation for separating out the VIOT ACPI table build from the PCI host bridge numeration. Signed-off-by: Mark Cave-Ayland Reviewed-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé --- hw/acpi/viot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/acpi

[PATCH v3 4/6] tests/acpi: virt: allow VIOT acpi table changes

Signed-off-by: Mark Cave-Ayland Acked-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b

[PATCH v3 2/6] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function

Instead of generating each table entry inline, move the individual PCI host bridge table entry generation to a separate build_pci_host_range() function. Signed-off-by: Mark Cave-Ayland Reviewed-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé --- hw/acpi/viot.c | 48 +

[PATCH] gitlab-ci: add meson JUnit test result into report

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- .gitlab-ci.d/buildtest-template.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.d/buildtest-template.yml b/.gitlab-ci.d/buildtest-template.yml index dc6d67aacf..b381345dbc 100644 --- a/.gitlab-ci.d/buildtest-temp

[PATCH] target/arm/hvf: Include missing "cpregs.h"

From: Philippe Mathieu-Daudé Fix when building HVF on macOS Aarch64: target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you mean 'ARMCPUInfo'? const ARMCPRegInfo *ri; ^~~~ ARMCPUInfo target/arm/cpu-qom.h:38:3: note: 'A

[PATCH] target/arm/hvf: Fix build failure due to missing cpregs.h header file

cpregs.h was previously split out from cpu.h into a separate file, but I think this was forgotten to be included in hvf.c. I got a build failure when trying to build on Apple Silicon: [...] ../target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier 'ARM_CP_NO_RAW' assert(!(r

Re: [PATCH v2 5/6] hw/isa/piix4: QOM'ify PIIX4 PM creation

On 22/05/2022 22:24, Bernhard Beschow wrote: Just like the real hardware, create the PIIX4 ACPI controller as part of the PIIX4 southbridge. This also mirrors how the IDE and USB functions are already created. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c| 14 +++

[PATCH] target/i386/tcg: Fix masking of real-mode addresses with A20 bit

The correct A20 masking is done if paging is enabled (protected mode) but it seems to have been forgotten in real mode. For example from the AMD64 APM Vol. 2 section 1.2.4: > If the sum of the segment base and effective address carries over into bit 20, > that bit can be optionally truncated to mi

Re: [PULL 0/8] Linux user for 7.1 patches

ll request linux-user 20220525 s390x fixes CPUArchState cleanup elfload cleanup fix for uclibc-ng and by musl Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Fabrice Fontaine (1):

Re: [PATCH v4 03/17] target/m68k: Fix coding style in m68k_interrupt_all

Le 30/04/2022 à 19:53, Richard Henderson a écrit : Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Signed-of

Re: [PULL 0/1] Block patches

On 5/25/22 05:49, Stefan Hajnoczi wrote: The following changes since commit 0cac736e73723850a99e5142e35d14d8f8efb232: Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into staging (2022-05-24 15:55:12 -0700) are available in the Git repository at:

Re: [PATCH] target/arm/hvf: Include missing "cpregs.h"

On 5/25/22 09:19, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Fix when building HVF on macOS Aarch64: target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you mean 'ARMCPUInfo'? const ARMCPRegInfo *ri; ^~~~

Re: [PATCH v4 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15

Le 30/04/2022 à 19:53, Richard Henderson a écrit : These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c

Re: [RFC PATCH v5 0/3] Sysbus device generic QAPI plug support

On 25/05/2022 12:45, Peter Maydell wrote: On Wed, 25 May 2022 at 10:51, Damien Hedde wrote: On 5/24/22 19:44, Mark Cave-Ayland wrote: Sorry for coming late into this series, however one of the things I've been thinking about a lot recently is that with the advent of QOM and qdev, is there rea

Re: [PATCH v4 15/17] linux-user/strace: Fix print_syscall_err

Le 30/04/2022 à 19:53, Richard Henderson a écrit : Errors are not all negative numbers, but only the top 4k. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/strace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace

[PULL 00/17] Misc patches for 2022-05-25

The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d: Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you t

[PULL 02/17] hostmem: default the amount of prealloc-threads to smp-cpus

From: Jaroslav Jindrak Prior to the introduction of the prealloc-threads property, the amount of threads used to preallocate memory was derived from the value of smp-cpus passed to qemu, the amount of physical cpus of the host and a hardcoded maximum value. When the prealloc-threads property was

[PULL 08/17] hw/audio/ac97: Remove unimplemented reset functions

From: BALATON Zoltan The warm_reset() and cold_reset() functions are not implemented and do nothing so no point in calling them or keep around as dead code. Therefore remove them for now. Signed-off-by: BALATON Zoltan Reviewed-by: Víctor Colombo Message-Id: Signed-off-by: Paolo Bonzini ---

[PULL 01/17] target/i386: Remove LBREn bit check when access Arch LBR MSRs

From: Yang Weijiang Live migration can happen when Arch LBR LBREn bit is cleared, e.g., when migration happens after guest entered SMM mode. In this case, we still need to migrate Arch LBR MSRs. Signed-off-by: Yang Weijiang Message-Id: <20220517155024.33270-1-weijiang.y...@intel.com> Signed-off

[PULL 03/17] thread-pool: optimize scheduling of completion bottom half

The completion bottom half was scheduled within the pool->lock critical section. That actually results in worse performance, because the worker thread can run its own small critical section and go to sleep before the bottom half starts running. Note that this simple change does not produce an imp

[PULL 04/17] thread-pool: replace semaphore with condition variable

Since commit f9fc8932b1 ("thread-posix: remove the posix semaphore support", 2022-04-06) QemuSemaphore has its own mutex and condition variable; this adds unnecessary overhead on I/O with small block sizes. Check the QTAILQ directly instead of adding the indirection of a semaphore's count. Using

[PULL 07/17] hw/audio/ac97: Coding style fixes to avoid checkpatch errors

From: BALATON Zoltan Signed-off-by: BALATON Zoltan Reviewed-by: Víctor Colombo Message-Id: <62862a057e9c9ec0bb45248b2b9a3a1babb346a6.1650706617.git.bala...@eik.bme.hu> Signed-off-by: Paolo Bonzini --- hw/audio/ac97.c | 727 1 file changed, 357

[PULL 15/17] i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls

From: Vitaly Kuznetsov KVM kind of supported "extended GVA ranges" (up to 4095 additional GFNs per hypercall) since the implementation of Hyper-V PV TLB flush feature (Linux-4.18) as regardless of the request, full TLB flush was always performed. "Extended GVA ranges for TLB flush hypercalls" fea

[PULL 05/17] thread-pool: remove stopping variable

Just setting the max threads to 0 is enough to stop all workers. Message-Id: <20220514065012.1149539-4-pbonz...@redhat.com> Reviewed-by: Stefan Hajnoczi Reviewed-by: Nicolas Saenz Julienne Signed-off-by: Paolo Bonzini --- util/thread-pool.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletio

[PULL 06/17] contrib/elf2dmp: add ELF dump header checking

From: Viktor Prutyanov Add ELF header checking to prevent processing input file which is not QEMU x86_64 guest memory dump or even not ELF. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1013 Signed-off-by: Viktor Prutyanov Reviewed-by: Richard Henderson Message-Id: <20220520084339.1

[PULL 16/17] i386: Hyper-V Direct TLB flush hypercall

From: Vitaly Kuznetsov Hyper-V TLFS allows for L0 and L1 hypervisors to collaborate on L2's TLB flush hypercalls handling. With the correct setup, L2's TLB flush hypercalls can be handled by L0 directly, without the need to exit to L1. Signed-off-by: Vitaly Kuznetsov Message-Id: <20220525115949

[PULL 09/17] hw/audio/ac97: Remove unneeded local variables

From: BALATON Zoltan Several functions have a local variable that is just a copy of one of the function parameters. This is unneeded complication so just get rid of these. Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell Message-Id: Signed-off-by: Paolo Bonzini --- hw/audio/ac97.c

[PULL 13/17] i386: Hyper-V Enlightened MSR bitmap feature

From: Vitaly Kuznetsov The newly introduced enlightenment allow L0 (KVM) and L1 (Hyper-V) hypervisors to collaborate to avoid unnecessary updates to L2 MSR-Bitmap upon vmexits. Signed-off-by: Vitaly Kuznetsov Message-Id: <20220525115949.1294004-3-vkuzn...@redhat.com> Signed-off-by: Paolo Bonzin

[PULL 10/17] target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host

From: "Maciej S. Szmigiero" Since KVM commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled") it is not possible to disable MPX on a "-cpu host" just by adding "-mpx" there if the host CPU does indeed support MPX. QEMU will fail to set MSR_IA32_VMX_TRUE_{EXIT,EN

Re: [PATCH v4 16/17] linux-user/strace: Adjust get_thread_area for m68k

Le 30/04/2022 à 19:53, Richard Henderson a écrit : Unlike i386, m68k get_thread_area has no arguments. Signed-off-by: Richard Henderson --- linux-user/strace.list | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b

[PULL 11/17] ide_ioport_read: Return lower octet of data register instead of 0xFF

From: Lev Kujawski Prior to this patch, the pre-GRUB Solaris x86 bootloader would fail to load on QEMU with the following screen output: SunOS Secondary Boot version 3.00 prom_panic: Could not mount filesystem. Entering boot debugger: [136419]: _ This occurs because the bootloader issues an AT

Re: [PATCH v4 17/17] target/m68k: Mark helper_raise_exception as noreturn

Le 30/04/2022 à 19:53, Richard Henderson a écrit : Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Signed-off-by: Richard Henderson --- target/m68k/helper.h| 2 +- target/m68k/op_helper.c | 5 +++-- 2 files changed, 4

[PULL 12/17] i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES

From: Vitaly Kuznetsov Previously, HV_CPUID_NESTED_FEATURES.EAX CPUID leaf was handled differently as it was only used to encode the supported eVMCS version range. In fact, there are also feature (e.g. Enlightened MSR-Bitmap) bits there. In preparation to adding these features, move HV_CPUID_NEST

[PULL 14/17] i386: Hyper-V XMM fast hypercall input feature

From: Vitaly Kuznetsov Hyper-V specification allows to pass parameters for certain hypercalls using XMM registers ("XMM Fast Hypercall Input"). When the feature is in use, it allows for faster hypercalls processing as KVM can avoid reading guest's memory. KVM supports the feature since v5.14. R

[PULL 17/17] i386: docs: Convert hyperv.txt to rST

From: Vitaly Kuznetsov rSTify docs/hyperv.txt and link it from docs/system/target-i386.rst. Signed-off-by: Vitaly Kuznetsov Message-Id: <20220525115949.1294004-7-vkuzn...@redhat.com> Signed-off-by: Paolo Bonzini --- docs/hyperv.txt | 303 docs/

Re: [PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

On 5/24/22 18:23, Alejandro Jimenez wrote: > On 5/24/2022 3:48 PM, Moger, Babu wrote: >> >> On 5/24/22 10:19, Igor Mammedov wrote: >>> On Tue, 24 May 2022 11:10:18 -0400 >>> Igor Mammedov wrote: >>> >>> CCing AMD folks as that might be of interest to them >> >> I am trying to recreate the bug on

Re: [PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

On 5/25/22 02:05, Igor Mammedov wrote: > On Tue, 24 May 2022 14:48:29 -0500 > "Moger, Babu" wrote: > >> On 5/24/22 10:19, Igor Mammedov wrote: >>> On Tue, 24 May 2022 11:10:18 -0400 >>> Igor Mammedov wrote: >>> >>> CCing AMD folks as that might be of interest to them >> I am trying to recreat

Re: [PATCH v4 17/17] target/m68k: Mark helper_raise_exception as noreturn

On 5/25/22 12:45, Laurent Vivier wrote: +DEF_HELPER_2(raise_exception, noreturn, env, i32) ... -static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +G_NORETURN static void +raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)   {   CPUState *cs = env_cpu(env

Re: [PATCH v9 08/12] target/hexagon: import flex/bison to docker files

On 5/25/22 18:38, Alex Bennée wrote: Richard Henderson writes: On 5/25/22 05:29, Anton Johansson wrote: For clarity's sake, here are the exact steps taken to produce this patch:     1. Update QEMU's libvirt-ci to the commit https://gitlab.com/libvirt/libvirt-ci/-/commit/43927ff508e8ecb1ac2

Re: [PATCH v9 08/12] target/hexagon: import flex/bison to docker files

On 5/25/22 13:14, Anton Johansson wrote: Just to make sure I understood you correctly, I should:     1. Make a standalone patch that updates libvirt-ci and runs     the refresh script, in case any package mappings changed     2. Change this patch to add flex/bison to QEMU's qemu.yml,   

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