[PULL 00/19] aspeed queue

The following changes since commit f5643914a9e8f79c606a76e6a9d7ea82a3fc3e65: Merge tag 'pull-9p-20220501' of https://github.com/cschoenebeck/qemu into staging (2022-05-01 07:48:11 -0700) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspee

[PULL 01/19] hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function

From: Steven Lee AST2600's HPLL register offset and bit definition are different from AST2500. Add a hpll calculation function and an apb frequency calculation function based on SCU200 register description in ast2600v11.pdf. Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater [ clg: checkp

[PULL 09/19] aspeed/timer: Add AST1030 support

From: Steven Lee ast1030 tmc(timer controller) is identical to ast2600 tmc. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220401083850.15266-6-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- include/hw/

[PULL 12/19] aspeed: Add an AST1030 eval board

From: Jamin Lin The image should be supplied with ELF binary. $ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220401083850.15266-9-jamin_...@aspeedtech.com>

[PULL 13/19] test/avocado/machine_aspeed.py: Add ast1030 test case

From: Jamin Lin Add test case to test "ast1030-evb" machine with zephyr os Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220401083850.15266-10-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- tests/avoca

[PULL 03/19] aspeed: sbc: Correct default reset values

From: Joel Stanley In order to correctly report secure boot running firmware, these values must be set. They are taken from a running machine when secure boot is enabled. We don't yet have documentation from ASPEED on what they mean. Set the raw values for now, and in the future improve the mode

[PULL 19/19] aspeed/hace: Support AST1030 HACE

From: Steven Lee Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE engine. Signed-off-by: Steven Lee Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_hace.h | 2 ++ hw/misc/aspeed_hace.c | 20 2 files changed, 22 insertions(+) diff

[PULL 02/19] hw: aspeed_scu: Introduce clkin_25Mhz attribute

From: Steven Lee AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute for aspeed_scu_get_clkin() to return the correct clkin for ast2600. Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220315075753.8591-3-steven_...@aspeedtech.com> Signed-off-by: Cédric Le Goa

[PULL 15/19] aspeed/hace: Support HMAC Key Buffer register.

From: Steven Lee Support HACE28: Hash HMAC Key Buffer Base Address Register. Signed-off-by: Troy Lee Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220426021120.28255-2-steven_...@aspeedtech.com> Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_hace.h | 1 +

[PULL 17/19] tests/qtest: Add test for Aspeed HACE accumulative mode

From: Steven Lee This add two addition test cases for accumulative mode under sg enabled. The input vector was manually craft with "abc" + bit 1 + padding zeros + L. The padding length depends on algorithm, i.e. SHA512 (1024 bit), SHA256 (512 bit). The result was calculated by command line sha5

[PULL 18/19] hw/gpio/aspeed_gpio: Fix QOM pin property

From: Peter Delevoryas I was setting gpioV4-7 to "1110" using the QOM pin property handler and noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too. (qemu) qom-set /machine/soc/gpio gpioV4 true (qemu) qom-set /machine/soc/gpio gpioV5 true (qemu) qom-set /machine/soc/g

[PULL 04/19] aspeed: Add eMMC Boot Controller stub

From: Joel Stanley Guest code (u-boot) pokes at this on boot. No functionality is required for guest code to work correctly, but it helps to document the region being read from. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Message-Id: <20220318092211.723938-1-j...@jms.id.au> Signe

[PATCH qemu v14 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as tail eleme

[PATCH qemu v14 02/15] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff

[PATCH qemu v14 03/15] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PULL 05/19] aspeed/adc: Add AST1030 support

From: Steven Lee Per ast1030_v7.pdf, AST1030 ADC engine is identical to AST2600's ADC. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220401083850.15266-2-jamin_...@aspeedtech.com> Signed-off-by: Cédric Le Goater ---

[PATCH qemu v14 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f67ec1f249..a319cda969 100644 --- a/

[PULL 06/19] aspeed/smc: Add AST1030 support

From: Steven Lee AST1030 spi controller's address decoding unit is 1MB that is identical to ast2600, but fmc address decoding unit is 512kb. Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller. In addition, add ast1030 fmc, spi1, and spi2 class init handler. Signed-off-by: Tr

[PATCH qemu v14 04/15] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PATCH qemu v14 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) di

[PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector

[PATCH qemu v14 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 11 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 22 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v2 1/8] qapi: Drop stray trailing symbol

Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster --- qapi/run-state.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qapi/run-state.json b/qapi/run-state.json index 8124220bd9..15d6c9a2ed 100644 --- a/qapi/run-state.json +++ b/qapi/run-state.json @@ -348,7 +

[PULL 07/19] aspeed/wdt: Fix ast2500/ast2600 default reload value

From: Steven Lee Per ast2500_2520_datasheet_v1.8 and ast2600v11.pdf, the default value of WDT00 and WDT04 is 0x014FB180 for ast2500/ast2600. Add default_status and default_reload_value attributes for storing counter status and reload value as they are different from ast2400. Signed-off-by: Troy

[PATCH qemu v14 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 29 +++ target/riscv/internals.h| 5 +- target/risc

[PULL 08/19] aspeed/wdt: Add AST1030 support

From: Steven Lee AST1030 wdt controller is similiar to AST2600's wdt, but it has extra registers. Introduce ast1030 object class and increse the number of regs(offset) of ast1030 model. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater M

[PATCH v2 6/8] qapi: Drop unnecessary whitespace in comments

The only instances that get changed are those in which the additional whitespace was not (or couldn't possibly be) used for alignment purposes. Signed-off-by: Andrea Bolognani --- qapi/block-core.json | 24 qapi/block-export.json | 2 +- qapi/block.json| 2 +-

[PATCH qemu v14 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c| 30 ++

[PATCH qemu v14 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 23 ++ target/riscv/vector_helper.c| 40 + 2 files changed, 63 insertions(+) diff --git a/target/riscv/insn_trans/

[PULL 10/19] aspeed/scu: Add AST1030 support

From: Steven Lee Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider selection is defined in SCU310[11:8]. Add a get_apb_freq function and a class init handler for ast1030. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goa

[PATCH qemu v14 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c| 440 +---

[PATCH v2 7/8] qapi: Reduce whitespace used for alignment in comments

Use the minimum number of spaces necessary. Signed-off-by: Andrea Bolognani --- qapi/block-core.json | 38 +++--- qapi/control.json| 10 +- qapi/crypto.json | 42 +- qapi/ui.json | 16

[PATCH qemu v14 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PULL 11/19] aspeed/soc : Add AST1030 support

From: Steven Lee The embedded core of AST1030 SoC is ARM Coretex M4. It is hard to be integrated in the common Aspeed Soc framework. We introduce a new ast1030 class with instance_init and realize handlers. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by

[PATCH v2 8/8] qapi: Stop using whitespace for alignment in comments

Perfectly aligned things look pretty, but keeping them that way as the schema evolves requires churn, and in some cases newly-added lines are not aligned properly. Overall, trying to align things is just not worth the trouble. Signed-off-by: Andrea Bolognani --- qapi/block-core.json | 43 ++

Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V

On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote: > > On Tue, Apr 19, 2022 at 9:51 AM Daniel P. Berrangé > wrote: > > > > On Mon, Apr 11, 2022 at 07:10:06PM -0700, Atish Patra wrote: > > > > > > The RISC-V virt machine has helped RISC-V software eco system to evolve > > > at a > > > rapid pace

[PULL 14/19] hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model

From: Jae Hyun Yoo Current fmc model of AST2500 EVB and AST2600 EVB can't emulate quad mode properly so fix them using equivalent mx25l25635e and mx66u51235f respectively. These default settings still can be overridden using the 'fmc-model' command line option. Reported-by: Graeme Gregory Sign

Fio regression caused by f9fc8932b11f3bcf2a2626f567cb6fdd36a33a94

Hello Mike, Paolo, others, in my perf pipeline I noticed a regression bisected to the f9fc8932b11f3bcf2a2626f567cb6fdd36a33a94 - "thread-posix: remove the posix semaphore support" commit and I'd like to ask you to verify it might have caused that and eventually consider fixing it. The regressio

[PATCH v2 4/8] qapi: Drop unnecessary empty lines in comments

Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster --- qapi/block-core.json | 4 qapi/block.json | 1 - qapi/char.json| 1 - qapi/common.json | 2 -- qapi/control.json | 2 -- qapi/crypto.json | 1 - qapi/machine.json | 2 -- qapi/migratio

[PATCH v2 0/8] qapi: Primarily whitespace tweaks

If patch 8/8 is accepted, 7/8 should be squashed into it to reduce churn. Changes from [v1]: * use a more fine-grained split for whitespace changes. [v1] https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg05406.html Andrea Bolognani (8): qapi: Drop stray trailing symbol qapi: Fix co

[PULL 16/19] aspeed/hace: Support AST2600 HACE

From: Steven Lee The aspeed ast2600 accumulative mode is described in datasheet ast2600v10.pdf section 25.6.4: 1. Allocating and initiating accumulative hash digest write buffer with initial state. * Since QEMU crypto/hash api doesn't provide the API to set initial state of hash li

Re: [RFC PATCH v1 0/8] qapi: add generator for Golang interface

Andrea Bolognani writes: > On Mon, May 02, 2022 at 01:46:23PM +0200, Markus Armbruster wrote: >> Andrea Bolognani writes: >> >> > The wire protocol would still retain the unappealing name, but at >> >> > least client libraries could hide the uglyness from users. >> >> >> >> At the price of mild

Re: [PATCH v3 3/3] nbd/server: Allow MULTI_CONN for shared writable exports

Am 02.05.2022 um 23:12 hat Eric Blake geschrieben: > On Fri, Apr 29, 2022 at 02:49:35PM +0200, Kevin Wolf wrote: > ... > > > Or a multi-pathed connection to network storage, where one QEMU > > > process accesses the network device, but those accesses may > > > round-robin which server they reach, a

[PATCH v2 2/8] qapi: Fix comment indentation

It should start on the very first column. Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster --- qapi/ui.json | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/qapi/ui.json b/qapi/ui.json index 059302a5ef..43e62efd76 100644 --- a/qa

[PATCH qemu v14 00/15] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH v2 5/8] qapi: Drop unnecessary empty lines outside of comments

Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster --- qapi/audio.json | 1 - qapi/block-core.json | 11 --- qapi/block.json | 3 --- qapi/char.json | 1 - qapi/control.json| 1 - qapi/crypto.json | 12 qapi/job

Re: [PATCH 6/7] qapi: Drop unnecessary horizontal spacing in comments

On Mon, May 02, 2022 at 07:24:53PM +0200, Markus Armbruster wrote: > Andrea Bolognani writes: > > On Mon, May 02, 2022 at 10:50:07AM +0200, Markus Armbruster wrote: > >> I doubt changing to a different alignment now is useful. The next > >> patch, however, drops the alignment entirely. Possibly

[PATCH qemu v14 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8

[PATCH qemu v14 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 44 + target/riscv/vector_helper.c| 20 +++ 2 files changed, 64 insertions(+) diff --git a/target/riscv/insn_trans/tra

Re: [PATCH 1/2] acpi/nvdimm: Create _LS{I,R,W} method for NVDIMM device

On Fri, 29 Apr 2022 17:01:47 +0800 Robert Hoo wrote: > On Wed, 2022-04-27 at 16:34 +0200, Igor Mammedov wrote: > > On Tue, 12 Apr 2022 14:57:52 +0800 > > Robert Hoo wrote: > > > > > Since ACPI 6.2, previous NVDIMM/_DSM funcions "Get Namespace Label > > > Data > > > Size (function index 4)", "

[PATCH] qapi: Fix incorrect Since tags

The missing colon causes them to be interpreted as regular text. Signed-off-by: Andrea Bolognani --- qapi/crypto.json | 2 +- qapi/misc.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qapi/crypto.json b/qapi/crypto.json index 1ec54c15ca..529aa730d4 100644 --- a/qapi

Re: [PULL 06/11] QIOChannelSocket: Implement io_writev zero copy flag & io_flush for CONFIG_LINUX

* Leonardo Bras Soares Passos (lsoar...@redhat.com) wrote: > Hello Dave, > > On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert > wrote: > > > > Leo: > > Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY > > one I guess is the simpler one; I think Stefanha managed to find

[PATCH v2 3/8] qapi: Add missing separators between sections

This only affects readability. The generated documentation doesn't change. Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster --- qapi/block-core.json | 5 + qapi/block.json | 1 + qapi/crypto.json | 7 +++ qapi/machine.json| 1 + qapi/migration.json | 4

Re: [PATCH v2 6/8] qapi: Drop unnecessary whitespace in comments

Andrea Bolognani writes: > The only instances that get changed are those in which the > additional whitespace was not (or couldn't possibly be) used for > alignment purposes. > > Signed-off-by: Andrea Bolognani This mixes complete no-brainers with "I consider it an improvement, but folks might

Re: [PATCH] qapi: Fix incorrect Since tags

Andrea Bolognani writes: > The missing colon causes them to be interpreted as regular > text. > > Signed-off-by: Andrea Bolognani > --- > qapi/crypto.json | 2 +- > qapi/misc.json | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/qapi/crypto.json b/qapi/crypto.json >

Re: [PATCH v8 2/5] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()

On Mon, 2 May 2022 18:07:00 +0800 Gavin Shan wrote: > Hi Igor, > > On 5/2/22 4:52 PM, Igor Mammedov wrote: > > On Mon, 25 Apr 2022 11:27:59 +0800 > > Gavin Shan wrote: > > > >> The CPU topology isn't enabled on arm/virt machine yet, but we're > >> going to do it in next patch. After the CPU

Re: [PATCH] target/openrisc: implement shutdown and reset helpers

On Mon, May 02, 2022 at 04:57:43PM -0700, Richard Henderson wrote: > On 5/2/22 15:52, Jason A. Donenfeld wrote: > > OpenRISC defines various nop instructions in or1k as meaning shutdown or > > reset. Implement these in TCG. This has been tested with Linux and > > confirmed to work. > > No, OpenRIS

Re: [PATCH v8 3/5] hw/arm/virt: Consider SMP configuration in CPU topology

On Mon, 25 Apr 2022 11:28:00 +0800 Gavin Shan wrote: > Currently, the SMP configuration isn't considered when the CPU > topology is populated. In this case, it's impossible to provide > the default CPU-to-NUMA mapping or association based on the socket > ID of the given CPU. > > This takes accou

Re: [RFC PATCH v2 0/8] Removal of AioContext lock, bs->parents and ->children: new rwlock

Am 02.05.2022 um 10:02 hat Emanuele Giuseppe Esposito geschrieben: > > > Am 30/04/2022 um 07:17 schrieb Stefan Hajnoczi: > > On Thu, Apr 28, 2022 at 11:56:09PM +0200, Emanuele Giuseppe Esposito wrote: > >> > >> > >> Am 28/04/2022 um 12:45 schrieb Stefan Hajnoczi: > >>> On Wed, Apr 27, 2022 at 08:

Re: [PATCH 0/2] build improvments

On Fri, Apr 29, 2022 at 12:10:34AM +0200, Paolo Bonzini wrote: > On 4/28/22 20:21, Konstantin Kostiuk wrote: > > Konstantin Kostiuk (2): > >configure: Add cross prefix for widl tool > >qga-vss: always build qga-vss.tlb when qga-vss.dll is built > > > > configure | 3 +++ >

Re: [PATCH v8 1/5] qapi/machine.json: Add cluster-id

On Mon, 25 Apr 2022 11:27:58 +0800 Gavin Shan wrote: > This adds cluster-id in CPU instance properties, which will be used > by arm/virt machine. Besides, the cluster-id is also verified or > dumped in various spots: > > * hw/core/machine.c::machine_set_cpu_numa_node() to associate > CPU w

Re: [PATCH] tests/tcg/s390x: Use a different PCRel32 notation in branch-relative-long.c

On 02/05/2022 18.48, Ilya Leoshkevich wrote: Binutils >=2.37 and Clang do not accept (. - 0x1) PCRel32 constants. While this looks like a bug that needs fixing, use a different notation (-0x1) as a workaround. Reported-by: Thomas Huth Signed-off-by: Ilya Leoshkevich --- tests

Re: [PATCH 2/3] ui/gtk: detach_all option for making all VCs detached upon starting

On Thu, Apr 28, 2022 at 04:13:03PM -0700, Dongwon Kim wrote: > With "detach-all=on" for display, QEMU starts with all VC windows > detached automatically. > > If used with "full-screen=on", it places individual windows (from > top window) starting from monitor 0 or monitor n in case monitor=n. >

Re: [PATCH] target/openrisc: implement shutdown and reset helpers

On Tue, May 03, 2022 at 10:54:41AM +0200, Jason A. Donenfeld wrote: > On Mon, May 02, 2022 at 04:57:43PM -0700, Richard Henderson wrote: > > On 5/2/22 15:52, Jason A. Donenfeld wrote: > > > OpenRISC defines various nop instructions in or1k as meaning shutdown or > > > reset. Implement these in TCG.

Re: [PATCH 1/3] ui/gtk: new param monitor to specify target monitor for launching QEMU

On Thu, Apr 28, 2022 at 04:13:02PM -0700, Dongwon Kim wrote: > Introducing a new integer parameter to specify the monitor where the > Qemu window is placed upon launching. > > Monitor can be any number between 0 and (total number of monitors - 1). > > It can be used together with full-screen=on,

Re: [PATCH 3/3] ui/gtk: specify detached window's size and location

On Thu, Apr 28, 2022 at 04:13:04PM -0700, Dongwon Kim wrote: > Specify location and size of detached window based on top level > window's location and size info when detachment happens. Can you explain what problem is being solved by this change ? What's wrong with default size/placement logic ?

Re: [PATCH] hw/openrisc: use right OMPIC size variable

On Mon, May 02, 2022 at 04:59:47PM -0700, Richard Henderson wrote: > On 5/2/22 16:28, Jason A. Donenfeld wrote: > > This appears to be a copy and paste error. The UART size was used > > instead of the much smaller OMPIC size. > > > > Signed-off-by: Jason A. Donenfeld > > --- > > hw/openrisc/open

Re: [PATCH v3 2/3] block: improve block_dirty_bitmap_merge(): don't allocate extra bitmap

Am 01.04.2022 um 12:08 hat Vladimir Sementsov-Ogievskiy geschrieben: > We don't need extra bitmap. All we need is to backup the original > bitmap when we do first merge. So, drop extra temporary bitmap and work > directly with target and backup. > > Still to keep old semantics, that on failure tar

[PATCH v1] vga: avoid crash if no default vga card

QEMU in some arch will crash when executing -vga help command, because there is no default vga model. Add check to this case and avoid crash. Signed-off-by: Guo Zhi --- softmmu/vl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/softmmu/vl.c b/softmmu/vl.c index c2919579f

Re: [PATCH v3 1/3] block: block_dirty_bitmap_merge(): fix error path

Am 01.04.2022 um 12:08 hat Vladimir Sementsov-Ogievskiy geschrieben: > At the end we ignore failure of bdrv_merge_dirty_bitmap() and report > success. And still set errp. That's wrong. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > Reviewed-by: Nikita Lapshin Reviewed-by: Kevin Wolf

Re: [PATCH v3 3/3] block: simplify handling of try to merge different sized bitmaps

Am 01.04.2022 um 12:08 hat Vladimir Sementsov-Ogievskiy geschrieben: > We have too much logic to simply check that bitmaps are of the same > size. Let's just define that hbitmap_merge() and > bdrv_dirty_bitmap_merge_internal() require their argument bitmaps be of > same size, this simplifies things

Re: [RFC PATCH v1 0/8] qapi: add generator for Golang interface

On Tue, May 03, 2022 at 09:57:27AM +0200, Markus Armbruster wrote: > Andrea Bolognani writes: > > I still feel that 1) users of a language SDK will ideally not need to > > look at the QAPI schema or wire chatter too often > > I think the most likely point of contact is the QEMU QMP Reference > Man

Re: [PATCH] hw/dma: Add Xilinx AXI CDMA

On Tue, May 3, 2022 at 3:16 AM Frank Chang wrote: > On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias > wrote: > >> On Thu, Apr 28, 2022 at 5:43 PM wrote: >> >>> From: Frank Chang >>> >>> Add Xilinx AXI CDMA model, which follows >>> AXI Central Direct Memory Access v4.1 spec: >>> https://docs.x

Re: [PATCH 0/2] build improvments

Hi Daniel, This was my mistake when I sent patches. Thanks for your comment. Best Regards, Konstantin Kostiuk. On Tue, May 3, 2022 at 11:59 AM Daniel P. Berrangé wrote: > On Fri, Apr 29, 2022 at 12:10:34AM +0200, Paolo Bonzini wrote: > > On 4/28/22 20:21, Konstantin Kostiuk wrote: > > > Konst

[PATCH v2] hw/openrisc: use right OMPIC size variable

This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too and doesn't allow the IPI to work in Linux. So set it to the old value. Signed-off-by: Jason A. Donenfeld --- hw/openrisc/openrisc_sim.c | 4

Re: [PATCH v7 00/22] host: Support macOS 12

On 3/7/22 12:17 AM, Philippe Mathieu-Daudé wrote: > From: Philippe Mathieu-Daudé > > Few patches to be able to build QEMU on macOS 12 (Monterey). > > Missing review: > 0006-hvf-Fix-OOB-write-in-RDTSCP-instruction-decode.patch > 0013-osdep-Avoid-using-Clang-specific-__builtin_available.patch >

Re: [PATCH] qapi: Fix incorrect Since tags

On Tue, May 03, 2022 at 10:44:37AM +0200, Markus Armbruster wrote: > I posted a more complete fix as "[PATCH] qapi: Fix malformed "Since:" > section tags", and you even reviewed it :) Oh boy, I clearly need more coffee. Sorry for the noise :/ -- Andrea Bolognani / Red Hat / Virtualization

Re: [PATCH-for-6.2 0/2] hw/block/fdc: Fix CVE-2021-3507

Am 23.03.2022 um 03:25 hat John Snow geschrieben: > On Fri, Mar 18, 2022 at 2:50 PM Thomas Huth wrote: > > > > On 10/03/2022 18.53, Jon Maloy wrote: > > > > > > On 3/10/22 12:14, Thomas Huth wrote: > > >> On 06/02/2022 20.19, Jon Maloy wrote: > > >>> Trying again with correct email address. > > >>

Re: [PATCH] hw/openrisc: use right OMPIC size variable

On Tue, May 03, 2022 at 06:19:29PM +0900, Stafford Horne wrote: > On Mon, May 02, 2022 at 04:59:47PM -0700, Richard Henderson wrote: > > On 5/2/22 16:28, Jason A. Donenfeld wrote: > > > This appears to be a copy and paste error. The UART size was used > > > instead of the much smaller OMPIC size. >

Re: [PATCH v2 13/26] tests: replace pipe() with g_unix_open_pipe(CLOEXEC)

On Tue, Apr 26, 2022 at 01:27:02PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Suggested-by: Daniel P. Berrangé > Signed-off-by: Marc-André Lureau > --- > tests/qtest/ivshmem-test.c| 5 +++-- > tests/unit/test-io-channel-file.c | 2 +- > 2 files changed, 4 i

Re: [PATCH v2 15/26] virtiofsd: replace pipe() with g_unix_open_pipe(CLOEXEC)

On Tue, Apr 26, 2022 at 01:27:04PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Suggested-by: Daniel P. Berrangé > Signed-off-by: Marc-André Lureau > --- > tools/virtiofsd/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Daniel P. Berran

Re: [PATCH for-7.0 0/2] block/vmdk: Fix reopening bs->file

Am 14.03.2022 um 17:27 hat Hanna Reitz geschrieben: > Hi, > > A couple of months ago I noticed that changing a vmdk node’s file child > through blockdev-reopen would crash qemu. I started writing a fix at > some point, got distracted, but now here it is. Thanks, fixed up a merge conflict with 28

Re: [PATCH v2 16/26] io: replace pipe() with g_unix_open_pipe(CLOEXEC)

On Tue, Apr 26, 2022 at 01:27:05PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Suggested-by: Daniel P. Berrangé > Signed-off-by: Marc-André Lureau > --- > io/channel-command.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Daniel P. Berran

Re: [PATCH v2 20/26] io: replace qemu_set{_non}block()

On Tue, Apr 26, 2022 at 01:27:09PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Those calls are non-socket fd, or are POSIX-specific. Use the dedicated > GLib API. (qemu_set_nonblock() is for socket-like) > > Signed-off-by: Marc-André Lureau > --- > io/channel-comman

[RFC PATCH 3/4] tcg/ppc: Optimize memory ordering generation with lwsync

lwsync orders more than just LD_LD, importantly it matches x86 and s390 default memory ordering. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 2 ++ tcg/ppc/tcg-target.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h

Re: [PATCH v2 19/26] chardev: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:08PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Those calls are either for non-socket fd, or are POSIX-specific. Use the > dedicated GLib API. (qemu_set_nonblock() is for socket-like) > > Signed-off-by: Marc-André Lureau > --- > charde

[RFC PATCH 1/4] target/ppc: Fix eieio memory ordering semantics

The generated eieio memory ordering semantics do not match the instruction definition in the architecture. Add a big comment to explain this strange instruction and correct the memory ordering behaviour. Signed-off: Nicholas Piggin --- target/ppc/translate.c | 26 +- 1 fi

Re: [PATCH v2 21/26] qga: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:10PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > The call is POSIX-specific. Use the dedicated GLib API. > > Signed-off-by: Marc-André Lureau > --- > qga/commands-posix.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) Rev

[RFC PATCH 2/4] tcg/ppc: ST_ST memory ordering is not provided with eieio

eieio does not provide ordering between stores to CI memory and stores to cacheable memory so it can't be used as a general ST_ST barrier. Signed-of-by: Nicholas Piggin --- tcg/ppc/tcg-target.c.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target

Re: [PATCH v2 24/26] net: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:13PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Those calls are POSIX-specific. Use the dedicated GLib > API. (qemu_set_nonblock() is for socket-like) > > Signed-off-by: Marc-André Lureau > --- > net/tap.c | 33 +++-

Re: [PATCH v2 23/26] ui: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:12PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > The call is POSIX-specific. Use the dedicated GLib API. > > Signed-off-by: Marc-André Lureau > --- > ui/input-linux.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) Reviewed

[RFC PATCH 4/4] target/ppc: Implement lwsync with weaker memory ordering

This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync rather than sync. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 4 +++- target/ppc/cpu_init.c | 13 +++-- target/ppc/machine.c | 3 ++- target/ppc/translate.c | 8 +++- 4 files changed, 19 inser

Re: [PATCH v2 22/26] hw: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:11PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Those calls are non-socket fd, or are POSIX-specific. Use the dedicated > GLib API. (qemu_set_nonblock() is for socket-like) > > Signed-off-by: Marc-André Lureau > --- > hw/input/virtio-i

Re: [PATCH v2 25/26] tests: replace qemu_set_nonblock()

On Tue, Apr 26, 2022 at 01:27:14PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > The call is POSIX-specific. Use the dedicated GLib API. > > Signed-off-by: Marc-André Lureau > --- > tests/qtest/vhost-user-test.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(

Re: [PATCH 0/3] coroutine: use QEMU_DEFINE_STATIC_CO_TLS()

Am 07.03.2022 um 16:38 hat Stefan Hajnoczi geschrieben: > The coroutine implementation uses __thread variables internally. Compiler > optimizations may cache Thread-Local Storage values across > qemu_coroutine_yield(), leading to stale values being used after the coroutine > is re-entered from anot

Re: [RFC PATCH v1 0/8] qapi: add generator for Golang interface

Am 03.05.2022 um 11:40 hat Andrea Bolognani geschrieben: > So the issues preventing us from producing a "perfect" Go API are > > 1. inconsistent capitalization in type names > >-> could be addressed by simply changing the schema, as type > names do not travel on the wire > > 2. mis

Re: [PATCH v2 12/26] qga: replace pipe() with g_unix_open_pipe(CLOEXEC)

On Wed, Apr 27, 2022 at 12:24:44PM +0400, Marc-André Lureau wrote: > Hi > > On Wed, Apr 27, 2022 at 5:08 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > > > On 4/26/22 02:27, marcandre.lur...@redhat.com wrote: > > > From: Marc-André Lureau > > > > > > Suggested-by: Daniel P. Berr

Re: [PATCH v5 00/13] KVM: mm: fd-based approach for supporting KVM guest private memory

On Thursday 28 Apr 2022 at 20:29:52 (+0800), Chao Peng wrote: > > + Michael in case he has comment from SEV side. > > On Mon, Apr 25, 2022 at 07:52:38AM -0700, Andy Lutomirski wrote: > > > > > > On Mon, Apr 25, 2022, at 6:40 AM, Chao Peng wrote: > > > On Sun, Apr 24, 2022 at 09:59:37AM -0700, A

[PATCH v2] vga: avoid crash if no default vga card

QEMU in some arch will crash when executing -vga help command, because there is no default vga model. Add check to this case and avoid crash. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/978 Signed-off-by: Guo Zhi --- softmmu/vl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion

Re: [PATCH RFC 04/10] intel_iommu: Second Stage Access Dirty bit support

On 4/29/22 19:21, Peter Xu wrote: > On Fri, Apr 29, 2022 at 10:12:01AM +0100, Joao Martins wrote: >> On 4/29/22 03:26, Jason Wang wrote: >>> On Fri, Apr 29, 2022 at 5:14 AM Joao Martins >>> wrote: @@ -3693,7 +3759,8 @@ static void vtd_init(IntelIOMMUState *s) /* TODO: read cap

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