We used to do off-by-one fixup for pss->page when finished one host huge page
transfer. That seems to be unnecesary at all. Drop it.
Cc: Keqian Zhu
Cc: Kunkun Jiang
Cc: Andrey Gruzdev
Signed-off-by: Peter Xu
---
migration/ram.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Temp pages will need to grow if we want to have multiple channels for postcopy,
because each channel will need its own temp page to cache huge page data.
Before doing that, cleanup the related code. No functional change intended.
Since at it, touch up the errno handling a little bit on the setup
In ram_load_postcopy() we'll try to detect non-same-page case and dump error.
This error is very helpful for debugging. Adding ramblock & offset into the
error log too.
Signed-off-by: Peter Xu
---
migration/ram.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/migrat
Based-on: <20211224065000.97572-1-pet...@redhat.com>
Human version - This patchset is based on:
https://lore.kernel.org/qemu-devel/20211224065000.97572-1-pet...@redhat.com/
This series can also be found here:
https://github.com/xzpeter/qemu/tree/postcopy-preempt
Abstract
This serie
Commit ba1b7c812c ("migration/ram: Optimize ram_save_host_page()") managed to
optimize host huge page use case by scanning the dirty bitmap when looking for
the next dirty small page to migrate.
However when updating the pss->page before returning from that function, we
used MIN() of these two val
Postcopy create threads. A common manner is we init a sem and use it to sync
with the thread. Namely, we have fault_thread_sem and listen_thread_sem and
they're only used for this.
Make it a shared infrastructure so it's easier to create yet another thread.
Signed-off-by: Peter Xu
---
migratio
This variable, along with its helpers, is used to detect whether multiple
channel will be supported for migration. In follow up patches, there'll be
other capability that requires multi-channels. Hence move it outside multifd
specific code and make it public. Meanwhile rename it from "multifd" t
This patch allows us to read the tid even without blocktime feature enabled.
It's useful when tracing postcopy fault thread on faulted pages to show thread
id too with the address.
Remove the comments - they're merely not helpful at all.
Signed-off-by: Peter Xu
---
migration/postcopy-ram.c | 14
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 7b42f6fd90..93ff43bb3f 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
Static variable is very unfriendly to threading of ram_block_from_stream().
Move it into MigrationIncomingState.
Make the incoming state pointer to be passed over to ram_block_from_stream() on
both caller sites.
Signed-off-by: Peter Xu
---
migration/migration.h | 3 ++-
migration/ram.c |
This patch enables postcopy-preempt feature.
It contains two major changes to the migration logic:
(1) Postcopy requests are now sent via a different socket from precopy
background migration stream, so as to be isolated from very high page
request delays
(2) For huge page enabled
Add a helper to detect whether postcopy has pending request.
Since at it, cleanup the code a bit, e.g. in unqueue_page() we shouldn't need
to check it again on queue empty because we're the only one (besides cleanup
code, which should never run during this process) that will take a request off
the
Hi!
The following changes since commit 69353c332c558cead5f8081d0bb69f989fe33fa3:
Merge remote-tracking branch
'remotes/konstantin/tags/qga-win32-pull-2022-01-10' into staging (2022-01-16
16:32:34 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-r
From: Ilya Leoshkevich
According to PoP, both 32- and 64-bit shifts use lowest 6 address
bits. The current code special-cases 32-bit shifts to use only 5 bits,
which is not correct. For example, shifting by 32 bits currently
preserves the initial value, however, it's supposed zero it out
instead.
This patch simplifies unqueue_page() on both sides of it (itself, and caller).
Firstly, due to the fact that right after unqueue_page() returned true, we'll
definitely send a huge page (see ram_save_huge_page() call - it will _never_
exit before finish sending that huge page), so unqueue_page() do
From: Ilya Leoshkevich
Add a test for each shift instruction in order to to prevent
regressions.
Signed-off-by: Ilya Leoshkevich
Acked-by: David Hildenbrand
Message-Id: <20220112165016.226996-6-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/Makefile.target | 1 +
tests/t
From: Ilya Leoshkevich
SLDA operates on 64-bit values, so its sign bit index should be 63,
not 31.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Reported-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Reviewed-by: David Hildenbrand
Message-Id: <20220112165016.226996-2-...@l
Postcopy handles huge pages in a special way that currently we can only have
one "channel" to transfer the page.
It's because when we install pages using UFFDIO_COPY, we need to have the whole
huge page ready, it also means we need to have a temp huge page when trying to
receive the whole content
From: Eric Farman
Let's wait to mark the VCPU STOPPED until the possible
STORE STATUS operation is completed, so that we know the
CPU is fully stopped and done doing anything. (When we
also clear the possible sigp_order field for STOP orders.)
Suggested-by: David Hildenbrand
Signed-off-by: Eric
This boolean flag shows whether the current page during migration is triggered
by postcopy or not. Then in ram_save_host_page() and deeper stack we'll be
able to have a reference on the priority of this page.
Signed-off-by: Peter Xu
---
migration/ram.c | 6 ++
1 file changed, 6 insertions(+
From: Ilya Leoshkevich
An overflow occurs for SLAG when at least one shifted bit is not equal
to sign bit. Therefore, we need to check that `shift + 1` bits are
neither all 0s nor all 1s. The current code checks only `shift` bits,
missing some overflows.
Fixes: cbe24bfa91d2 ("target-s390: Conver
On 1/18/22 14:59, Mark Kanda wrote:
OK. Thank you Daniel and Paolo. I'll implement these changes for v3.
To clarify, the command should be
{ 'command': 'query-stats',
'data': 'StatsFilter',
'returns': 'StatsResults' }
so the "target" would be mandatory and there's one level less of
[This is a trivial patch, but due to the number of files it touches
I'm not using qemu-trivial@ route.]
For a long time, we assumed that libxml2 is neecessary for parallels
block format support (block/parallels*). However, this format actually
does not use libxml. Since this is the only user of li
From: Cornelia Huck
Split out some more specialized devices etc., so that we can build
smarter lists of people to be put on cc: in the future.
Signed-off-by: Cornelia Huck
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: David Hildenbrand
Acked-by: Christian Borntraeger
Acked-by: Thomas Huth
A
Firstly, postcopy already preempts precopy due to the fact that we do
unqueue_page() first before looking into dirty bits.
However that's not enough, e.g., when there're host huge page enabled, when
sending a precopy huge page, a postcopy request needs to wait until the whole
huge page that is sen
On 1/18/22 18:05, Thomas Huth wrote:
The fdt version test in meson.build uses a function from libfdt v1.4.7,
but we require version 1.5.1 nowadays. Thus use a function that has
been introduced in that version instead.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/822
Signed-off-by: Tho
From: Eric Farman
After the recent restructuring, I'd like to volunteer to help
in some of the s390 I/O areas.
Built on "[PATCH RFC v2] MAINTAINERS: split out s390x sections"
Signed-off-by: Eric Farman
Acked-by: Christian Borntraeger
Acked-by: Halil Pasic
Message-Id: <20220112164044.2210508-
On 1/18/22 21:38, Eric Auger wrote:
+
+typedef struct QGenericPCIBus {
+QOSGraphObject obj;
+QPCIBus bus;
+uint64_t gpex_pio_base;
+uint64_t ecam_alloc_ptr;
+} QGenericPCIBus;
+
+/*
+ * qpci_init_generic():
+ * @ret: A valid QGenericPCIBus * pointer
+ * @qts: The %QTestState
+ * @
From: Marc Hartmayer
In the past s390 used a fixed command line length of 896 bytes. This has changed
with the Linux commit 5ecb2da660ab ("s390: support command lines longer than 896
bytes"). There is now a parm area indicating the maximum command line size. This
parm area has always been initial
From: Nico Boehr
Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But,
as per the principles of operation, bit 5 is ignored in MSCH and bits 0,
1, 6 and 7 need to be zero.
As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used
by ioinst_handle_msch(), adjust th
From: Ilya Leoshkevich
SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
cout_s64() relies on o->out being the shift result, however,
wout_r1_D32() clobbers it.
Fix by using a temporary.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Signed-off-by: Ilya Leoshkevi
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
Using bdrv_do_drained_begin_quiesce() in bdrv_child_cb_drained_end()
bdrv_child_cb_drained_begin()
is not a good idea: the callback might be called when running
a drain in a coroutine, and bdrv_drained_begin_poll() does not
handle that case,
On 1/18/22 15:22, Markus Armbruster wrote:
So, supporting auto-generated trace points for qga qmp commands requires some
deeper refactoring.
Similar trouble with tests?
The normal case seems to be "generate trace code", with an exception for
cases where our build system defeats that. Agree?
On Wed, Jan 19, 2022 at 07:00:14AM -0500, Yang Zhong wrote:
> The SGX NUMA patches were merged into Qemu 7.0 release, we need
> clarify detailed version history information and also change
> some related comments, which make SGX related comments clearer.
>
> Signed-off-by: Yang Zhong
> ---
> qap
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
- First of all, inconsistency between block_job_create under
aiocontext lock that internally calls blk_insert_bs and therefore
bdrv_replace_child_noperm, and blk_insert_bs that is called two lines
above in the same test without aiocontext. There
On 1/18/22 15:47, Igor Mammedov wrote:
and what exactly this CPU ID is,
may QOM path pointing to VCPU instance would be better?
For x86 it would be the APIC ID but yes, having a QOM path is more
future proof. Thanks Igor for noting this.
Paolo
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
Depending on the options given to reopen_state,
bdrv_reopen_parse_file_or_backing could pick another bs
that could be from another graph, and thus not protected
by subtree_drained_begin called by the callers of this
function.
We can't simply dr
On Sat, Nov 13, 2021 at 07:47:20PM +0100, BALATON Zoltan wrote:
> On Mon, 8 Nov 2021, BALATON Zoltan wrote:
> > On Mon, 8 Nov 2021, Paolo Bonzini wrote:
> > > On 11/8/21 15:30, Paolo Bonzini wrote:
> > > > On 11/8/21 14:05, BALATON Zoltan wrote:
> > > > > When using ACPI on big endian machine (such
On Wed, Jan 19, 2022 at 09:43:23AM +0100, Paolo Bonzini wrote:
> On 1/18/22 15:47, Igor Mammedov wrote:
> > and what exactly this CPU ID is,
> > may QOM path pointing to VCPU instance would be better?
>
> For x86 it would be the APIC ID but yes, having a QOM path is more future
> proof. Thanks Ig
On Mon, Jan 17, 2022 at 06:37:31PM +0800, Yang Zhong wrote:
> On Thu, Jan 13, 2022 at 04:15:10PM +, Daniel P. Berrangé wrote:
> > On Wed, Dec 15, 2021 at 09:25:13PM +0100, Paolo Bonzini wrote:
> > > From: Yang Zhong
> > >
> > > Add the SGXEPCSection list into SGXInfo to show the multiple
> >
Copying the maintainers for block/parallels.c
On Wed, Jan 19, 2022 at 12:04:23PM +0300, Michael Tokarev wrote:
> [This is a trivial patch, but due to the number of files it touches
> I'm not using qemu-trivial@ route.]
>
> For a long time, we assumed that libxml2 is neecessary for parallels
> blo
On 25.10.2021 22:03, Alex Bennée wrote:
NDNF writes:
These patches adds the ability to generate files in drcov format.
Primary goal this scripts is to have coverage
logfiles thatwork in Lighthouse.
Queued with some fixes to plugins/next, thanks.
ping
On Wed, Jan 19, 2022 at 09:16:46AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 19, 2022 at 07:00:14AM -0500, Yang Zhong wrote:
> > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > clarify detailed version history information and also change
> > some related comments, which mak
Subject doesn't say what needs them: "block: drain block devices across
graph modifications"
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
Protect bdrv_replace_child_noperm, as it modifies the
graph by adding/removing elements to .children and .parents
list of a bs. Use the newly introduc
On Wed, Jan 19, 2022 at 05:22:59PM +0800, Yang Zhong wrote:
> On Wed, Jan 19, 2022 at 09:16:46AM +, Daniel P. Berrangé wrote:
> > On Wed, Jan 19, 2022 at 07:00:14AM -0500, Yang Zhong wrote:
> > > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > > clarify detailed version hist
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
job mutex will be used to protect the job struct elements and list,
replacing AioContext locks.
Right now use a shared lock for all jobs, in order to keep things
simple. Once the AioContext lock is gone, we can introduce per-job
locks.
Not eve
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
* Finally fully enable assert_bdrv_graph_writable(), checking also for the
drains, in patch 11.
Wow, this is definitely not just moving code around! It's great that
you could pull this off. It gives me a lot more confidence that the
loc
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
+/** Protected by job_mutex */
Technically not yet true. You can add this in patch 15 and at the same
time remove this one:
* Set to false by the job while the coroutine has yielded and may be
* re-entered by job_enter().
On 1/18/22 17:27, Emanuele Giuseppe Esposito wrote:
Same as the locked version, but use BDRV_POLL_UNLOCKED
... We are going to add drains to all graph modifications, and they are
generally performed without the AioContext lock taken.
Paolo
Signed-off-by: Emanuele Giuseppe Esposito
---
b
From: Miroslav Rezanina
GCC options -mlittle and -mlittle-endian are equivalent on ppc64
architecture. However, clang supports only -mlittle-endian option.
Use longer form in configure to properly support both GCC and clang
compiler.
Signed-off-by: Miroslav Rezanina
---
configure | 2 +-
1 fi
Damien Hedde writes:
> Hi Mirela,
>
> On 1/11/22 17:54, Mirela Grujic wrote:
>> Hi,
>>
>> While working on a prototype and configuring a whole machine using
>> QMP we run into the following scenario.
>>
>> Some device models use array properties.
A gift that keeps on giving...
>>
On Tue, 18 Jan 2022 at 23:30, Andre Przywara wrote:
> Looking at k-u-t's arm/gic.c and QEMU's hw/intc/arm_gic.c I see two
> problems here: QEMU implements word accesses as four successive calls to
> gic_dist_readb() - which is probably fine if that helps code design,
> but it won't allow it to act
Pavel Dovgalyuk writes:
> On 25.10.2021 22:03, Alex Bennée wrote:
>> NDNF writes:
>>
>>> These patches adds the ability to generate files in drcov format.
>>> Primary goal this scripts is to have coverage
>>> logfiles thatwork in Lighthouse.
>> Queued with some fixes to plugins/next, thanks.
On Wed, 19 Jan 2022 at 04:03, Alexey Kardashevskiy wrote:
>
>
>
> On 1/17/22 03:45, Peter Maydell wrote:
> > On Fri, 7 Jan 2022 at 07:29, Alexey Kardashevskiy wrote:
> >>
> >> "PowerPC Processor binding to IEEE 1275" says in
> >> "8.2.1. Initial Register Values" that the initial state is defined
> On 17 Jan 2022, at 15:30, Liviu Ionescu wrote:
>
> I will try to rebuild using --with-cocoa on newer systems, to validate the
> rest of the build.
I confirm that after reverting to --with-cocoa, both Intel and Apple Silicon
builds are able to emulate Thomas' vexpress-a9 project.
However
On Tue, Jan 18, 2022 at 03:44:40PM -0300, Fabiano Rosas wrote:
> powerpc_excp_40x applies only to the 405, so remove HV code and
> references to BookE.
>
> Signed-off-by: Fabiano Rosas
> Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 26 ++
> 1 file changed
On Tue, Jan 18, 2022 at 03:44:43PM -0300, Fabiano Rosas wrote:
> There is no DSISR in the 405. It uses DEAR which we already set
> earlier at ppc_cpu_do_unaligned_access.
Enabled specifically, I note, by env->mmu_model rather than
env->excp_model, which doesn't make a lot of sense. Another cleanu
On Tue, Jan 18, 2022 at 03:44:44PM -0300, Fabiano Rosas wrote:
> The current Debug exception dispatch is the BookE one, so it is
> different from the 405. We effectively don't support the 405 Debug
> exception.
>
> This patch removes the BookE code and moves the DEBUG into the "not
> implemented"
On Tue, Jan 18, 2022 at 03:44:38PM -0300, Fabiano Rosas wrote:
> Differences from the generic powerpc_excp code:
>
> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
> - No MSR_HV or MSR_LE;
> - No power saving states;
> - No Hypervisor Emulation Assistance;
> - Not 64 bits;
> - No
On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
> The 405 has no DSISR or DAR, so convert the trace entry to
> trace_ppc_excp_print.
I think it would be preferable to show ESR and DEAR here, which are
very loosely equivalent to DSISR and DAR on 40x. Might want to create
a new trace
On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
> The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
> just a clean copy of the MSR.
>
> We're using the BookE Exception Syndrome Register which is different
> from the 405.
Hrm. We really do want to set the 40x ES
On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
> There's no sc 1.
No... but what exactly should and will happen if you attempt to
execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
cause a 0x700? If it's a 0x700, better double check that that is
generated at tr
On 1/5/22 15:02, Emanuele Giuseppe Esposito wrote:
Now that they are not nop anymore, remove the aiocontext
to avoid deadlocks.
Ok, that should have been in patch 1, together with a description of the
deadlocks. :) Disregard that review.
There is only one JobDriver callback, ->free() that
> On 17 Jan 2022, at 18:19, Philippe Mathieu-Daudé wrote:
>
> The consensus was UI should not be addressed within QEMU itself, but
> via an external helper, eventually using D-Bus. D-Bus support has been
> recently merged:
> https://www.qemu.org/docs/master/interop/dbus.html
Thank you for the
On 1/19/22 12:35 PM, Daniel P. Berrangé wrote:
> Copying the maintainers for block/parallels.c
>
> On Wed, Jan 19, 2022 at 12:04:23PM +0300, Michael Tokarev wrote:
>> [This is a trivial patch, but due to the number of files it touches
>> I'm not using qemu-trivial@ route.]
>>
>> For a long time, we
Getters such as job_get_aio_context are often wrong because the
AioContext can change immediately after returning.
So, I wonder if job.aio_context should be protected with a kind of "fake
rwlock": read under BQL or job_lock, write under BQL+job_lock. For this
to work, you can add an assert
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
These functions assume that the job lock is held by the
caller, to avoid TOC/TOU conditions. Therefore, their
name must end with _locked.
Introduce also additional helpers that define _locked
functions (useful when the job_mutex is globally appl
On 1/5/22 15:02, Emanuele Giuseppe Esposito wrote:
Introduce the job locking mechanism through the whole job API,
following the comments and requirements of job-monitor (assume
lock is held) and job-driver (lock is not held).
job_{lock/unlock} is independent from real_job_{lock/unlock}.
Note: a
On 1/5/22 15:02, Emanuele Giuseppe Esposito wrote:
+++ b/blockjob.c
@@ -335,13 +335,13 @@ BlockJobInfo *block_job_query(BlockJob *job, Error **errp)
info = g_new0(BlockJobInfo, 1);
info->type = g_strdup(job_type_str(&job->job));
info->device= g_strdup(job->job.id);
-
On 1/16/22 17:45, Peter Maydell wrote:
On Fri, 7 Jan 2022 at 07:29, Alexey Kardashevskiy wrote:
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
+WITH_JOB_LOCK_GUARD() {
+abort = job->ret < 0;
+}
+
if (s->prepared) {
return 0;
}
At this point I think job->ret is stable and can be accessed without
guard. The question however is what serializes calls
On 1/5/22 15:02, Emanuele Giuseppe Esposito wrote:
In preparation to the job_lock/unlock patch, remove these
aiocontext locks.
The main reason these two locks are removed here is because
they are inside a loop iterating on the jobs list. Once the
job_lock is added, it will have to protect the who
On 1/5/22 12:13, Hanna Reitz wrote:
-assert(s->bus->dma->aiocb == NULL);
+
+/*
+ * Wait for potentially still-scheduled BHs, like ide_trim_bh_cb()
+ * (blk_drain() will only poll if there are in-flight requests on the
+ * BlockBackend, which there may not n
On 1/19/22 10:56, mreza...@redhat.com wrote:
From: Miroslav Rezanina
GCC options -mlittle and -mlittle-endian are equivalent on ppc64
architecture. However, clang supports only -mlittle-endian option.
Use longer form in configure to properly support both GCC and clang
compiler.
Signed-off-by:
On 1/19/22 10:56, Paolo Bonzini wrote:
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
job mutex will be used to protect the job struct elements and list,
replacing AioContext locks.
Right now use a shared lock for all jobs, in order to keep things
simple. Once the AioContext lock is gone, w
On 1/5/22 15:01, Emanuele Giuseppe Esposito wrote:
In this series, we want to remove the AioContext lock and instead
use the already existent job_mutex to protect the job structures
and list. This is part of the work to get rid of AioContext lock
usage in favour of smaller granularity locks.
In
Dear Sukreet Pal,
On Tuesday 18 of January 2022 12:41:35 sukreet@st.ovgu.de wrote:
> Yes, we can push the conversation in qemu mailing list.
Great, may be there is some other input from the list.
Recapitulation:
Sukreet Pal want to use CAN emulation included
in QEMU to test some CAN related
On 1/19/22 07:06, David Gibson wrote:
On Tue, Jan 18, 2022 at 03:44:40PM -0300, Fabiano Rosas wrote:
powerpc_excp_40x applies only to the 405, so remove HV code and
references to BookE.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/excp_helper.c | 26 ++--
On 13/1/22 21:20, Philipp Tomsich wrote:
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v
On 1/18/22 19:44, Fabiano Rosas wrote:
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/cpu_init.c | 1 +
1 file ch
On 1/18/22 19:44, Fabiano Rosas wrote:
Introduce a new powerpc_excp function specific for 40x CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/excp_helper.c | 474
On 13/1/22 21:20, Philipp Tomsich wrote:
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
Thi
On Mon, Jan 17, 2022 at 08:43:25PM +0800, Longpeng(Mike) via wrote:
From: Longpeng
Implements the .instance_init and the .class_init interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev-pci.c | 52 ++-
hw/virtio/vdpa-dev.c | 81 +
On 19.01.22 12:11, Paolo Bonzini wrote:
On 1/5/22 12:13, Hanna Reitz wrote:
- assert(s->bus->dma->aiocb == NULL);
+
+ /*
+ * Wait for potentially still-scheduled BHs, like
ide_trim_bh_cb()
+ * (blk_drain() will only poll if there are in-flight
requests on the
+ *
On Mon, Jan 17, 2022 at 08:43:27PM +0800, Longpeng(Mike) via wrote:
From: Longpeng
Implements the .unrealize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --g
On 1/19/22 07:13, David Gibson wrote:
On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
The 405 has no DSISR or DAR, so convert the trace entry to
trace_ppc_excp_print.
I think it would be preferable to show ESR and DEAR here, which are
very loosely equivalent to DSISR and DAR on
On Mon, Jan 17, 2022 at 08:43:26PM +0800, Longpeng(Mike) via wrote:
From: Longpeng
Implements the .realize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 101 +++
include/hw/virtio/vdpa-dev.h | 8 +++
2 files changed, 109 insertions(+)
d
On 1/18/22 19:44, Fabiano Rosas wrote:
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Thank
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4
target/riscv/insn_trans/tra
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..b487a8282c 10064
This patchset implements RISC-V scalar crypto extension v1.0.0 version
instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v5
To test rvk imple
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 53 +++
target/riscv/helper.h
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++
include/cryp
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 139
target/riscv/helper.h | 6 +
target/riscv/insn32.decode
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 57
target/riscv/helper.h | 7 ++
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 +
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 49 +
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode | 6 ++
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 136
target/riscv/helper.h
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 64 +
target/riscv/
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