From: Longpeng
Implements the .get_config and .set_config interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 4e4dd3d201..4f97a7521b 100644
--- a/hw/vir
From: Longpeng
Implements the .unrealize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 2d534d837a..4e4dd3d201 100644
--- a/hw/virtio/vdpa-d
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 64649bfb5a..0644aace22 1006
From: Longpeng
Implements the .set_status interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 100 ++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 32b3117c4b..64649bfb5a 100644
From: Longpeng
Implements the .get_features interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 4f97a7521b..32b3117c4b 100644
--- a/hw/virtio/vdpa-dev.c
+++ b/h
Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
The v1.0 release includes the following commits:
ec5274b platform: implement K210 system reset
5487cf0 include: sbi: Simplify HSM state define names
8df1f9a lib: sbi: Use SBI_HSM_STATE_xyz defines instead of SBI_STATE_xyz defines
7c
The GDB statck is as follows:
(gdb) bt
0 __lll_lock_wait (futex=futex@entry=0x56211df20360, private=0) at
lowlevellock.c:52
1 0x7f263caf20a3 in __GI___pthread_mutex_lock (mutex=0x56211df20360) at
../nptl/pthread_mutex_lock.c:80
2 0x56211a757364 in qemu_mutex_lock_impl (mutex=0x56211df2
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use re
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
instruct
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
flo
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions(-)
FreeBSD: Upgrade to 12.3 release
Note, since libtasn1 was fixed in 12.3 [*], this commit re-enables GnuTLS.
[*] https://gitlab.com/gnutls/libtasn1/-/merge_requests/71
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
Reviewed-by: Warner Losh
---
.gitlab-ci.d/cirrus.yml | 5 +
tests/vm/fr
On 1/4/22 4:40 PM, Richard Henderson wrote:
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into
staging (2022-01-04 07:23:27 -0800)
are available in the Git repository at:
https://
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented i
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 33 +
1 file changed, 33 insertions(+)
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
target/riscv/cp
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
---
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 6 +
target/riscv/csr.c | 57
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/riscv/cpu.c | 3
From: Bin Meng
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 trigger
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
---
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 17dcc3c14f..1744
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented i
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 33 +
1 file changed, 33
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
---
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 6 +
target/riscv/csr.c | 57
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/h
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/ri
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented i
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is
On Wed, Jan 5, 2022 at 5:32 AM Patrick Venture wrote:
>
>
>
> On Tue, Jan 4, 2022 at 1:18 PM Patrick Venture wrote:
>>
>> From: Peter Foley
>>
>> Match the other error handling in this function.
>
>
> Just noticed I didn't fix up the commit title here to match style. Should I
> do a PATCH RESE
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
---
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-o
Anup Patel 於 2021年12月30日 週四 下午8:53寫道：
> From: Anup Patel
>
> The AIA specification defines IMSIC interface CSRs for easy access
> to the per-HART IMSIC registers without using indirect xiselect and
> xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
>
> Signed-off-by: Anup Patel
>
This patchset improves support for sched_* syscalls under user emulation.
The first commit adds support for sched_g/setattr that was previously not
implemented. These syscalls are not exposed by glibc. The struct type needs
to be redefined as it can't be included directly before
https://lkml.org/
These syscalls are not exposed by glibc. The struct type need to be
redefined as it can't be included directly before
https://lkml.org/lkml/2020/5/28/810 .
sched_attr type can grow in future kernel versions. When client sends
values that QEMU does not understand it will return E2BIG with same
sema
When scsalable mode is enabled, the passthrough more is not determined
by the context entry but PASID entry, so switch to use the logic of
vtd_dev_pt_enabled() to determine the passthrough mode in
vtd_do_iommu_translate().
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 38
There seems to be difference in syscall and libc definition of these
methods and therefore musl does not implement them (1e21e78bf7). Call
syscall directly to ensure the behavior of the libc of user application,
not the libc that was used to build QEMU.
Signed-off-by: Tonis Tiigi
---
linux-user/
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during initialization. So
let's don't warn in this case.
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/i386
Hi All:
This series tries to introduce PASID support for Intel IOMMU. The work
is based on the previous scalabe mode support by implement the
ECAP_PASID. A new "x-pasid-mode" is introduced to enable this
mode. All internal vIOMMU codes were extended to support PASID instead
of the current RID2PASI
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus struct
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
with PASID
2) tag IOTLB with PASID
3) PASID cache and its flush
For simplic
On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> To support generic vdpa deivce, we need add the following ioctls:
> - GET_VECTORS_NUM: the count of vectors that supported
Does this mean MSI vectors? If yes, it looks like a layer violation:
vhost is transport independe
On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> Add helpers to get the "Transitional PCI Device ID" and "class_id" of the
> deivce which is specificed by the "Virtio Device ID".
>
> These helpers will be used to build the generic vDPA device later.
>
> Signed-off-by: L
Brown bag time: offset 0 from esp is the return address,
offset 4 is the first argument.
Fixes: d7478d4229f0 ("common-user: Fix tail calls to
safe_syscall_set_errno_tail")
Signed-off-by: Richard Henderson
---
Ho hum. I'm disappointed that our CI didn't catch this,
despite cross-i386-user. And
> -Original Message-
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Wednesday, January 5, 2022 12:38 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; mst ; Stefano
> Garzarella ; Cornelia Huck ; pbonzini
> ; Gonglei (Arei) ; Yechuan
On Tue, Jan 04, 2022 at 05:38:38PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Fri, Dec 24, 2021 at 11:53:15AM +0800, Robert Hoo wrote:
> > > On Thu, 2021-12-23 at 20:29 +0800, Chao Peng wrote:
> > > > From: "Kirill A. Shutemov"
> > > >
> > > > +static void
On Tue, Jan 04, 2022 at 05:43:50PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Tue, Dec 28, 2021 at 09:48:08PM +, Sean Christopherson wrote:
> > >KVM handles
> > > reverse engineering the memslot to get the offset and whatever else it
> > > needs.
> > > no
On Tue, Jan 04, 2022 at 05:31:30PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Fri, Dec 24, 2021 at 12:13:51PM +0800, Chao Peng wrote:
> > > On Thu, Dec 23, 2021 at 06:06:19PM +, Sean Christopherson wrote:
> > > > On Thu, Dec 23, 2021, Chao Peng wrote:
> >
On Wed, Jan 5, 2022 at 1:48 PM Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang [mailto:jasow...@redhat.com]
> > Sent: Wednesday, January 5, 2022 12:38 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
On Tue, Jan 04, 2022 at 06:06:12PM +0800, Yan Zhao wrote:
> On Tue, Jan 04, 2022 at 05:10:08PM +0800, Chao Peng wrote:
> > On Tue, Jan 04, 2022 at 09:46:35AM +0800, Yan Zhao wrote:
> > > On Thu, Dec 23, 2021 at 08:30:09PM +0800, Chao Peng wrote:
> > > > When a page fault from the secondary page tab
> -Original Message-
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Wednesday, January 5, 2022 12:36 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; mst ; Stefano
> Garzarella ; Cornelia Huck ; pbonzini
> ; Gonglei (Arei) ; Yechuan
在 2022/1/5 下午2:40, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) 写道:
-Original Message-
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Wednesday, January 5, 2022 12:36 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
Cc: Stefan Hajnoczi ; mst ; S
On 1/4/22 22:00, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
linux-user/ppc/cpu
On Wed, Jan 05, 2022 at 12:35:53PM +0800, Jason Wang wrote:
> On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
> >
> > From: Longpeng
> >
> > To support generic vdpa deivce, we need add the following ioctls:
> > - GET_VECTORS_NUM: the count of vectors that supported
>
> Does this mean MSI ve
On 1/4/22 9:39 PM, Daniel P. Berrangé wrote:
On Mon, Dec 27, 2021 at 10:27:29PM +0800, zhenwei pi wrote:
1, The full picture of this patch set:
+-+ ++ +---+
|UVC(done)| |virtio(TODO)| |other HW device|
+-+ +-
On 1/4/22 11:22 PM, Philippe Mathieu-Daudé wrote:
On 27/12/21 15:27, zhenwei pi wrote:
A device of USB video class usually uses larger desc structure, so
use larger buffer to avoid failure.
Signed-off-by: zhenwei pi
---
hw/usb/desc.c | 15 ---
hw/usb/desc.h | 1 +
2 files ch
On Wed, Jan 5, 2022 at 3:02 PM Michael S. Tsirkin wrote:
>
> On Wed, Jan 05, 2022 at 12:35:53PM +0800, Jason Wang wrote:
> > On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
> > >
> > > From: Longpeng
> > >
> > > To support generic vdpa deivce, we need add the following ioctls:
> > > - GET_V
On 12/22/21 08:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
Applied in ppc-next (with the change asked by Richard).
Thanks,
C.
From: Richard Henderson
Use the cached pmc_ins_cnt value. Unroll the loop over the
different PMC counters. Treat the PMC4 run-latch specially.
Signed-off-by: Richard Henderson
Message-Id: <20220103224746.167831-3-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/power8-p
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