From: Bin Meng <bin.m...@windriver.com> Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- (no changes since v2) Changes in v2: - change the config option to 'disabled' by default target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0f3b3a4219..35445bbc86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -75,6 +75,7 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, + RISCV_FEATURE_DEBUG, RISCV_FEATURE_MISA }; @@ -332,6 +333,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool debug; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3aa07bc019..d36c31ce9a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } + if (cpu->cfg.debug) { + set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); /* Validate that MISA_MXL is set properly. */ @@ -634,6 +638,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), -- 2.25.1