On Mon, 13 Dec 2021 05:33:43 -0500
"Michael S. Tsirkin" wrote:
> On Mon, Dec 13, 2021 at 08:43:55AM +0100, Thomas Huth wrote:
> >
> > Hi Michael, hi Igor,
> >
> > just FYI, a crash has been reported in the ACPI code ...
> > by the way, do you have a gitlab account, so you could be put on CC: f
On Tue, Dec 14, 2021 at 12:54:05AM +1100, Simon Burge wrote:
> Hi Phil,
>
> =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= wrote:
>
> > Oops, missing your Signed-off-by tag, see:
> > https://www.qemu.org/docs/master/devel/submitting-a-patch.html#patch-emails-must-includ
> e-a-signed-off-by-line
> >
> >
Peter Maydell writes:
> When an ITS detects an error in a command, it has an
> implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
> to ignore the command, proceeding to the next one in the queue, or to
> stall the ITS command queue, processing nothing further. The
> behaviour
Peter Maydell writes:
> Fix process_its_cmd() to consistently return CMD_STALL for
> memory errors and CMD_CONTINUE for parameter errors, as
> we claim in the comments that we do.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
--
Alex Bennée
Peter Maydell writes:
> In process_cmdq(), we read 64 bits of the command packet, which
> contain the command identifier, which we then switch() on to dispatch
> to an appropriate sub-function. However, if address_space_ldq_le()
> reports a memory transaction failure, we still read the command
Peter Maydell writes:
> Refactor process_its_cmd() so that it consistently uses
> the structure
> do thing;
> if (error condition) {
> return early;
> }
> do next thing;
>
> rather than doing some of the work nested inside if (not error)
> code blocks.
>
> Signed-off-by: Peter May
Peter Maydell writes:
> Fix process_mapc() to consistently return CMD_STALL for memory
> errors and CMD_CONTINUE for parameter errors, as we claim in the
> comments that we do.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
--
Alex Bennée
Peter Maydell writes:
> Fix process_mapti() to consistently return CMD_STALL for memory
> errors and CMD_CONTINUE for parameter errors, as we claim in the
> comments that we do.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
--
Alex Bennée
Peter Maydell writes:
> Fix process_mapd() to consistently return CMD_STALL for memory
> errors and CMD_CONTINUE for parameter errors, as we claim in the
> comments that we do.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
--
Alex Bennée
On Mon, Dec 13, 2021 at 05:40:08AM -0500, Emanuele Giuseppe Esposito wrote:
> Hello everyone,
>
> As you know already, my current goal is to try to remove the AioContext lock
> from the QEMU block layer.
> Currently the AioContext is used pretty much throughout the whole block
> layer, it is a l
Cédric Le Goater writes:
> On 12/13/21 14:35, Fabiano Rosas wrote:
>> When Altivec support was added to the e6500 kernel in 2012[1], the
>> QEMU code was not changed, so we don't register the VPU/VPUA
>> exceptions for the e6500:
>>
>>qemu: fatal: Raised an exception without defined vector 7
On Mon, Dec 13, 2021 at 11:07:38AM +, Peter Maydell wrote:
> On Mon, 13 Dec 2021 at 10:56, Jean-Philippe Brucker
> wrote:
> >
> > On Mon, Dec 13, 2021 at 10:04:57AM +, Peter Maydell wrote:
> > > On Mon, 13 Dec 2021 at 09:28, Jean-Philippe Brucker
> > > wrote:
> > > >
> > > > On Sun, Dec 1
Peter Maydell writes:
> The ITS has several tables which all share a similar format,
> described by the TableDesc struct: the guest may configure them
> to be a single-level table or a two-level table. Currently we
> open-code the process of finding the table entry in all the
> functions which
On Mon, Dec 13, 2021 at 10:47:00AM +0800, Jason Wang wrote:
> On Sun, Dec 12, 2021 at 5:30 PM Michael S. Tsirkin wrote:
> >
> > On Sat, Dec 11, 2021 at 03:00:27AM +, Longpeng (Mike, Cloud
> > Infrastructure Service Product Dept.) wrote:
> > >
> > >
> > > > -Original Message-
> > > > F
On Sat, Dec 11, 2021 at 04:11:04AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
> > -Original Message-
> > From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> > Sent: Thursday, December 9, 2021 11:55 PM
> > To: Longpeng (Mike, Cloud Infrastructure Ser
* Zheng Chuan (zhengch...@huawei.com) wrote:
> Hi, Juan,
>
> Sorry, forget to send to qemu-devel, resend it.
>
> On 2021/11/24 18:05, Juan Quintela wrote:
> > We will need to split it later in zero_num (number of zero pages) and
> > normal_num (number of normal pages). This name is better.
> >
Daniel P. Berrangé writes:
> On Fri, Dec 10, 2021 at 04:26:20PM +0100, Markus Armbruster wrote:
>>
>> The existing binary provides bad CLI and limited QMP.
>>
>> Going from limited to good QMP involves reworking the startup code. I
>> believe that's easier in a new binary.
>>
>> Going from ba
On 12/12/21 9:05 PM, Anup Patel wrote:
+ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, state), ®);
+if (ret) {
+abort();
+}
+env->kvm_timer_state = reg;
Please read the timer frequency here.
Yep.
+
+env->kvm_timer_dirty = true;
+}
+
+static void kvm_riscv_put_reg
On 12/10/21 2:07 AM, Yifei Jiang via wrote:
+static bool kvmtimer_needed(void *opaque)
+{
+return kvm_enabled();
+}
+
+
+static const VMStateDescription vmstate_kvmtimer = {
+.name = "cpu/kvmtimer",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = kvmtimer_needed,
+.
Paolo Bonzini writes:
> On 12/10/21 14:54, Markus Armbruster wrote:
>> I want an open path to a single binary. Taking years to get there is
>> fine.
>
> The single binary is a distraction in my opinion. Imagine
> instead of vl.c you have this in your second binary:
[...]
> static void open_so
Hi all!
The functionality is reviewed, python testing part is not.
I've dropped the patch "qapi: make blockdev-add a coroutine command":
it's optional, I don't want to slow down the whole series because of it.
v4:
01-03: wording, add Eric's r-b
others: small changes, never had an r-b
Vladimir
Split qemu_tool_popen() from qemu_tool_pipe_and_status() to be used
separately.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/iotests.py | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iote
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
nbd/client-connection.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/nbd/client-connection.c b/nbd/client-connection.c
index 722998c985..2bda42641d 100644
--- a/nbd/client-connection.c
+++
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
.../qemu-iotests/tests/nbd-reconnect-on-open | 71 +++
.../tests/nbd-reconnect-on-open.out | 11 +++
2 files changed, 82 insertions(+)
create mode 100755 tests/qemu-iotests/tests/nbd-reconnect-on-open
create mode 100644
It is useful when start of vm and start of nbd server are not
simple to sync.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
qapi/block-core.json | 9 -
block/nbd.c | 45 +++-
2 files changed, 52 insertions(+), 2
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/iotests.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py
index 1ed3eb1058..69d380e137 100644
--- a/tests/qemu-iotests/iotests.py
+++ b/tests/qemu-iotests/iotes
For QemuIoInteractive use new wrapper as well, which allows relying on
default format.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/iotests.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qe
The only caller of nbd_do_establish_connection() that uses errp is
nbd_open(). The only way to cancel this call is through open_timer
timeout. And for this case, user will be more interested in description
of last failed connect rather than in
"Connection attempt cancelled by other operation".
So,
On Tue, Nov 30, 2021 at 04:46:31AM -0500, Emanuele Giuseppe Esposito wrote:
> Add a getter function for the if_name array, so that also
> outside functions can access it.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> blockdev.c| 5 +
> include/sysemu/blockdev.h | 1 +
On 12/13/21 2:23 AM, Philippe Mathieu-Daudé wrote:
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signe
On Tue, Nov 30, 2021 at 04:46:32AM -0500, Emanuele Giuseppe Esposito wrote:
> drive_add is only used in softmmu/vl.c, so it can be a static
> function there, and drive_def is only a particular use case of
> qemu_opts_parse_noisily, so it can be inlined.
>
> Also remove drive_mark_claimed_by_board,
Damien Hedde writes:
[...]
>> Painted with a big brush, there are two kinds of code in hw/: actual
>> device emulation, and "wiring". Both in C, and sometimes in the same .c
>> file.
>>
>> Doing the "wiring" in configuration instead is less powerful (no longer
>> Turing complete[2]), but easi
On Tue, Nov 30, 2021 at 04:46:30AM -0500, Emanuele Giuseppe Esposito wrote:
> bdrv_backing_overridden is only used in block.c, so there is
> no need to leave it in block_int.h
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> block.c | 4 +++-
> include/block/block_int.h |
On Tue, Nov 30, 2021 at 04:46:33AM -0500, Emanuele Giuseppe Esposito wrote:
> Remove drive_get_max_devs, as it is not used by anyone.
>
> Last use was removed in commit 8f2d75e81d5
> ("hw: Drop superfluous special checks for orphaned -drive").
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Revi
On Mon, 13 Dec 2021 at 15:00, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > The ITS has several tables which all share a similar format,
> > described by the TableDesc struct: the guest may configure them
> > to be a single-level table or a two-level table. Currently we
> > open-code the p
On Tue, Nov 30, 2021 at 04:46:29AM -0500, Emanuele Giuseppe Esposito wrote:
> These patches are taken from my old patches and feedback of
> my series "block layer: split block APIs in global state and I/O".
>
> The reason for a separate series is that the original one is
> already too long, and th
On 12/13/21 4:13 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. We are currently
honoring this behavior in xscvdpspn, since helper_xscvdpspn handles the
conve
On Tue, Dec 07, 2021 at 01:23:30PM +, Stefan Hajnoczi wrote:
> v3:
> - Fixed FUSE export aio_set_fd_handler() call that I missed and double-checked
> for any other missing call sites using Coccinelle [Rich]
> v2:
> - Cleaned up unused return values in nvme and virtio-blk [Stefano]
> - Documen
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Revi
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset o
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and advices.
v7:
- code motion following reviews
- correction of a bug preventing riscv{32,64}-linux-user to compile
- sync with ma
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
wher
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
include/qe
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translat
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
include/exec/memop.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b/incl
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 3 +
target
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of the processor because w
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9 +
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
-
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 10 ++
target/riscv/translate.c
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/targe
Friendly bump.
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, w
On 12/13/21 16:19, Markus Armbruster wrote:
I think it's more often just three: the long one that can do everything,
the short one that can do simple things (and doesn't tell you anything
about the long one), and the bad one you shouldn't use.
If we're going to have a good CLI, it would ideally
On 12/13/21 16:28, Markus Armbruster wrote:
Paolo Bonzini writes:
On 12/10/21 14:54, Markus Armbruster wrote:
I want an open path to a single binary. Taking years to get there is
fine.
The single binary is a distraction in my opinion. Imagine
instead of vl.c you have this in your second b
Because sa may be 0,
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
may attempt a zero-width deposit at bit 32, which will assert
for TARGET_REGISTER_BITS == 32.
Use the newer extract2 when possible, which itself includes the
rotri special case; otherwise mirror the code from tra
On Fri, Dec 10, 2021 at 05:04:08PM +, Jean-Philippe Brucker wrote:
> Add ACPI support for virtio-iommu on the virt machine, by instantiating
> a VIOT table. Also add the tests for the ACPI table.
ACPI parts:
Acked-by: Michael S. Tsirkin
> Since last posting [1], I rebased onto v6.2.0-rc4. No
On Mon, Dec 13, 2021 at 06:30:45PM +0100, Paolo Bonzini wrote:
> On 12/13/21 16:19, Markus Armbruster wrote:
> > I think it's more often just three: the long one that can do everything,
> > the short one that can do simple things (and doesn't tell you anything
> > about the long one), and the bad o
On Mon, Dec 13, 2021 at 06:37:44PM +0100, Paolo Bonzini wrote:
> On 12/13/21 16:28, Markus Armbruster wrote:
> > Would you object to me expanding the CLI here to the point where I think
> > we can deprecate the old binary?
> >
> > If yes, why?
>
> Yes, for two reasons.
>
> First, because there w
On 12/13/21 10:28, Cédric Le Goater wrote:
The POWER8 processors with a NVLink logic unit have 4 PHB3 devices per
chip.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv
On 12/13/21 10:28, Cédric Le Goater wrote:
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb3.c | 2 +-
1 file changed, 1 insertion(+), 1 d
On 12/13/21 10:28, Cédric Le Goater wrote:
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 dev
On 12/13/21 10:28, Cédric Le Goater wrote:
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater
---
On 12/13/21 19:07, Daniel P. Berrangé wrote:
- /usr/bin/qemu (or /usr/bin/qemu-vm) - for a high level binary that
targets humans and uses a templating system to expose a friendly
simple config, that internally invokes whichever target specific
/usr/bin/qemu-buildvm-$TARGET is im
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi
---
target/arm/cpu_tcg.c | 37 +
1 file changed, 37 insertions(+
On Mon, Dec 13, 2021 at 07:37:49PM +0100, Paolo Bonzini wrote:
> On 12/13/21 19:07, Daniel P. Berrangé wrote:
> >- /usr/bin/qemu (or /usr/bin/qemu-vm) - for a high level binary that
> > targets humans and uses a templating system to expose a friendly
> > simple config, that internally
Since v1:
Add preliminary code movement patch to ease reviewing
Richard patch.
Philippe Mathieu-Daudé (1):
target/hppa: Minor code movement
Richard Henderson (1):
target/hppa: Fix deposit assert from trans_shrpw_imm
target/hppa/translate.c | 19 ---
1 file changed, 12 insert
Move the 'a->r1 == 0' if ladder earlier, simply
to ease reviewing the next commit change.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3b9744deb4
From: Richard Henderson
Because sa may be 0,
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
may attempt a zero-width deposit at bit 32, which will assert
for TARGET_REGISTER_BITS == 32.
Use the newer extract2 when possible, which itself includes the
rotri special case; otherwis
On Mon, Dec 13, 2021 at 3:16 PM Kostiantyn Kostiuk
wrote:
>
> Signed-off-by: Kostiantyn Kostiuk
> Signed-off-by: Kostiantyn Kostiuk
Reviewed-by: Marc-André Lureau
> ---
> qga/commands-win32.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/qga/commands-win32.c
On Mon, Dec 13, 2021 at 3:16 PM Kostiantyn Kostiuk
wrote:
>
> To prevent memory leaks, always try to free initialized variables.
>
> Signed-off-by: Kostiantyn Kostiuk
> Signed-off-by: Kostiantyn Kostiuk
Reviewed-by: Marc-André Lureau
(nit: since it's a common return point, I would rather name
On Mon, Dec 13, 2021 at 3:16 PM Kostiantyn Kostiuk
wrote:
>
> In case when the function fails to get parent device data,
> the parent_dev_info variable will be initialized, but not freed.
>
> Signed-off-by: Kostiantyn Kostiuk
> Signed-off-by: Kostiantyn Kostiuk
Reviewed-by: Marc-André Lureau
On Mon, Dec 13, 2021 at 3:16 PM Kostiantyn Kostiuk
wrote:
>
> Microsoft suggests this solution in the documentation:
> https://docs.microsoft.com/en-us/windows/win32/api/setupapi/nf-setupapi-setupdigetdeviceinterfacedetaila
>
> Signed-off-by: Kostiantyn Kostiuk
> Signed-off-by: Kostiantyn Kostiuk
On Mon, Dec 13, 2021 at 3:16 PM Kostiantyn Kostiuk
wrote:
>
> Signed-off-by: Kostiantyn Kostiuk
> Signed-off-by: Kostiantyn Kostiuk
Reviewed-by: Marc-André Lureau
(250loc.. the function would deserve to be refactored to not be so long..)
> ---
> qga/commands-win32.c | 6 ++
> 1 file cha
On Mon, 13 Dec 2021, Fabiano Rosas wrote:
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, in
On 12/13/21 19:24, Byron Lathi wrote:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi
> ---
> target/arm/cpu_tcg.c | 37 ++
On 13/12/2021 12:46, Richard Henderson wrote:
On 12/13/21 4:13 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. We are currently
honoring this behavior in xscv
On 13/12/2021 09:36, Philippe Mathieu-Daudé wrote:
On 12/13/21 13:13, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. We are currently
honoring this behavior in x
> On 13 Dec 2021, at 18:59, Daniel P. Berrangé wrote:
>
> …. we no longer have to solve everything
> Ourselves.
I support this sentiment.
Lets re-factor the code so people can build what they need using an API.
Actually, ‘QEMU’ only need support the existing CLI, and provide a suitable
inte
On 12/13/21 10:24 AM, Byron Lathi wrote:
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi
---
target/arm/cpu_tcg.c | 37 ++
On Mon, Dec 13, 2021 at 04:32:34PM +0100, Vladimir Sementsov-Ogievskiy wrote:
> It is useful when start of vm and start of nbd server are not
> simple to sync.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Eric Blake
> ---
> qapi/block-core.json | 9 -
> block/nbd.c
Ani, an inline response below.
Thanks!
eric
On 12/10/21 08:09, Ani Sinha wrote:
On Thu, Dec 9, 2021 at 11:24 PM Eric DeVolder wrote:
Ani, inline responses below. eric
On 12/9/21 00:29, Ani Sinha wrote:
On Fri, Dec 3, 2021 at 12:39 AM Eric DeVolder wrote:
This implements a PCI device for
Happy holidays, Taylor,
I've located a bug in tests/multiarch/float_*, which means that the hexagon *.ref files
are out of date.
At your convenience, would you please check out
https://gitlab.com/rth7680/qemu/-/commits/fix-sfp-test
and re-generate the files for me? I'll squash the diff into
Let's wait to mark the VCPU STOPPED until the possible
STORE STATUS operation is completed, so that we know the
CPU is fully stopped and done doing anything. (When we
also clear the possible sigp_order field for STOP orders.)
Suggested-by: David Hildenbrand
Signed-off-by: Eric Farman
---
target
Here is an update to the SIGP handling series, to correspond to
version 5 of the KVM series [1].
Unlike earlier versions, there is no new interface to exploit.
So this simply rearranges processing to mirror expectations
on the kernel side.
[1] https://lore.kernel.org/r/20211213210550.856213-1-far
Byron Lathi writes:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi
> ---
> target/arm/cpu_tcg.c | 37 +
Hi Ani,
inline response below.
Eric
On 12/12/21 07:43, Ani Sinha wrote:
.
On Thu, Dec 9, 2021 at 11:28 PM Eric DeVolder wrote:
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
This patch starts in the middle of pci device code addition, between
e
Happy holidays to you as well!!
Sure - would you prefer a patch or a fresh copy of the files?
Taylor
> -Original Message-
> From: Richard Henderson
> Sent: Monday, December 13, 2021 3:04 PM
> To: Taylor Simpson
> Cc: qemu-devel
> Subject: update hexagon float ref files
>
> Happy hol
On 12/13/21 1:31 PM, Taylor Simpson wrote:
Happy holidays to you as well!!
Sure - would you prefer a patch or a fresh copy of the files?
Which ever is easier for you.
r~
On 12/13/21 1:02 PM, Alex Bennée wrote:
+cpu->midr = 0x410fc0f1;
hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
I can't find the actual value in the TRM.
https://developer.arm.com/documentation/ddi0434/c
has exactly this value at the top of table 4-9.
+cpu-
Michael,
Thanks for reviewing! Inline responses below.
eric
On 12/12/21 16:56, Michael S. Tsirkin wrote:
On Thu, Dec 09, 2021 at 12:57:31PM -0500, Eric DeVolder wrote:
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
On 12/13/21 21:15, Matheus K. Ferst wrote:
> On 13/12/2021 09:36, Philippe Mathieu-Daudé wrote:
>> On 12/13/21 13:13, matheus.fe...@eldorado.org.br wrote:
>>> From: Matheus Ferst
>>>
>>> The non-signalling versions of VSX scalar convert to shorter/longer
>>> precision insns doesn't silence SNaNs i
On 12/13/21 19:56, Philippe Mathieu-Daudé wrote:
> From: Richard Henderson
>
> Because sa may be 0,
>
> tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
>
> may attempt a zero-width deposit at bit 32, which will assert
> for TARGET_REGISTER_BITS == 32.
>
> Use the newer extract2
The goal for me was to eventually add the SAMA5D, so I might have made some
assumptions that were not correct for all devices. My apologies for the
typos.
I will add those changes and re-submit.
On Mon, Dec 13, 2021 at 3:46 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 12/13/21
On 13/12/2021 03:13, yangxiaojuan wrote:
Ping!
Please help review the V3 patch, thank you!
I've been fairly busy recently, but I will try and find some time to look at the v3
sometime during the week.
ATB,
Mark.
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