On 10/21/21 13:44, Philippe Mathieu-Daudé wrote:
> On 10/21/21 12:42, Peter Xu wrote:
>> The pci_bus_fn is similar to pci_bus_dev_fn that only takes a PCIBus* and an
>> opaque. The pci_bus_ret_fn is similar to pci_bus_fn but it allows to return
>> a
>> void* pointer.
>>
>> Use them where proper i
On Thu, Oct 14, 2021 at 09:36:17PM +0200, Gerd Hoffmann wrote:
> Allows edk2 detect virtio-mmio devices and pcie ecam.
> See comment in hw/i386/microvm-dt.c for more details.
Anyone picking this up?
Or should I do a one-patch pull request?
take care,
Gerd
On 21/10/2021 11.49, John Paul Adrian Glaubitz wrote:
Hello!
I'm regularly building debian-installer packages for Debian's unofficial ports
which includes sh4 among others. The kernel package and therefore the installer
package contains a kernel for the SH7751R machine which is emulated by QEMU
Hi Sid,
Cc'ing maintainers:
$ ./scripts/get_maintainer.pl -f chardev/char.c
"Marc-André Lureau" (maintainer:chardev)
Paolo Bonzini (reviewer:Character device...)
$ ./scripts/get_maintainer.pl -f gdbstub.c
"Alex Bennée" (maintainer:GDB stub)
"Philippe Mathieu-Daudé" (reviewer:GDB stub)
On
On Wed, 20 Oct 2021 18:27:36 +0100
Jean-Philippe Brucker wrote:
> To generate the IOMMU ACPI table, acpi-build.c can use base QEMU types
> instead of a special IommuType value.
>
> Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Igor Mammedov
> ---
> include/hw/i386/x86-iommu.h | 12 -
On Wed, 20 Oct 2021 18:27:37 +0100
Jean-Philippe Brucker wrote:
> We're about to support a third vIOMMU for x86, virtio-iommu which
> doesn't inherit X86IOMMUState. Move the IOMMU singleton into
> PCMachineState, so it can be shared between all three vIOMMUs.
>
> The x86_iommu_get_default() help
On Wed, Oct 20, 2021 at 09:06:06PM +0200, Klaus Jensen wrote:
> On Oct 7 18:24, Lukasz Maniak wrote:
> > From: Łukasz Gieryk
> >
> > The Nvme device defines two properties: max_ioqpairs, msix_qsize. Having
> > them as constants is problematic for SR-IOV support.
> >
> > The SR-IOV feature intro
On Thu, Oct 21, 2021 at 02:57:24PM +0200, Gerd Hoffmann wrote:
> On Thu, Oct 14, 2021 at 09:36:17PM +0200, Gerd Hoffmann wrote:
> > Allows edk2 detect virtio-mmio devices and pcie ecam.
> > See comment in hw/i386/microvm-dt.c for more details.
>
> Anyone picking this up?
> Or should I do a one-pat
Running with '-d in_asm' under gdb I get:
IN:
0x40007feef0: 2e 45 71 ff jno 0x40007feef3
IN:
0x40007feef3: ff .byte0xff
0x40007feef4: e9 .byte0xe9
Thread 1 "qemu-x86_64" received signal
On Wed, 20 Oct 2021 18:27:38 +0100
Jean-Philippe Brucker wrote:
> Allow instantiating a virtio-iommu device by adding an ACPI Virtual I/O
> Translation table (VIOT), which describes the relation between the
> virtio-iommu and the endpoints it manages.
>
> Add a hotplug handler for virtio-iommu o
On Thu, 21 Oct 2021, John Paul Adrian Glaubitz wrote:
Hi Zoltan!
On 10/21/21 14:12, BALATON Zoltan wrote:
Adding -d in_asm shows it seems to loop early in the kernel but not sure where.
Maybe try to compare addresses with System.map to find out where it's getting
stuck (but System.map was not i
On Wed, 20 Oct 2021 18:27:39 +0100
Jean-Philippe Brucker wrote:
> When a virtio-iommu is instantiated, describe it using the ACPI VIOT
> table.
>
> Reviewed-by: Eric Auger
> Signed-off-by: Jean-Philippe Brucker
Acked-by: Igor Mammedov
> ---
> hw/arm/virt-acpi-build.c | 7 +++
> hw/arm/
On Wed, 20 Oct 2021 18:27:40 +0100
Jean-Philippe Brucker wrote:
> virtio-iommu is now supported with ACPI VIOT as well as device tree.
> Remove the restriction that prevents from instantiating a virtio-iommu
> device under ACPI.
>
> Reviewed-by: Eric Auger
> Signed-off-by: Jean-Philippe Brucker
On Wed, 20 Oct 2021 18:27:41 +0100
Jean-Philippe Brucker wrote:
> We do not support instantiating multiple IOMMUs. Before adding a
> virtio-iommu, check that no other IOMMU is present. This will detect
> both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
>
> Fixes: 70e89132
On Wed, 20 Oct 2021 18:27:43 +0100
Jean-Philippe Brucker wrote:
> Create empty data files and allow updates for the upcoming VIOT tests.
>
> Signed-off-by: Jean-Philippe Brucker
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
> tests/data/acpi/q35/DSDT.viot | 0
> te
On Tue, Oct 12, 2021 at 04:48:43AM -0400, Emanuele Giuseppe Esposito wrote:
> block.h currently contains a mix of functions:
> some of them run under the BQL and modify the block layer graph,
> others are instead thread-safe and perform I/O in iothreads.
> It is not easy to understand which functio
On Tue, Oct 12, 2021 at 04:48:45AM -0400, Emanuele Giuseppe Esposito wrote:
> Similarly to the previous patches, split block-backend.h
> in block-backend-io.h and block-backend-global-state.h
>
> In addition, remove "block/block.h" include as it seems
> it is not necessary anymore, together with "
On Thu, Oct 21, 2021 at 10:12 AM Jason Wang wrote:
>
> On Thu, Oct 21, 2021 at 3:03 PM Eugenio Perez Martin
> wrote:
> >
> > On Thu, Oct 21, 2021 at 4:34 AM Jason Wang wrote:
> > >
> > > On Wed, Oct 20, 2021 at 8:07 PM Eugenio Perez Martin
> > > wrote:
> > > >
> > > > On Wed, Oct 20, 2021 at 11
On Tue, Oct 12, 2021 at 04:48:47AM -0400, Emanuele Giuseppe Esposito wrote:
> Similarly to the previous patch, split block_int.h
> in block_int-io.h and block_int-global-state.h
>
> block_int-common.h contains the structures shared between
> the two headers, and the functions that can't be categor
On Wed, Oct 20, 2021 at 09:07:47PM +0200, Klaus Jensen wrote:
> On Oct 7 18:23, Lukasz Maniak wrote:
> > This patch implements initial support for Single Root I/O Virtualization
> > on an NVMe device.
> >
> > Essentially, it allows to define the maximum number of virtual functions
> > supported b
On Tue, Oct 12, 2021 at 04:48:52AM -0400, Emanuele Giuseppe Esposito wrote:
> blockjob functions run always under the BQL lock.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> include/block/blockjob.h | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Stefan Hajnoczi
signatu
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/683
** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #683
It's been a while...
Daniel P. Berrangé writes:
> On Thu, Sep 09, 2021 at 01:20:16AM +0200, Philippe Mathieu-Daudé wrote:
>> Add the AccelClass::secure_policy_supported field to classify
>> safe (within security boundary) vs unsafe accelerators.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> -
Philippe Mathieu-Daudé writes:
> Hi Sid,
>
> Cc'ing maintainers:
>
> $ ./scripts/get_maintainer.pl -f chardev/char.c
> "Marc-André Lureau" (maintainer:chardev)
> Paolo Bonzini (reviewer:Character device...)
>
> $ ./scripts/get_maintainer.pl -f gdbstub.c
> "Alex Bennée" (maintainer:GDB stub
On 10/20/21 7:21 AM, Yanan Wang wrote:
Hi,
This is the latest v9 series which supports exposing vCPU topology
to the guest for Arm virt machines.
Description of this series:
Once the view of an accurate virtual cpu topology is provided to guest,
with a well-designed vCPU pinning to the pCPU we
Hi Zoltan!
On 10/21/21 15:49, BALATON Zoltan wrote:
> So somthing seems to overwrite it. Maybe you can try building an uncompressed
> kernel or one using a different compression and see if that does the same, at
> least that way we can see if it's in the decompressing or later. I think it's
> past
On Tue, Oct 12, 2021 at 04:48:54AM -0400, Emanuele Giuseppe Esposito wrote:
> drive_add is only used in softmmu/vl.c, so it can be a static
> function there, and drive_def is only a particular use case of
> qemu_opts_parse_noisily, so it can be inlined.
>
> Also remove drive_mark_claimed_by_board,
On Tue, Oct 12, 2021 at 04:48:49AM -0400, Emanuele Giuseppe Esposito wrote:
> We want to be sure that the functions that write the child and
> parent list of a bs are under BQL and drain.
>
> BQL prevents from concurrent writings from the GS API, while
> drains protect from I/O.
>
> TODO: drains
On Tue, Oct 12, 2021 at 04:49:05AM -0400, Emanuele Giuseppe Esposito wrote:
> The job API will be handled separately in another serie.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> include/qemu/job.h | 16
> 1 file changed, 16 insertions(+)
Reviewed-by: Stefan Hajnoczi
On Tue, Oct 12, 2021 at 04:48:58AM -0400, Emanuele Giuseppe Esposito wrote:
> copy-before-write functions always run under BQL lock.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Reviewed-by: Paolo Bonzini
> ---
> block/copy-before-write.c | 2 ++
> block/copy-before-write.h | 7 +++
> 2
Hi Alistair, Bin and all :
Sorry for bumping this stale topic.
As our last discussion, I have removed Kconfigs and meson options.
The custom CSR logic is in-built by default and whether a custom CSR
is presented on the accessing hart will be checked at runtime.
Changes from V4 :
Remove Kconfigs a
riscv_csrrw() will be called by CSR handling helpers, which is the
most suitable place for checking wheter a custom CSR is being accessed.
If we're touching a custom CSR, invoke the registered handlers.
Signed-off-by: Ruinland Chuan-Tzu Tsai
---
target/riscv/cpu.c | 19 +
Hi Alistair, Bin and all,
This patchset is based on the V5 patch of custom CSR support.
It demonstrates how Andes intends to use custom CSR by revealing how
Andes CoDense Extension(c), exec.it, uses a custom CSR, uitb, to
execute an instruction mapped by either user code or firmware.
To accomplis
Introduce A25 and AX25 CPU model designed by Andes Technology.
Signed-off-by: Ruinland Chuan-Tzu Tsai
---
target/riscv/cpu.c | 16
target/riscv/cpu.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd..0c93b7edd7 100
Add CSR bits definitions, CSR table and handler functions for Andes
AX25 and A25 CPUs. Also, enable the logic in a(x)25_cpu_init().
Signed-off-by: Ruinland Chuan-Tzu Tsai
---
target/riscv/andes_cpu_bits.h | 129 +++
target/riscv/cpu.c | 4 +
target/riscv/csr_an
This is inspired by Antmicro's work on their fork of TCG.
We try to decode custom instrucions first - - if the decoders reject
what they encounter, invoke the decoders for standard instructions.
Caveats: the pc_succ_next shall be corrected if custom decoder rejcets
the incoming opcode.
Signed-off
On Thu, Sep 23, 2021 at 04:31:00PM +0200, Stefano Garzarella wrote:
> Between the submission of a request and the unplug, other devices
> with larger limits may have been queued new requests without flushing
> the batch.
>
> Using the new `dev_max_batch` parameter, laio_io_unplug() can check
> if
On Thu, Sep 23, 2021 at 04:30:58PM +0200, Stefano Garzarella wrote:
> Commit d7ddd0a161 ("linux-aio: limit the batch size using
> `aio-max-batch` parameter") added a way to limit the batch size
> of Linux AIO backend for the entire AIO context.
>
> The same AIO context can be shared by multiple de
In this patch, we demonstrate how Andes Performance Extension(c) insn :
bfos and bfoz could be used with Andes CoDense : exec.it.
By doing so, an Andes vendor designed CSR : uitb must be used.
Signed-off-by: Ruinland Chuan-Tzu Tsai
---
target/riscv/andes_codense.decode | 23 +
targ
On Thu, Sep 23, 2021 at 04:30:59PM +0200, Stefano Garzarella wrote:
> This new parameter can be used by block devices to limit the
> Linux AIO batch size more than the limit set by the AIO context.
>
> file-posix backend supports this, passing its `aio-max-batch` option
> previously added.
>
> Ad
From: Eric Auger
Ignore IORT till reference blob for E.b spec revision gets
added.
Signed-off-by: Eric Auger
Reviewed-by: Michael S. Tsirkin
Message-Id: <20211014115643.756977-2-eric.au...@redhat.com>
Signed-off-by: Richard Henderson
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 f
On Thu, Sep 23, 2021 at 04:30:57PM +0200, Stefano Garzarella wrote:
> Commit d7ddd0a161 ("linux-aio: limit the batch size using
> `aio-max-batch` parameter") added a way to limit the batch size
> of Linux AIO backend for the entire AIO context.
>
> The same AIO context can be shared by multiple de
From: Philippe Mathieu-Daudé
Since EDK2 BaseTools only require the brotli submodule,
we don't need to initialize other submodules to build it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Gerd Hoffmann
Message-Id: <20211018105816.2663195-2-phi...@redhat.com>
Sig
From: Eric Auger
Add the DBG2 table generated with
tests/data/acpi/rebuild-expected-aml.sh
Signed-off-by: Eric Auger
Acked-by: Michael S. Tsirkin
Message-Id: <20211019080037.930641-4-eric.au...@redhat.com>
Signed-off-by: Richard Henderson
---
tests/qtest/bios-tables-test-allowed-diff.h | 1
The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-10-20 06:10:51 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-arm-20211021
From: Yanan Wang
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it
also adds all missing subnodes from the given path. We'll use it
in a coming patch where we will add cpu-map to the device tree.
And we also tweak an error message of qemu_fdt_add_subnode().
Co-developed-by: Andre
From: Eric Auger
Upgrade the IORT table from B to E.b specification
revision (ARM DEN 0049E.b).
The SMMUv3 and root complex node have additional
fields. Also unique IORT node identifiers are
introduced: they are generated in sequential order.
They are not cross-referenced though.
Signed-off-by:
From: Shuuichirou Ishii
Signed-off-by: Shuuichirou Ishii
Reviewed-by: Alex Bennée
Reviewed-by: Yanan Wang
Message-Id: <20211008063604.670699-1-ishii.shuuic...@fujitsu.com>
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Eric Auger
Re-generate reference blobs with rebuild-expected-aml.sh.
Differences reported by "make check V=1" are listed below
(IORT.numamem). Differences for other variants are similar.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
From: Eric Auger
Add placeholders for DBG2 reference table for
virt tests and ignore till reference blob is added.
Signed-off-by: Eric Auger
Acked-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
Message-Id: <20211019080037.930641-2-eric.au...@redhat.com>
Signed-off-by: Richard Henderson
---
From: Eric Auger
ARM SBBR specification mandates DBG2 table (Debug Port Table 2)
since v1.0 (ARM DEN0044F 8.3.1.7 DBG2).
The DBG2 table allows to describe one or more debug ports.
Generate an DBG2 table featuring a single debug port, the PL011.
The DBG2 specification can be found at
"Microsoft
From: Gavin Shan
The empty NUMA node, where no memory resides, are allowed. For
example, the following command line specifies two empty NUMA nodes.
With this, QEMU fails to boot because of the conflicting device-tree
node names, as the following error message indicates.
/home/gavin/sandbox/qem
From: Philippe Mathieu-Daudé
The EDK2 firmware images built to test QEMU do not require
the following submodules:
- MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
- UnitTestFrameworkPkg/Library/CmockaLib/cmocka
The only submodules required are:
- ArmPkg/Library/ArmSoftFloatLib/berkel
The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-10-20 06:10:51 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-arm-20211021
From: Yanan Wang
Add a generic API to build Processor hierarchy node structure (Type 0),
which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1.
This function will be used to build ACPI PPTT table for cpu topology.
Co-developed-by: Ying Fang
Co-developed-by: Henglong Fan
Co-deve
From: Luc Michel
Until now, int was used as the return type for all the ELF
loader related functions. The returned value is the sum of all loaded
program headers "MemSize" fields.
Because of the overflow check in elf_ops.h, trying to load an ELF bigger
than INT_MAX will fail. Switch to ssize_t t
From: Yanan Wang
On existing older machine types, without cpu topology described
in ACPI or DT, the guest will populate one by default. With the
topology described, it will read the information and set up its
topology as instructed, but that may not be the same as what was
getting used by default
From: Yanan Wang
Add a generic empty binary file for the new introduced PPTT table
under tests/data/acpi/virt, and list it as files to be changed in
tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Yanan Wang
Reviewed-by: Eric Auger
Message-Id: <20211020142125.7516-7-wangyana...@huaw
On Freitag, 8. Oktober 2021 18:08:48 CEST Christian Schoenebeck wrote:
> On Freitag, 8. Oktober 2021 16:24:42 CEST Christian Schoenebeck wrote:
> > On Freitag, 8. Oktober 2021 09:25:33 CEST Greg Kurz wrote:
> > > On Thu, 7 Oct 2021 16:42:49 +0100
> > >
> > > Stefan Hajnoczi wrote:
> > > > On Thu,
From: Andrew Jones
Support device tree CPU topology descriptions.
In accordance with the Devicetree Specification, the Linux Doc
"arm/cpus.yaml" requires that cpus and cpu nodes in the DT are
present. And we have already met the requirement by generating
/cpus/cpu@* nodes for members within ms->
From: Andrew Jones
Add the Processor Properties Topology Table (PPTT) used to
describe CPU topology information to ACPI guests.
Note, a DT-boot Linux guest with a non-flat CPU topology will
see socket and core IDs being sequential integers starting
from zero, which is different from ACPI-boot Li
From: Yanan Wang
Generate the Processor Properties Topology Table (PPTT) for ARM
virt machines supporting it (>= 6.2).
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Reviewed-by: Eric Auger
Message-Id: <20211020142125.7516-8-wangyana...@huawei.com>
Signed-off-by: Richard Henderson
---
From: Yanan Wang
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
Disassembled output of the updated new file:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180810 (64-bit version)
The fact that the MMIO handler is not re-entrant causes an infinite
loop under certain conditions:
Guest write to TDT -> Loopback -> RX (DMA to TDT) -> TX
We now eliminate the effect of this problem locally in e1000, by adding
a boolean in struct E1000State indicating when the TX side is busy. T
From: Chih-Min Chao
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
The original logic:
Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
The alternative path:
Set invalid flag if ft1 == sNaN || ft2 == sNaN.
Return NaN only if ft1 == NaN && ft2 == Na
From: Chih-Min Chao
The sNaN propagation behavior has been changed since cd20cee7 in
https://github.com/riscv/riscv-isa-manual.
In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with
IEEE 754-2008 minNum and maxNum operations.
In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s
On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote:
-static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+/* Custom insn related definitions/prototypes */
+extern __thread bool cpu_has_custom_insns;
+/*
+ * These 2 are for indication if decode fails.
+ * We don't want t
Hi Kunkun,
On 9/14/21 3:53 AM, Kunkun Jiang wrote:
> We expand MemoryRegions of vfio-pci sub-page MMIO BARs to
> vfio_pci_write_config to improve IO performance.
s/to vfio_pci_write_config/ in vfio_pci_write_config()
> The MemoryRegions of destination VM will not be expanded
> successful in live m
Le 20/10/2021 à 16:08, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> +
>> +#define REQUIRE_64_OR_128BIT(ctx) do { \
>> + if (get_xl(ctx) == MXL_RV32) { \
>> + return false; \
>> + } \
>> +} while (0)
>
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/insn32.decode| 4 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 65 ++
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 86 +++
target/riscv/helper.h | 13 +++
target/ri
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv/i
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32.deco
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c0..1b3a7784b06 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,6 +617,7
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6 +618,7
From: Frank Chang
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h,
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 6 ++
target/riscv/helper.h | 1 +
target/riscv/insn32.de
om/dgibson/qemu.git tags/ppc-for-6.2-20211021
for you to fetch changes up to 6f9e8515c106650fbba7222c8f66234c8546c025:
hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels
(2021-10-21 11:42:47 +1100)
ppc patch
On 21.10.21 10:00, Peter Xu wrote:
> On Thu, Oct 21, 2021 at 09:17:57AM +0200, David Hildenbrand wrote:
>> I know, whenever someone proposes a way to tackle part of a challenging
>> problem, everybody discovers their hopes and dreams and suddenly you
>> have to go all the way to solve the complete
Hi Kunkun,
On 9/14/21 3:53 AM, Kunkun Jiang wrote:
> The MSI-X structures of some devices and other non-MSI-X structures
> are in the same BAR. They may share one host page, especially in the
may be in the same bar?
> case of large page granularity, such as 64K.
>
> For example, MSIX-Table size of
On Sat, Sep 4, 2021 at 8:42 PM Bin Meng wrote:
>
> On Thu, Sep 2, 2021 at 7:42 PM Anup Patel wrote:
> >
> > The machine or device emulation should be able to force set certain
> > CPU features because:
> > 1) We can have certain CPU features which are in-general optional
> >but implemented by
On Apple hosts we can read AppleSMC OSK directly from SMC
and forward this value to QEMU
Signed-off-by: Vladislav Yaroshchuk
---
hw/misc/applesmc.c | 129 +
1 file changed, 129 insertions(+)
diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c
index 1
The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-10-20 06:10:51 -0700)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-pull-request
for you to
On 20/10/2021 19:57, Alex Bennée wrote:
Pavel Labath writes:
On 20/10/2021 10:35, Alex Bennée wrote:
Maybe this is related to the weird output I was seeing above?
Yes, that's definitely related. What's happening is that the qemu does
not stop other thread when one of them hits a breakpoin
It was reported that enabling SafeStack reduces IOPS significantly
(>25%) with the following fio benchmark on virtio-blk using a NVMe host
block device:
# fio --rw=randrw --bs=4k --iodepth=64 --runtime=1m --direct=1 \
--filename=/dev/vdb --name=job1 --ioengine=libaio --thread \
-
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
This patch set contains a few bug fixes and I2C devices for some
NPCM7XX boards.
Patch 1~2 fix a problem that causes the SMBus module to behave
incorrectly when it's in FIFO mode and trying to receive more than
16 bytes at a time.
Patch 3 fixes a error in a register for ADC module.
Patch 4 makes
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by: Titu
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i2c/np
We made 3 changes to the at24c_eeprom_init function in
npcm7xx_boards.c:
1. We allow the function to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
2. We make at24c EEPROMs are backed by drives so that we c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/adc/npcm7xx_adc.c | 2 +-
tests/qtest
The ID can be used to indicate SMBus modules when adding
dynamic devices to them.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 2ab0080e0b..72953d65ef 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@
On Thu, Oct 21, 2021 at 11:39:51AM -0700, Hao Wu wrote:
> Originally we read in from SMBus when RXF_STS is cleared. However,
> the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
> module to read incorrect amount of bytes in FIFO mode when the number
> of bytes read changed. This p
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of read only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote:
In this patch, we demonstrate how Andes Performance Extension(c) insn :
bfos and bfoz could be used with Andes CoDense : exec.it.
By doing so, an Andes vendor designed CSR : uitb must be used.
Signed-off-by: Ruinland Chuan-Tzu Tsai
---
targ
gitlab.com/rth7680/qemu.git tags/pull-arm-20211021
for you to fetch changes up to f801789ff00f457044dcd91323316dbde42578d1:
tests/data/acpi/virt: Update the empty expected file for PPTT (2021-10-21
08:04:15 -0700)
Introduce cp
From: Matheus Ferst
This patch series implements 56 new instructions for POWER10, moving 28
"old" instructions to decodetree along the way. The series is divided by
facility as follows:
- From patch 1 to 4: Floating-Point
- From patch 5 to 10: Fixed-Point
- From patch 11 to 19: Vector
- From pat
From: pherde
Signed-off-by: Fernando Eckhardt Valle
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode | 11 +++
target/ppc/translate/fp-impl.c.inc | 14 ++
2 files changed, 25 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
From: pherde
Move resolve_PLS_D from fixedpoint-impl.c.inc to translate.c
because this way the function can be used not only by fixed
point instructions.
Signed-off-by: Fernando Eckhardt Valle (pherde)
Signed-off-by: Matheus Ferst
---
target/ppc/translate.c | 19 ++
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h| 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c| 18 ++
target/ppc/translate/fixedpoint-impl.c.inc | 12
4 files ch
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