On Mon, Oct 18, 2021 at 3:36 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
> ---
> target/riscv/machine.c | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 16a08302da..4d99880797 100644
> --- a
On Tue, Oct 19, 2021 at 06:45:19AM +, Xueming(Steven) Li wrote:
> On Tue, 2021-10-19 at 02:15 -0400, Michael S. Tsirkin wrote:
> > On Fri, Oct 08, 2021 at 03:58:04PM +0800, Xueming Li wrote:
> > > When vhost-user device cleanup and unmmap notifier address, VM cpu
> > > thread that writing the n
Sure, will fix that.
Thanks
вт, 19 окт. 2021 г. в 09:53, Alistair Francis :
> On Mon, Oct 18, 2021 at 3:36 AM Alexey Baturo
> wrote:
> >
> > Signed-off-by: Alexey Baturo
> > ---
> > target/riscv/machine.c | 27 +++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git
Hi Jean,
On 10/14/21 2:11 PM, Jean-Philippe Brucker wrote:
> Hi Eric,
>
> On Thu, Oct 14, 2021 at 04:34:05AM -0400, Eric Auger wrote:
>> Add the framework to test the virtio-iommu-pci device
>> and tests exercising the attach/detach, map/unmap API.
>>
>> Signed-off-by: Eric Auger
>> Acked-by: Tho
On Mon, 18 Oct 2021 23:38:25 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
On Mon, 18 Oct 2021 23:38:26 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
The hide_device helper can be called several times for the same
devices as it shouldn't change any state and should only return an
information.
But not to rely anymore on QemuOpts we have introduced a new field
to store the parameters of the device and don't allow to update it
once it is done.
An
On Mon, 18 Oct 2021 23:38:27 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
On Tue, 2021-10-19 at 02:37 -0400, Michael S. Tsirkin wrote:
> On Fri, Oct 08, 2021 at 03:58:05PM +0800, Xueming Li wrote:
> > When vhost-user vdpa client restart, VQ notifier resources become
> > invalid, no need to keep mmap, vdpa client will set VQ notifier after
> > reconnect.
> >
> > Removes
On Mon, 18 Oct 2021 23:38:28 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
Kevin's series "qdev: Add JSON -device" has introduced a regression
in failover by removing the QemuOpts parameter.
This series fixes that (see PATCH 1) and also makes some cleanup
in the hide_device function caller to remove the failover specific
code from qdev_device_add_from_qdict() and clarify
On Mon, Oct 11, 2021 at 12:28:19PM +0800, Jason Wang wrote:
> Hi All:
>
> This patch implements the multiqueue support for vhost-vDPA. The most
> important requirement si the control virtqueue support. The virtio-net
> and vhost-net core are tweak to support control virtqueue as if what
> data que
Commit f3a850565693 ("qdev/qbus: add hidden device support") has
introduced a generic way to hide a device but it has modified
qdev_device_add() to check a specific option of the failover device,
"failover_pair_id", before calling the generic mechanism.
It's not needed (and not generic) to do that
On Tue, Oct 19, 2021 at 07:21:24AM +, Xueming(Steven) Li wrote:
> On Tue, 2021-10-19 at 02:37 -0400, Michael S. Tsirkin wrote:
> > On Fri, Oct 08, 2021 at 03:58:05PM +0800, Xueming Li wrote:
> > > When vhost-user vdpa client restart, VQ notifier resources become
> > > invalid, no need to keep m
On Tue, Oct 19, 2021 at 3:21 PM Michael S. Tsirkin wrote:
>
> On Mon, Oct 11, 2021 at 12:28:19PM +0800, Jason Wang wrote:
> > Hi All:
> >
> > This patch implements the multiqueue support for vhost-vDPA. The most
> > important requirement si the control virtqueue support. The virtio-net
> > and vho
On Mon, 18 Oct 2021 23:38:29 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 19 +
target/loongarch/helper.h| 8 +
target/loongarch/insn_trans/trans_core.c | 54 +++
target
This series patch add softmmu support for LoongArch.
Base on the linux-user emulation support V7 patch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The manual:
* https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
Patch 1 Add a readme for
This patch define All the CSR registers and its field.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 493 +
1 file changed, 493 insertions(+)
create mode 100644 target/loongarch/cpu-csr.h
diff --git a/target/loongarch
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 49
include/hw/pci-host/ls7a.h | 4 +++
2 files changed, 53 insertions(+)
diff --git a/hw/loongarch/ls3a5000_virt
This patch add a stabletimer support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 10 +
target/loongarch/csr_helper.c | 26 +
target/loongarch/meson.build | 1 +
target/loongarch/stabletimer
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
|+-++-+ +---
This patch Add loongarch interrupt and exception handle.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 293 +
target/loongarch/cpu.h | 6 +-
2 files changed, 298 insertions(+), 1 deletion(-)
diff --git a/target/loong
This patch introduce vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 12 +++
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 155 +++
target/loongarch/meson.build | 6 ++
4 file
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 284
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 5 +-
target/loongarch/helper.h| 4 ++
target/loongarch/insn_trans/trans_c
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/qapi/machine-targe
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 2 ++
target/loongarch/insn_trans/trans_core.c | 23 +
target/loongarch/insn_trans/trans_extra.c | 2 ++
target/loongarch/op_helper
This patch set default csr values Mainly used for
cpu_initfn and cpu_reset.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 40
target/loongarch/cpu.h | 6 ++
2 files changed, 46 insertions(+)
diff --git a/target/l
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 74 +
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ipi.c | 145 +++
hw/loongarch/ls3a5000_virt.c | 2 +
hw/loongarch/meson.build | 2 +-
include/hw/loongarch/gipi.h
This is a model of the PCIe Host Bridge found on a Loongson-5000
processor. It includes a interrupt controller, some interface for
pci and nonpci devices we only emulate part devices for tcg mode.
It support for MSI and MSIX interrupt sources.
For more detailed info about ls7a1000 you can see the
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 571 +
hw/intc/meson.build| 1 +
hw/loongarch/Kconfig
Le 15/08/2021 à 22:24, Oğuz Ersen a écrit :
> Hi, this is a small patch to update Turkish translation, thanks.
>
> --
> Best Regards
> Oğuz Ersen
>
Applied to my trivial-patches branch.
Thanks,
Laurent
On Mon, 18 Oct 2021 23:38:24 +0800
Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing Mach
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3 +
confi
Le 15/10/2021 à 11:29, Greg Kurz a écrit :
> Fix the comment to match what the code is doing, as explained in
> the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09
> that introduced the change:
>
> Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization
> of vCPU
Le 15/10/2021 à 15:16, Laurent Vivier a écrit :
> This script is not used a lot but it helps to debug migration,
> so it's annoying when we need it and it doesn't work...
>
> The first patch fix an error message that is erroneous and thus
> doesn't help at all.
>
> The second fixes a problem intr
在 2021/9/18 上午10:04, Zhang Chen 写道:
When COLO use only one vnet_hdr_support parameter between
COLO network filter(filter-mirror, filter-redirector or
filter-rewriter and colo-compare, packet will not be parsed
correctly. Acquire network driver related to COLO, if it is
nirtio-net,
Typo.
Cc'ing qemu-triv...@nongnu.org. What about this simple one ?
Before this patch, with "-smp 4, dies=2" for a PC machine, we will
generate warn strings like:
qemu-system-x86_64: warning: CPU(s) not present in any NUMA nodes: CPU 0
[socket-id: 0die-id: 0, core-id: 0, thread-id: 0]
After we will
Le 07/08/2021 à 13:09, Philippe Mathieu-Daudé a écrit :
> After chatting with Richard Henderson and Paolo Bonzini, we
> concluded the load/store API is mature enough to have target
> code endianess-agnostic.
> Thus we could remove the TARGET_WORDS_BIGENDIAN definition from
> target-specific code (r
When vDPA applicaiton in client mode shutdown, unmapped VQ notifier
might being accessed by vCPU thread under high tx traffic, it will
crash VM in rare conditon. This patch try to fix it with better RCU
sychronization of new flatview.
v2: no RCU draining on vCPU thread
v3: minor fix on coding styl
Le 18/10/2021 à 15:45, Greg Kurz a écrit :
> All of these pages live in the wiki, not in the main web site.
>
> Signed-off-by: Greg Kurz
> ---
> README.rst | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/README.rst b/README.rst
> index 79b19f1481e1..237
Le 15/10/2021 à 22:35, Tong Ho a écrit :
> This series fixes memory leaks in Xilinx eFUSE devices for
> the Versal and ZynqMP product families.
>
> The leaks result from failing to free memory allocated
> by object_get_canonical_path().
>
> Tong Ho (3):
> hw/nvram: Fix Memory Leak in Xilinx eFu
On Tue, 2021-10-19 at 03:24 -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 19, 2021 at 07:21:24AM +, Xueming(Steven) Li wrote:
> > On Tue, 2021-10-19 at 02:37 -0400, Michael S. Tsirkin wrote:
> > > On Fri, Oct 08, 2021 at 03:58:05PM +0800, Xueming Li wrote:
> > > > When vhost-user vdpa client r
Add placeholders for DBG2 reference table for
virt tests and ignore till reference blob is added.
Signed-off-by: Eric Auger
Acked-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
tests/data/acpi/virt/DBG2 | 0
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
2 files chang
Le 18/10/2021 à 15:45, Greg Kurz a écrit :
> All of these pages live in the wiki, not in the main web site.
>
> Signed-off-by: Greg Kurz
> ---
> README.rst | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/README.rst b/README.rst
> index 79b19f1481e1..237
Add the DBG2 table generated with
tests/data/acpi/rebuild-expected-aml.sh
Signed-off-by: Eric Auger
Acked-by: Michael S. Tsirkin
---
tests/data/acpi/virt/DBG2 | Bin 0 -> 87 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a
When vhost-user vdpa client restart, VQ notifier mmap address and MR
become invalid, restore MR only is wrong. vdpa client will set VQ
notifier after reconnect.
This patch removes VQ notifier restore and related flags.
Fixes: 44866521bd6e ("vhost-user: support registering external host notifiers"
ARM SBBR specification mandates DBG2 table (Debug Port Table 2)
since v1.0 (ARM DEN0044F 8.3.1.7 DBG2).
The DBG2 table allows to describe one or more debug ports.
Generate an DBG2 table featuring a single debug port, the PL011.
The DBG2 specification can be found at
"Microsoft Debug Port Table 2
When vhost-user device cleanup and unmmap notifier address, VM cpu
thread that writing the notifier failed with accessing invalid address.
To avoid this concurrent issue, wait memory flatview update by draining
rcu callbacks, then unmap notifiers.
Fixes: 44866521bd6e ("vhost-user: support registe
This series generates the ACPI DBG2 table along with machvirt.
The DBG2 specification can be found at
https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table.
DBG2 is mandated by ARM SBBR since its v1.0 release (the rationale
behind is Windows requires it on all sy
Hi Richard,
On 10/18/21 11:00 PM, Richard Henderson wrote:
> On 10/7/21 12:29 AM, Eric Auger wrote:
>> diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/DBG2
>> index
>> e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..86e6314f7b0235ef8ed3e0221e09f996c41f5e98
>> 100644
>> GIT binary patch
>>
On 08/10/2021 15:34, Kevin Wolf wrote:
Instead of accessing the global QemuOptsList, which really belong to the
command line parser and shouldn't be accessed from devices, store a
pointer to the QemuOpts in a new VirtIONet field.
This is not the final state, but just an intermediate step to get
Le 08/10/2021 à 09:50, Yanan Wang a écrit :
> The expected output string from cpu_slot_to_string() ought to be
> like "socket-id: *, die-id: *, core-id: *, thread-id: *", so add
> the missing ", " before "die-id". This affects the readability
> of the error message.
>
> Fixes: 176d2cda0d ("i386/cp
CCing Paolo since kvm-unit-tests use multiboot.
On Sun, Oct 10, 2021 at 09:10:05PM +0200, Adam Lackorzynski wrote:
Use DMA transfers in the multiboot loader to copy
data.
This significantly lowers QEMU's startup latency by
a factor of about 40, for example, going from 30sec
to 0.8sec when loadi
在 2021/10/1 下午3:06, Eugenio Pérez 写道:
This tree is able to look for a translated address from an IOVA address.
At first glance is similar to util/iova-tree. However, SVQ working on
devices with limited IOVA space need more capabilities, like allocating
IOVA chunks or perform reverse translatio
On Fri, Oct 15, 2021 at 6:42 AM Jason Wang wrote:
>
>
> 在 2021/10/15 上午12:39, Eugenio Perez Martin 写道:
> > On Wed, Oct 13, 2021 at 5:47 AM Jason Wang wrote:
> >>
> >> 在 2021/10/1 下午3:05, Eugenio Pérez 写道:
> >>> This will make qemu aware of the device used buffers, allowing it to
> >>> write the g
Recent commit 6952026120 "monitor: Tidy up find_device_state()"
assumed the function's argument is "the device's ID or QOM path" (as
documented for device_del). It's actually either an absolute QOM
path, or a QOM path relative to /machine/peripheral/. Such a relative
path is a device ID when it d
Am 19.10.21 um 10:57 schrieb Markus Armbruster:
Recent commit 6952026120 "monitor: Tidy up find_device_state()"
assumed the function's argument is "the device's ID or QOM path" (as
documented for device_del). It's actually either an absolute QOM
path, or a QOM path relative to /machine/periphera
My main motivation was to convert SubmitAPatch[1] based on a chat with
Peter Maydell and Dan Berrangé on #qemu channel (on OFTC). But the page
also links to a couple of other contribution-related pages, so I
converted them too:
- SubmitAPullRequest: https://wiki.qemu.org/Contribute/SubmitAPullR
The original wiki is here[1]. I converted by copying the wiki source
into a .wiki file and convert to rST using `pandoc`:
$ pandoc -f Mediawiki -t rst trivial-patches.wiki -o trivial-patches.rst
Update the active maintainer names to reflect current reality.
[1] https://wiki.qemu.org/Con
The original wiki is here[1]. I converted by copying the wiki source
into a .wiki file and convert to rST using `pandoc`:
$ pandoc -f Mediawiki -t rst spell-check.wiki -o spell-check.rst
As part of this rST converstion, I've removed the dated and `codespell`
invocations, and linked to the Gi
The original wiki is here[1]. I converted by copying the wiki source
into a .wiki file and convert to rST using `pandoc`:
$ pandoc -f Mediawiki -t rst key-signing-party.wiki -o
key-signing-party.rst
This is a 1-1 conversion; no content changes.
[1] https://wiki.qemu.org/KeySigni
The original wiki is here[1]. I converted by copying the wiki source
into a .wiki file and convert to rST using `pandoc`:
$ pandoc -f Mediawiki -t rst submitting-a-pull-request.wiki \
-o submitting-a-pull-request.rst
This is a 1-1 conversion; no content changes besides updating the
"
Markus Armbruster writes:
> Christian Borntraeger writes:
>
>> Am 13.10.21 um 11:07 schrieb Paolo Bonzini:
>>> From: Markus Armbruster
>>> Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"
>>> extended find_device_state() to accept QOM paths in addition to qdev
>>> IDs. This ad
Add the entries for contributing-related rSTified wiki docs.
Signed-off-by: Kashyap Chamarthy
---
docs/devel/index.rst | 5 +
1 file changed, 5 insertions(+)
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index f95df10b3e..f7bec644f3 100644
--- a/docs/devel/index.rst
+++ b/docs/de
- The original wiki is here[1]. I copied the wiki source[2] into a .wiki
file, and used `pandoc` to convert it to rST:
$> pandoc -f Mediawiki -t rst submitting-a-patch.wiki -o
submitting-a-patch.rst
- The only minor touch-ups I did was to fix URLs. But 99%, it is a 1-1
conversion.
On Tue, Oct 19, 2021 at 11:03:38AM +0200, Kashyap Chamarthy wrote:
> My main motivation was to convert SubmitAPatch[1] based on a chat with
> Peter Maydell and Dan Berrangé on #qemu channel (on OFTC). But the page
> also links to a couple of other contribution-related pages, so I
> converted them
Recent Linux kernels are accessing the PCI device in slot 0 that
represents the PCI host bridge. This causes ppc4xx_pci_map_irq()
to return -1 which causes an assert() later:
hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed.
Thus we should allocate an IRQ line for the
Le 19/10/2021 à 11:03, Kashyap Chamarthy a écrit :
> The original wiki is here[1]. I converted by copying the wiki source
> into a .wiki file and convert to rST using `pandoc`:
>
> $ pandoc -f Mediawiki -t rst trivial-patches.wiki -o
> trivial-patches.rst
>
> Update the active maintaine
On Tue, Oct 19, 2021 at 4:32 PM Jason Wang wrote:
>
>
> 在 2021/10/1 下午3:06, Eugenio Pérez 写道:
> > This tree is able to look for a translated address from an IOVA address.
> >
> > At first glance is similar to util/iova-tree. However, SVQ working on
> > devices with limited IOVA space need more cap
在 2021/10/1 下午3:06, Eugenio Pérez 写道:
Use translations added in VhostIOVATree in SVQ.
Now every element needs to store the previous address also, so VirtQueue
can consume the elements properly. This adds a little overhead per VQ
element, having to allocate more memory to stash them. As a possi
On Tue, Oct 19, 2021 at 05:40:13AM +0200, Philippe Mathieu-Daudé wrote:
> +Stefan
>
> On 10/18/21 20:07, Ari Sundholm wrote:
> > AIO discards regressed as a result of the following commit:
> > 0dfc7af2 block/file-posix: Optimize for macOS
> >
> > When trying to run blkdiscard within a Linux g
While there are a number of uses in the code-base of the exit(0)
pattern it gets in the way of clean exit which can do all of it's
house-keeping. In particular it was reported that you can crash
plugins this way because TCG can still be running on other threads
when the atexit callback is called.
From: Lukas Straub
To: qemu-devel
Cc: "Dr. David Alan Gilbert" , Juan Quintela
, Peter Xu , Leonardo Bras Soares
Passos
Date: Wed, 1 Sep 2021 17:58:57 +0200 (1 week, 15 hours, 17 minutes ago)
[[PGP Signed Part:No public key for 35AB0B289C5DB258 created at
2021-09-01T17:58:57+0200 using RSA]
From: Li Zhijian
The responder mr registering with ODP will sent RNR NAK back to
the requester in the face of the page fault.
-
ibv_poll_cq wc.status=13 RNR retry counter exceeded!
ibv_poll_cq wrid=WRITE RDMA!
-
ibv_advise_mr(3) helps to make pages present before the actual IO is
From: Li Zhijian
To: , ,
CC: Li Zhijian
Date: Sat, 31 Jul 2021 22:05:51 +0800 (5 weeks, 4 days, 17 hours ago)
multifd with unsupported protocol will cause a segment fault.
(gdb) bt
#0 0x563b4a93faf8 in socket_connect (addr=0x0, errp=0x7f7f02675410) at
../util/qemu-sockets.c:1190
#1 0x0
From: Lukas Straub
To: qemu-devel
Cc: "Dr. David Alan Gilbert" , Juan Quintela
, Peter Xu , Leonardo Bras Soares
Passos
Date: Wed, 4 Aug 2021 21:26:32 +0200 (5 weeks, 11 hours, 52 minutes ago)
[[PGP Signed Part:No public key for 35AB0B289C5DB258 created at
2021-08-04T21:26:32+0200 using RSA
The following changes since commit 362534a643b4a34bcb223996538ce9de5cdab946:
Merge remote-tracking branch
'remotes/bsdimp/tags/pull-bsd-user-20211018-pull-request' into staging
(2021-10-18 12:17:24 -0700)
are available in the Git repository at:
https://github.com/juanquintela/qemu.git tags
From: Li Zhijian
Previously, for the fsdax mem-backend-file, it will register failed with
Operation not supported. In this case, we can try to register it with
On-Demand Paging[1] like what rpma_mr_reg() does on rpma[2].
[1]:
https://community.mellanox.com/s/article/understanding-on-demand-pagi
From: Li Zhijian
To: , ,
CC: Li Zhijian
Date: Sat, 31 Jul 2021 22:05:52 +0800 (5 weeks, 4 days, 17 hours ago)
And change the default to true so that in '-incoming defer' case, user is able
to change multifd capability.
Signed-off-by: Li Zhijian
Reviewed-by: Juan Quintela
Signed-off-by: Juan
From: David Hildenbrand
The parameter is unused, let's drop it.
Reviewed-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Juan Quintela
Signed-off-by: David Hildenbrand
Signed-off-by: Juan Quintela
---
migration/ram.c | 13 +
1 file changed, 5 insertions(+), 8 dele
Le 11/10/2021 à 15:24, Thomas Huth a écrit :
On 11/10/2021 11.20, David Gibson wrote:
On Mon, Oct 11, 2021 at 10:10:36AM +0200, Thomas Huth wrote:
On 06/10/2021 09.25, Thomas Huth wrote:
On 05/10/2021 23.53, BALATON Zoltan wrote:
[...]
Maybe these 405 boards in QEMU ran with modified firmw
On 19/10/2021 11.31, Christophe Leroy wrote:
Le 11/10/2021 à 15:24, Thomas Huth a écrit :
On 11/10/2021 11.20, David Gibson wrote:
On Mon, Oct 11, 2021 at 10:10:36AM +0200, Thomas Huth wrote:
On 06/10/2021 09.25, Thomas Huth wrote:
On 05/10/2021 23.53, BALATON Zoltan wrote:
[...]
Maybe the
On Tue, 19 Oct 2021 11:31:03 +0200
Christophe Leroy wrote:
>
>
> Le 11/10/2021 à 15:24, Thomas Huth a écrit :
> > On 11/10/2021 11.20, David Gibson wrote:
> >> On Mon, Oct 11, 2021 at 10:10:36AM +0200, Thomas Huth wrote:
> >>> On 06/10/2021 09.25, Thomas Huth wrote:
> On 05/10/2021 23.53,
Introducing unsigned quad, signed quad, and octo accesses types
to handle load and store by 128-bit processors.
Signed-off-by: Frédéric Pétrot
---
include/exec/memop.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index c55
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
This v3 is based on Richard proposal for handling correctly the various
register sizes (v4 version of his series).
As compared to the v2, it simplifies a bit the
Le 19/10/2021 à 11:39, Thomas Huth a écrit :
On 19/10/2021 11.31, Christophe Leroy wrote:
Le 11/10/2021 à 15:24, Thomas Huth a écrit :
On 11/10/2021 11.20, David Gibson wrote:
On Mon, Oct 11, 2021 at 10:10:36AM +0200, Thomas Huth wrote:
On 06/10/2021 09.25, Thomas Huth wrote:
On 05/10/2
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Signed-off-by: Frédéric Pétro
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 5 -
2 files changed, 5 insertion
Addition of not, xor, div and rem on 128-bit integers, used in particular
within div/rem and csr helpers for computations on 128-bit registers.
These will be used by the 128-bit riscv version.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
include/qemu/int128.h | 264 +
On Mon, 18 Oct 2021 17:31:33 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Sep 02, 2021 at 07:35:40AM -0400, Igor Mammedov wrote:
> > Set -smp 1,maxcpus=288 to test for ACPI code that
> > deal with CPUs with large APIC ID (>255).
> >
> > PS:
> > Test requires KVM and in-kernel irqchip support,
> >
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. Most of these modifications have to deal
with changing what was a binary choice into a ternary one. Although we did
our best to avoid testing for TARGET_RISCV128 (which we did), it is
implici
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
wher
The 128-bit ISA adds ldu, lq and sq. We provide here support for these
instructions. Note that although we compute a 128-bit address, we only use
the lower 64-bit to actually address memory, cowardly utilizing the
existing address translation mechanism of QEMU.
Signed-off-by: Frédéric Pétrot
Co-a
Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/translate.c
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/translate.c | 22 ++
1 file ch
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/insn32.decode | 10 +
target/riscv/translate.c
Changed MO_Q into MO_UQ so as to avoid confusion, as suggested by
Philippe Mathieu-Daudé.
Signed-off-by: Frédéric Pétrot
---
include/exec/memop.h | 8
target/arm/translate-a32.h | 4 ++--
target/arm/translate-a64.c | 8
t
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