Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
---
target/riscv/translate.c | 27 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 6 +++---
target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
3 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 121fcd71fe..3c2e9fb790 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -382,6 +382,33 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
/* Include the auto-generated decoder for 32 bit insn */
#include "decode-insn32.c.inc"
+static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, target_long))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ func(dest, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ func(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index cc39e6033b..28f911f95d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -86,19 +86,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_ZBB(ctx);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_ZBB(ctx);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_ZBB(ctx);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
static bool trans_min(DisasContext *ctx, arg_min *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 91dc438a3a..ed138f748e 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -250,17 +250,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
@@ -317,7 +317,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -332,12 +332,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
--
2.33.0
