[PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions

[Frédéric Pétrot]

The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.

Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
---
 target/riscv/translate.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e8f08f921e..71982f6284 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -429,6 +429,17 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 
DisasExtend ext,
 
     gen_set_gpr(ctx, a->rd, dest);
 
+    if (get_xl_max(ctx) == MXL_RV128) {
+        if (get_ol(ctx) ==  MXL_RV128) {
+            uint64_t immh = -(a->imm < 0);
+            src1 = get_gprh(ctx, a->rs1);
+            dest = dest_gprh(ctx, a->rd);
+
+            func(dest, src1, immh);
+        }
+        gen_set_gprh(ctx, a->rd, dest);
+    }
+
     return true;
 }
 
@@ -443,6 +454,17 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, 
DisasExtend ext,
 
     gen_set_gpr(ctx, a->rd, dest);
 
+    if (get_xl_max(ctx) == MXL_RV128) {
+        if (get_ol(ctx) ==  MXL_RV128) {
+            dest = dest_gprh(ctx, a->rd);
+            src1 = get_gprh(ctx, a->rs1);
+            src2 = get_gprh(ctx, a->rs2);
+
+            func(dest, src1, src2);
+        }
+        gen_set_gprh(ctx, a->rd, dest);
+    }
+
     return true;
 }
 
-- 
2.33.0