From: Alistair Francis
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: LIU Zhiwei
Message-id:
946e1ef5e268b24084c7ddad84c146de62
From: Alistair Francis
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.fran...@wdc.com
---
docs/system/riscv/sifive_u.rst | 1 +
include/hw/ris
From: Alistair Francis
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Message-i
From: Anup Patel
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id: 20210831110603.338681-2-anup.pa...@wdc.com
Signed-off-by: Alistair F
From: Frank Chang
Real PDMA doesn't set Control.error if there are 0 bytes to be
transferred. The DMA transfer is still success.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x300 0x0 <= Disclaim channel 0
=> mw.l 0x300 0x1
From: Anup Patel
We re-factor and break the FDT generation into smaller functions
so that it is easier to modify FDT generation for different
configurations of virt machine.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id: 20210831110603.338681-4-anup.
From: Alistair Francis
This is the initial commit of the SiFive PWM timer. This is used by
guest software as a timer and is included in the SiFive FU540 SoC.
Signed-off-by: Justin Restivo
Signed-off-by: Alexandra Clifford
Signed-off-by: Amanda Strnad
Signed-off-by: Alistair Francis
Reviewed-
From: Anup Patel
We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id: 20210831110603.338681-5-anup.pa...@wdc.com
Signed
From: Frank Chang
Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will be transferred.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x300 0x0 <= Disclaim channel
From: Bin Meng
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210915084601.24304-1-bmeng...@gmail.com
Sig
From: Anup Patel
The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.
Signed-off-by: Anup Patel
Reviewed-by: Ali
From: Bin Meng
In U-Boot v2021.07 release, there were 2 major changes for the
SiFive Unleashed board support:
- Board config name was changed from sifive_fu540_defconfig to
sifive_unleashed_defconfig
- The generic binman tool was used to generate the FIT image
(combination of U-Boot proper,
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
d6cb4dfe75a2f536f217d7075b750ece3acb1535.1631767043.git.alistair.fran...@wdc.com
Signed-off-by: Alistair Francis
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Frank Chang
When virtual registers are swapped, mstatus.SD bit should also be
backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
across the world switches.
Signed-off-by: Frank Chang
Reviewed-by: Vincent Chen
Reviewed-by: Alistair Francis
Message-id: 20210914013717.8
From: Frank Chang
Setting Control.claim clears all of the chanel's Next registers.
This is effective only when Control.claim is set from 0 to 1.
Signed-off-by: Frank Chang
Tested-by: Max Hsu
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Message-id: 20210912130553.179501-2-frank.ch...@sifive.com
On Tue, 21 Sep 2021 08:56:52 +0200
Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
> ---
Maybe add ?
Fixes: 4e960974d4ee ("xive: Add trace events")
anyway
Reviewed-by: Greg Kurz
> hw/intc/spapr_xive_kvm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --gi
Signed-off-by: Cédric Le Goater
---
hw/intc/spapr_xive_kvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 53731d158625..7ac2502cc013 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -236,6
From: Green Wan
Real PDMA is able to deal with non-multiple transaction size transactions.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x300 0x0 <= Disclaim channel 0
=> mw.l 0x300 0x1 <= Claim channel 0
=> mw.l 0x3
On 9/21/21 08:02, WANG Xuerui wrote:
On 9/21/21 01:23, Richard Henderson wrote:
On 9/20/21 1:04 AM, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
---
configure | 4 +++-
meson.build | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
If there's no loongarch32, and never will be,
Hi Philippe,
On 9/21/21 14:59, Philippe Mathieu-Daudé wrote:
On 9/21/21 08:02, WANG Xuerui wrote:
On 9/21/21 01:23, Richard Henderson wrote:
On 9/20/21 1:04 AM, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
---
configure | 4 +++-
meson.build | 4 +++-
2 files changed, 6 insertions(+),
On 19/09/2021 22:10, Philippe Mathieu-Daudé wrote:
On 9/16/21 12:05, Mark Cave-Ayland wrote:
Since there is no need to generate a dummy declaration ROM, remove both
nubus_register_rom() and nubus_register_format_block(). These will shortly be
replaced with a mechanism to optionally load a decla
On 21/09/21 07:39, Hannes Reinecke wrote:
It would, but then anyone attempting to use tapes via qemu emulation
deserves to suffer.
Tapes are bitchy even when used normally, so attempting to use them
under qemu emulation will land you with lots of unhappy experiences,
where the timeout is the le
On 9/21/21 05:25, David Gibson wrote:
On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:
- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/we
On Mon, 20 Sep 2021 18:21:22 +0200
Eric Auger wrote:
> Hi,
>
> On 9/7/21 4:47 PM, Igor Mammedov wrote:
> > it replaces error-prone pointer arithmetic for build_header() API,
> > with 2 calls to start and finish table creation,
> > which hides offests magic from API user.
> >
> > While at it swi
On Fri, 17 Sep 2021 18:28:02 -0300
Daniel Henrique Barboza wrote:
> numa_complete_configuration() in hw/core/numa.c always adds a NUMA node
> for the pSeries machine if none was specified, but without node distance
> information for the single node created.
>
> NUMA FORM1 affinity code didn't re
On Mon, 20 Sept 2021 at 22:16, Philippe Mathieu-Daudé wrote:
> Forget this crap. The missing piece was:
>
> -- >8 --
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 0d5adccf1a7..da348938407 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -23,6 +23,11 @@
>
On 9/20/21 22:21, Alexander Graf wrote:
On 20.09.21 18:17, Philippe Mathieu-Daudé wrote:
On 9/20/21 15:15, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 11:11, Peter Maydell wrote:
On Thu, 16 Sept 2021 at 16:54, Alexander Graf wrote:
Now that Apple Silicon is widely available, people are obv
On Mon, 20 Sept 2021 at 22:44, Philippe Mathieu-Daudé wrote:
>
> Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU.
>
> See the comments added in commit 7ecdaa4a963 ("armv7m: Fix
> condition check for taking exceptions") which eventually
> forgot to implement this has_work() handler:
This commit adds emulation of the magnetometer on the LSM303DLHC.
It allows the magnetometer's X, Y and Z outputs to be set via the
mag-x, mag-y and mag-z properties, as well as the 12-bit
temperature output via the temperature property.
Signed-off-by: Kevin Townsend
---
hw/sensor/Kconfig
On Tue, Sep 21, 2021 at 10:13:36AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/21/21 05:25, David Gibson wrote:
> > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > > The reset value of IPIDR should be zero for Freescale chipset, per
> > > the following 2 manuals I checked:
> > >
> >
On 9/21/21 11:28, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 22:16, Philippe Mathieu-Daudé wrote:
Forget this crap. The missing piece was:
-- >8 --
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0d5adccf1a7..da348938407 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_t
On 9/21/21 11:34, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 22:44, Philippe Mathieu-Daudé wrote:
Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU.
See the comments added in commit 7ecdaa4a963 ("armv7m: Fix
condition check for taking exceptions") which eventually
forgot to imp
On Tue, 21 Sept 2021 at 10:41, Philippe Mathieu-Daudé wrote:
>
> On 9/21/21 11:28, Peter Maydell wrote:
> > On Mon, 20 Sept 2021 at 22:16, Philippe Mathieu-Daudé
> > wrote:
> >> Forget this crap. The missing piece was:
> >>
> >> -- >8 --
> >> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tc
On 9/20/21 10:04, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
---
tcg/loongarch/tcg-insn-defs.c.inc | 1080 +
1 file changed, 1080 insertions(+)
create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc
+static int32_t encode_dj_slots(LoongArchInsn opc, uint32_t
From: Hanna Reitz
Finalizing the job may cause its AioContext to change. This is noted by
job_exit(), which points at job_txn_apply() to take this fact into
account.
However, job_completed() does not necessarily invoke job_txn_apply()
(through job_completed_txn_success()), but potentially also
From: Hanna Reitz
We largely have two cancel modes for jobs:
First, there is actual cancelling. The job is terminated as soon as
possible, without trying to reach a consistent result.
Second, we have mirror in the READY state. Technically, the job is not
really cancelled, but it just is a dif
From: Hanna Reitz
Most callers of job_is_cancelled() actually want to know whether the job
is on its way to immediate termination. For example, we refuse to pause
jobs that are cancelled; but this only makes sense for jobs that are
really actually cancelled.
A mirror job that is cancelled durin
From: Hanna Reitz
When a transaction is aborted, no result matters, and so all jobs within
should be force-cancelled.
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20210907124245.143492-5-hre...@redhat.com>
Signed-off-by: Vladimir Se
From: Hanna Reitz
Once the mirror job is force-cancelled (job_is_cancelled() is true), we
should not generate new I/O requests. This applies to active mirroring,
too, so stop it once the job is cancelled.
(We must still forward all I/O requests to the source, though, of
course, but those are no
From: Hanna Reitz
As of HEAD^, there is no meaning to s->synced other than whether the job
is READY or not. job_is_ready() gives us that information, too.
Suggested-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
From: Hanna Reitz
An error does not take us out of the READY phase, which is what
s->synced signifies. It does of course mean that source and target are
no longer in sync, but that is what s->actively_sync is for -- s->synced
never meant that source and target are in sync, only that they were at
The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac:
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into
staging (2021-09-20 16:17:05 +0100)
are available in the Git repository at:
https://src.openvz.org/scm/~vsementsov/qemu.git tags/pull-jobs-
From: Hanna Reitz
Clearing .cancelled before leaving the main loop when the job has been
soft-cancelled is no longer necessary since job_is_cancelled() only
returns true for jobs that have been force-cancelled.
Therefore, this only makes a differences in places that call
job_cancel_requested().
From: Hanna Reitz
Callers should be able to specify whether they want job_cancel_sync() to
force-cancel the job or not.
In fact, almost all invocations do not care about consistency of the
result and just want the job to terminate as soon as possible, so they
should pass force=true. The replica
From: Hanna Reitz
Test what happens when there is an I/O error after a mirror job in the
READY phase has been cancelled.
Signed-off-by: Hanna Reitz
Reviewed-by: Vladimir Sementsov-Ogievskiy
Tested-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20210907124245.143492-13-hre...@redhat.com>
Signed
We have to consider the device id, otherwise we'll lose some events for
unrelated devices. If the device does not have a device id (very unlikely),
the target of the notifications has to update the size of all devices
manually either way.
This was noticed by starting a VM with two virtio-mem devic
From: Hanna Reitz
mirror_drained_poll() returns true whenever the job is cancelled,
because "we [can] be sure that it won't issue more requests". However,
this is only true for force-cancelled jobs, so use job_is_cancelled().
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vla
From: Hanna Reitz
We must check whether the job is force-cancelled early in our main loop,
most importantly before any `continue` statement. For example, we used
to have `continue`s before our current checking location that are
triggered by `mirror_flush()` failing. So, if `mirror_flush()` kept
Philippe Mathieu-Daudé writes:
> (Cc'ing qemu-devel@ mailing list since this is a development question).
>
> On 9/19/21 19:44, Robert Henry wrote:
>> What is the range of the values for vcpu_index given to callbacks, such as:
>>
>> typedef void (*qemu_plugin_vcpu_udata_cb_t)(unsigned int vcpu_
On Thu, 5 Aug 2021 18:30:39 -0400
Eric DeVolder wrote:
> Following the guidelines in tests/qtest/bios-tables-test.c, this
> is step 6, the re-generated ACPI tables binary blobs.
commit message should include ASL diff for new/changed content
for example see commit:
1aaef7d8092803 acpi: unit-te
On Thu, 5 Aug 2021 18:30:38 -0400
Eric DeVolder wrote:
> This change implements the test suite checks for the ERST table.
>
> Signed-off-by: Eric DeVolder
> ---
> tests/qtest/bios-tables-test.c | 43
> ++
> 1 file changed, 43 insertions(+)
>
> diff --
On Thu, 5 Aug 2021 18:30:32 -0400
Eric DeVolder wrote:
> This change reserves the PCI device_id for the new ACPI ERST
> device.
>
> Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
> ---
> include/hw/pci/pci.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/hw/pci/pci
Hi Philippe,
On 9/21/21 17:58, Philippe Mathieu-Daudé wrote:
On 9/20/21 10:04, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
---
tcg/loongarch/tcg-insn-defs.c.inc | 1080 +
1 file changed, 1080 insertions(+)
create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc
On Sat, 18 Sept 2021 at 10:34, Paolo Bonzini wrote:
>
> The following changes since commit 831aaf24967a49d7750090b9dcfd6bf356f16529:
>
> Merge remote-tracking branch 'remotes/marcandre/tags/misc-pull-request'
> into staging (2021-09-14 18:14:56 +0100)
>
> are available in the Git repository at:
On Tue, Sep 21, 2021 at 01:40:36PM +0100, Peter Maydell wrote:
> On Sat, 18 Sept 2021 at 10:34, Paolo Bonzini wrote:
> >
> > The following changes since commit 831aaf24967a49d7750090b9dcfd6bf356f16529:
> >
> > Merge remote-tracking branch 'remotes/marcandre/tags/misc-pull-request'
> > into stag
On Tue, 21 Sept 2021 at 13:48, Daniel P. Berrangé wrote:
>
> On Tue, Sep 21, 2021 at 01:40:36PM +0100, Peter Maydell wrote:
> > Is there anything that can be done to make meson version bumps
> > not a horrific pain to back out ? This seems to go wrong pretty
> > much every time.
>
> Save your prev
On 21/09/21 14:40, Peter Maydell wrote:
Is there anything that can be done to make meson version bumps
not a horrific pain to back out ? This seems to go wrong pretty
much every time.
Downgrading works fine in 0.58 and newer releases, but the fix is not in
0.55.x. The reason why it goes wrong
On 21/09/21 14:40, Peter Maydell wrote:
even after having blown
away the build directory and re-created it:
Doesn't look like you fully blew away the build directory though.
Paolo
On Wed, 15 Sept 2021 at 05:28, Markus Armbruster wrote:
>
> Peter Maydell writes:
> > I'm not sure how best to sort this tangle out. We could:
> > * make controller devices pass in NULL as bus name; this
> >means that some bus names will change, which is an annoying
> >breakage but for t
On 21.09.21 11:29, Philippe Mathieu-Daudé wrote:
> On 9/20/21 22:21, Alexander Graf wrote:
>> On 20.09.21 18:17, Philippe Mathieu-Daudé wrote:
>>> On 9/20/21 15:15, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 11:11, Peter Maydell
wrote:
> On Thu, 16 Sept 2021 at 16:54, Alexander G
On 9/20/21 11:02 PM, WANG Xuerui wrote:
The loongarch32 tuple will most certainly come into existence some time in the future, but
probably bare-metal-only and without a Linux port AFAIK.
Ok, I'll bear that in mind when considering target/loongarch/.
So should I drop the explicit probing for _
Hello!!
On Tue, Sep 21, 2021 at 07:25:42AM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > But, in anyway, I'll still need to store the target architecture that
> > can use such core module, like I did here in this patch. Otherwise,
> > if I compile different targets at the same time, I'll end up with
Hello!!
On Mon, Sep 20, 2021 at 09:03:28PM +0200, Paolo Bonzini wrote:
> On 20/09/21 15:02, Jose R. Ziviani wrote:
> > But, in anyway, I'll still need to store the target architecture that
> > can use such core module, like I did here in this patch. Otherwise,
> > if I compile different targets at
On Tue, 19 Jan 2021 at 15:57, Alex Bennée wrote:
>
>
> Claudio Fontana writes:
>
> > On 1/19/21 3:50 PM, Alex Bennée wrote:
> >>
> >> Claudio Fontana writes:
> >>> qemu-system-aarch64: -gdb
> >>> unix:path=/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEMU
> >>> waiting for connect
Hi Richard,
On 9/21/21 21:30, Richard Henderson wrote:
On 9/20/21 11:02 PM, WANG Xuerui wrote:
So should I drop the explicit probing for __loongarch64, instead just
probe for __loongarch__ and later #error out the non-__loongarch64
cases individually?
I'm ok with checking the __loongarch64
On Mon, 20 Sept 2021 at 09:09, Cédric Le Goater wrote:
>
> The following changes since commit c99e34e537f13a431a80e3e414e5904e9dd0a116:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging
> (2021-09-16 21:09:18 +0100)
>
> are available in the
On 9/21/21 22:07, WANG Xuerui wrote:
Hi Richard,
On 9/21/21 21:30, Richard Henderson wrote:
On 9/20/21 11:02 PM, WANG Xuerui wrote:
So should I drop the explicit probing for __loongarch64, instead
just probe for __loongarch__ and later #error out the
non-__loongarch64 cases individually?
Use consistent capitalization, and fix a missed line (we duplicate the
qemu-img synopses in too many places).
Fixes: 1899bf4737 (qemu-img: Add -F shorthand to convert)
Signed-off-by: Eric Blake
---
docs/tools/qemu-img.rst | 2 +-
qemu-img-cmds.hx| 2 +-
2 files changed, 2 insertions(+),
Am 20.09.2021 um 13:55 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Use bdrv_new_open_driver_opts() instead of complicated bdrv_open().
>
> Among other extra things bdrv_open() also check for white-listed
> formats, which we don't want for internal node creation: currently
> backup doesn't work
On Mon, 20 Sept 2021 at 18:25, Richard Henderson
wrote:
>
> On 9/20/21 1:04 AM, WANG Xuerui wrote:
> > Signed-off-by: WANG Xuerui
> Be consistent with loongarch or loongarch64 everywhere.
>
> If there's no loongarch32, and never will be, then there's probably no point
> in keeping
> the '64' su
21.09.2021 17:28, Eric Blake wrote:
Use consistent capitalization, and fix a missed line (we duplicate the
qemu-img synopses in too many places).
Fixes: 1899bf4737 (qemu-img: Add -F shorthand to convert)
Signed-off-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vla
On Mon, 20 Sept 2021 at 14:19, Richard Henderson
wrote:
>
> On 9/20/21 3:07 AM, Peter Maydell wrote:
> > This seems to result in a failure on the s390x all-linux-static
> > CI job:
> > https://gitlab.com/qemu-project/qemu/-/jobs/1604251543
> > due to a core dump running the 'trap' test.
>
> Curiou
On Thu, 5 Aug 2021 18:30:34 -0400
Eric DeVolder wrote:
> This implements a PCI device for ACPI ERST. This implements the
> non-NVRAM "mode" of operation for ERST as it is supported by
> Linux and Windows.
>
> Signed-off-by: Eric DeVolder
> ---
> hw/acpi/erst.c | 750
> +
On Thu, 16 Sept 2021 at 16:54, Alexander Graf wrote:
>
> With Apple Silicon available to the masses, it's a good time to add support
> for driving its virtualization extensions from QEMU.
>
> This patch adds all necessary architecture specific code to get basic VMs
> working, including save/restor
ository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210921
for you to fetch changes up to 4b445c926add3fdec13958736e482e88857bcad8:
target/arm: Optimize MVE 1op-immediate insns (2021-09-21 16:2
On Tue, Sep 21, 2021 at 10:35:04AM -0300, Jose R. Ziviani wrote:
> Hello!!
>
> On Tue, Sep 21, 2021 at 07:25:42AM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > > But, in anyway, I'll still need to store the target architecture that
> > > can use such core module, like I did here in this patch. Ot
On Tue, 21 Sep 2021, Peter Maydell wrote:
On Wed, 15 Sept 2021 at 05:28, Markus Armbruster wrote:
Peter Maydell writes:
I'm not sure how best to sort this tangle out. We could:
* make controller devices pass in NULL as bus name; this
means that some bus names will change, which is an ann
On 9/21/21 7:42 AM, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 18:25, Richard Henderson
wrote:
On 9/20/21 1:04 AM, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Be consistent with loongarch or loongarch64 everywhere.
If there's no loongarch32, and never will be, then there's probably n
Hi Peter,
On 9/21/21 22:42, Peter Maydell wrote:
On Mon, 20 Sept 2021 at 18:25, Richard Henderson
wrote:
On 9/20/21 1:04 AM, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Be consistent with loongarch or loongarch64 everywhere.
If there's no loongarch32, and never will be, then there's prob
This series includes 2 patches: the first is similar of v1, but using
OnOffAuto property.
The second patch moves the `seqpacket` handling in the vhost-vsock-common
class to reuse the same code/properties also in vhost-user-vsock devices.
Perhaps the patches can be merged into a single one, but to
virtio-vsock features, like VIRTIO_VSOCK_F_SEQPACKET, can be handled
by vhost-vsock-common parent class. In this way, we can reuse the
same code for all virtio-vsock backends (i.e. vhost-vsock,
vhost-user-vsock).
Let's move `seqpacket` property to vhost-vsock-common class, add
vhost_vsock_common_g
Now that commit 5a1cfd21 has clarified that a driver's block_status
can report larger *pnum than in the original request, we can take
advantage of that in the NBD driver. Rather that limiting our request
to the server based on the maximum @bytes our caller mentioned, we
instead ask for as much sta
Commit 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")
enabled the SEQPACKET feature bit.
This commit is released with QEMU 6.1, so if we try to migrate a VM where
the host kernel supports SEQPACKET but machine type version is less than
6.1, we get the following errors:
Features
The aarch64-linux QEMU usermode binaries can never run 32-bit
code, so they do not need to include the GDB XML for it.
(arm_cpu_register_gdb_regs_for_features() will not use these
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
advertise to gdb that we have them.)
Signed-off-by: Peter
We're going to move this code to a different file; fix the coding
style first so checkpatch doesn't complain. This includes deleting
the spurious 'break' statements after returns in the
vfp_gdb_get_reg() function.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 23 ---
Currently helper.c includes some code which is part of the arm
target's gdbstub support. This code has a better home: in gdbstub.c
and gdbstub64.c. Move it there.
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
into gdbstub64.c, this means that they're now compiled only for
This patchset's aim is to report MVE to gdb via the gdbstub.
That is done by the final patch, which is an RFC because the
gdb patches to support it are not yet upstream and so the XML
format isn't final. (Sending the XML works fine with a GDB
without the MVE support; you just don't get the auto-gen
Cortex-M CPUs with MVE should advertise this fact to gdb, using the
org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR
register. Presence of this feature also tells gdb to create
pseudo-registers Q0..Q7, so we do not need to tell gdb about them
separately.
Note that unless you have
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
definition of this XML feature does not include FPSID or FPEXC. In
particular, for M-profile cores there are no FPSID or FPEXC
registers, so advertising those is wron
On 21.09.21 17:30, Peter Maydell wrote:
> On Thu, 16 Sept 2021 at 16:54, Alexander Graf wrote:
>> With Apple Silicon available to the masses, it's a good time to add support
>> for driving its virtualization extensions from QEMU.
>>
>> This patch adds all necessary architecture specific code to
On 20/09/2021 18:31, Laurent Vivier wrote:
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
This prepares for allowing Nubus devices to be placed in a specific slot instead
of always being auto-allocated by the bus itself.
Signed-off-by: Mark Cave-Ayland
---
hw/nubus/nubus-device.c | 6 ++
' into staging
> (2021-09-19 18:53:29 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20210921
>
> for you to fetch changes up to 4b445c926add3fdec13958736e482e88857bcad8:
>
> t
On 20/09/2021 20:48, Laurent Vivier wrote:
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
Convert nubus_device_realize() to use a bitmap to manage available slots to
allow
for future Nubus devices to be plugged into arbitrary slots from the command
line.
Update mac_nubus_bridge_init() to
On 9/21/21 9:09 AM, WANG Xuerui wrote:
I think cpu=loongarch64 but ARCH=loongarch should be okay...
Make it easier on yourself and keep them the same.
r~
21.09.2021 19:17, Eric Blake wrote:
Now that commit 5a1cfd21 has clarified that a driver's block_status
can report larger *pnum than in the original request, we can take
advantage of that in the NBD driver. Rather that limiting our request
to the server based on the maximum @bytes our caller men
On Tue, Sep 21, 2021 at 08:25:11PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 21.09.2021 19:17, Eric Blake wrote:
> > Now that commit 5a1cfd21 has clarified that a driver's block_status
> > can report larger *pnum than in the original request, we can take
> > advantage of that in the NBD driver.
On 9/21/21 18:28, Peter Maydell wrote:
We're going to move this code to a different file; fix the coding
style first so checkpatch doesn't complain. This includes deleting
the spurious 'break' statements after returns in the
vfp_gdb_get_reg() function.
Signed-off-by: Peter Maydell
---
target
On 9/21/21 18:28, Peter Maydell wrote:
Currently helper.c includes some code which is part of the arm
target's gdbstub support. This code has a better home: in gdbstub.c
and gdbstub64.c. Move it there.
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
into gdbstub64.c, this
Add basic support for CLONE_PIDFD, only fork-like clone without additional
flags. This is enough to make Qt/forkfd working.
Signed-off-by: Andreas Schwab
---
linux-user/syscall.c | 52 ++--
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/li
21.09.2021 21:08, Eric Blake wrote:
On Tue, Sep 21, 2021 at 08:25:11PM +0300, Vladimir Sementsov-Ogievskiy wrote:
21.09.2021 19:17, Eric Blake wrote:
Now that commit 5a1cfd21 has clarified that a driver's block_status
can report larger *pnum than in the original request, we can take
advantage o
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