Re: QEMU-KVM offers OPAL firmware interface? OpenBSD guest support?

Hi Mark, Cédric, Greg at the openbsd-ppc ML, It is great to talk to you. Thank you for taking on the conversation. Right, OpenBSD implements powernv meaning it runs on bare metal on Power9, that is great. What I wanted to ask about with this thread is: To have the same utility of Power9 as of A

Re: QEMU-KVM offers OPAL firmware interface? OpenBSD guest support?

> runs Linux powernv bare metal on Power9 hardware. Each VM is a > KVM-QEMU instance. > > > If you want to also run OpenBSD inside a VM, then OpenBSD must > > > implement proper support to be able to run in the paravirtualized > > > PAPR environment provided by KVM-QEMU on POWER. The OpenBSD state

[PATCH 1/3] escc: checkpatch fixes

Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 160 + 1 file changed, 96 insertions(+), 64 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 52e7978287..63e0f15dfa 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -230,20 +230

[PATCH 3/3] escc: fix STATUS_SYNC bit in R_STATUS register

After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should remain high until the flag byte has been detected. Whilst the ESCC device doesn't yet implement SDLC mode, without this change the active low STATUS_SYNC is constantly asserted causing the MacOS OpenTransport extension to

[PATCH 0/3] escc: fix R_STATUS when SDLC mode is enabled

Here is another small set of ESCC fixes from my attempts to boot MacOS on the q800 machine. When MacOS loads the OpenTransport extension on boot it attempts to enable SDLC mode on the ESCC. QEMU's emulation doesn't support SDLC mode, but without these fixes the active low STATUS_SYNC bit in R_STA

[PATCH 2/3] escc: fix R_STATUS channel reset value

According to the "Z80X30 Register Reset Values" table in the ESCC datasheet bits 2 and 6 are set whilst bits 0 and 1 are cleared during channel reset. All other bits should be left unaltered. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 9 - 1 file changed, 4 insertions(+), 5 del

Re: [PATCH] Report any problems with loading the VGA driver for PPC Macintosh targets

On 27/08/2021 19:14, John Arbuckle wrote: I was having a problem with missing video resolutions in my Mac OS 9 VM. When I ran QEMU it gave no indication as to why these resolutions were missing. I found out that the OpenFirmware VGA driver was not being loaded. To prevent anyone from going thru

Re: [PATCH] Report any problems with loading the VGA driver for PPC Macintosh targets

On Sun, 29 Aug 2021 at 11:18, Mark Cave-Ayland wrote: > What I don't understand is that the binary is installed by default in QEMU's > sharedir > so everything works out of the box with "make install". Do you have some kind > of > custom installer which is doing something different? John has ha

Re: [PATCH 1/3] escc: checkpatch fixes

On Sun, 29 Aug 2021 at 11:04, Mark Cave-Ayland wrote: > > Signed-off-by: Mark Cave-Ayland > --- > hw/char/escc.c | 160 + > 1 file changed, 96 insertions(+), 64 deletions(-) Reviewed-by: Peter Maydell You might want to fix this existing typo: >

Re: [PATCH 3/3] escc: fix STATUS_SYNC bit in R_STATUS register

On Sun, 29 Aug 2021 at 11:04, Mark Cave-Ayland wrote: > > After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should > remain > high until the flag byte has been detected. Whilst the ESCC device doesn't yet > implement SDLC mode, without this change the active low STATUS_SYNC is

Re: [PATCH 2/3] escc: fix R_STATUS channel reset value

On Sun, 29 Aug 2021 at 11:07, Mark Cave-Ayland wrote: > > According to the "Z80X30 Register Reset Values" table in the ESCC datasheet > bits 2 and 6 are set whilst bits 0 and 1 are cleared during channel reset. > All other bits should be left unaltered. > > Signed-off-by: Mark Cave-Ayland > --- >

Re: [PATCH 0/3] escc: fix R_STATUS when SDLC mode is enabled

On Sun, 29 Aug 2021 at 11:05, Mark Cave-Ayland wrote: > > Here is another small set of ESCC fixes from my attempts to boot MacOS on the > q800 > machine. > > When MacOS loads the OpenTransport extension on boot it attempts to enable > SDLC mode on the ESCC. QEMU's emulation doesn't support SDLC m

Re: [PATCH] Report any problems with loading the VGA driver for PPC Macintosh targets

> On Aug 29, 2021, at 8:17 AM, Peter Maydell wrote: > > On Sun, 29 Aug 2021 at 11:18, Mark Cave-Ayland > wrote: >> What I don't understand is that the binary is installed by default in QEMU's >> sharedir >> so everything works out of the box with "make install". Do you have some >> kind of

[Bug 1701798] Re: dynamically linked binaries crash for big-endian targets

My last comment ("The issue seems to be fixed, even without the symlink for /usr/-linux-gnu/etc/ld.so.cache.") was incorrect. When this symlink is set, the program accesses /etc/ld.so.cache after accessing /usr/-linux-gnu/etc/ld.so.cache. In some cases, it works, in some cases it doesn't — dependin

applied? Re: [PATCH v1 0/2] Update NVMM support to recent changes, [PATCH v1 1/2] Only check CONFIG_NVMM when NEED_CPU_H is defined, [PATCH v1 2/2] Fix nvmm_ram_block_added() function arguments

Hi :) Have these patches been applied? How can I easily check it without manually checking if they are there in a git pullup? Am I notified normally when patches are applied? With regards, Reinoud On Sun, Jul 18, 2021 at 03:46:48PM +0200, Reinoud Zandijk wrote: > This patchset fixes small NVMM a

Re: applied? Re: [PATCH v1 0/2] Update NVMM support to recent changes, [PATCH v1 1/2] Only check CONFIG_NVMM when NEED_CPU_H is defined, [PATCH v1 2/2] Fix nvmm_ram_block_added() function arguments

On Sun, 29 Aug 2021 at 17:06, Reinoud Zandijk wrote: > > Hi :) > > Have these patches been applied? How can I easily check it without manually > checking if they are there in a git pullup? Am I notified normally when > patches are applied? Generally when a submaintainer picks up a patchset they'l

[Bug 1819289] Re: Windows 95 and Windows 98 will not install or run

Since there is some unclear information in here (which version is working? which is not?), could you please open a new ticket on gitlab instead, with a proper description what is not working with which version? -- You received this bug notification because you are a member of qemu- devel-ml, whic

[PATCH 1/3] configure: Add the possibility to read options from meson_options.txt

To avoid double maintenance between the configure script and meson_options.txt, add some simple logic in the configure script to read the options from meson_options.txt. Signed-off-by: Thomas Huth --- configure | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff

[PATCH 0/3] Use meson_options.txt in the configure script

It's cumbersome to maintain the build options twice, one time in the configure script and one time in meson_options.txt. Thus let's add some logic to the configure script to look at the meson_options.txt file instead of handling every option twice. Thomas Huth (3): configure: Add the possibility

[PATCH 2/3] configure: Remove options that can be handled via meson_options.txt instead

These trivial options can now be handled via the new generic code that parses meson_options.txt Signed-off-by: Thomas Huth --- configure | 316 +- meson_options.txt | 2 +- 2 files changed, 5 insertions(+), 313 deletions(-) diff --git a/conf

[PATCH 3/3] configure: Get help text from meson_options.txt

It's cumbersome to maintain the option help texts twice, once in the "configure" script and once in meson_options.txt. So let's add some logic to the configure script to read most of the help texts from meson_options.txt. Signed-off-by: Thomas Huth --- configure | 89

[PATCH v10 1/7] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..451a1637a1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@

[PATCH v10 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7330ff5a19..140178d23c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h

[PATCH v10 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ targ

[PATCH v10 0/7] RISC-V Pointer Masking implementation

v10: Hi folks, For this iteration I fixes some minor things Alistair mentioned in review and splitted one of patches into two: one with preliminary CSR numbers(unfortunately there're still no final ones) and another with actual CSR implementation. As for not raising the exception on writing int

[PATCH v10 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 6 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 276 + 3 files changed, 293 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..4178eecbec 100644 --- a/targ

[PATCH v10 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 target/riscv/translate.c | 36 ++-- 2 files changed, 54 insertions(+), 2 deletions(

[PATCH v10 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4178eecbec..ab8c81cb5e 100644 --- a/target/riscv/cpu.c ++

[PATCH v10 7/7] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab8c81cb5e..fde96c21f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,7 @@ static void ri

Re: [PATCH 5/5] qmp: Added qemu-ebpf-rss-path command.

On Tue, Aug 24, 2021 at 9:41 AM Markus Armbruster wrote: > > Andrew Melnichenko writes: > > > Hi, > > > >> The helper may or may not be installed at the path compiled into QEMU. > >> > > Yes, so the helper will not be called - QEMU will try to initiate eBPF RSS > > or use "in-qemu" RSS. > > My po

[PATCH v0] kvm: unsigned datatype in ioctl wrapper

From: johannst Ping. https://patchew.org/QEMU/20210805193950.514357-1-johannes.sto...@gmail.com/ https://lore.kernel.org/qemu-devel/20210805193950.514357-1-johannes.sto...@gmail.com/ Thanks and best, Johannes

Re: [PATCH v0] kvm: unsigned datatype in ioctl wrapper

On Thu, 5 Aug 2021 at 21:34, johannst wrote: > > Dear all, > > in my opinion the `type` argument in the kvm ioctl wrappers should be of > type unsigned. Please correct me if I am wrong. (Ccing Eric as our resident POSIX expert.) > Due to the same reason as explained in the comment on the > `irq_

Re: [PATCH 0/3] Use meson_options.txt in the configure script

Hi Thomas On Sun, Aug 29, 2021 at 9:32 PM Thomas Huth wrote: > It's cumbersome to maintain the build options twice, one time in the > configure script and one time in meson_options.txt. Thus let's add some > logic to the configure script to look at the meson_options.txt file > instead of handlin

Re: Testing a microcontroller emulation by loading the binary on incomplete Flash emulation

> Just create a minimal machine with some RAM in it, and use > the generic-loader to load the test binary into the RAM, then. > > -- PMM I should be using the -bios switch for loading the bare metal firmware, correct? -Gautam.

Re: Testing a microcontroller emulation by loading the binary on incomplete Flash emulation

Le dim. 29 août 2021 23:34, Gautam Bhat a écrit : > > Just create a minimal machine with some RAM in it, and use > > the generic-loader to load the test binary into the RAM, then. > > > > -- PMM > > I should be using the -bios switch for loading the bare metal firmware, > correct? > No: -device

Re: [PATCH v12 0/6] support dirtyrate at the granualrity of vcpu

ping - hi, what would you think about this patchset ? :) 在 2021/6/30 0:01, huang...@chinatelecom.cn 写道: From: Hyman Huang(黄勇) v12 - adjust the order of calculating dirty rate let memory_global_dirty_log_sync before calculating as v11 version description. v11 - rebase on master - call m

RE: [PATCH v2 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap

> FYI, Andrew's patches are now upstream so you'll be able to base your next > revision of your patches directly on upstream master when you're ready to > send it > out. Thanks for the comment. The reason I applied it locally was because I wanted to check the fixes before the Andrew’s patches was

Re: [PATCH v3 01/19] target/loongarch: Add README

Hi, Peter. On 08/27/2021 11:06 PM, Peter Xu wrote: > On Fri, Aug 27, 2021 at 03:14:36PM +0800, Song Gao wrote: >> +The following versions of the LoongArch core are supported >> +core: 3A5000 >> + >> https://github.com/loongson/LoongArch-Documentation/releases/download/LoongArch-Vol1-v3/Loo

Re: [PATCH] nvdimm: release the correct device list

ping On 03/08/2021 12:00, Li, Zhijian wrote: > ping > > Any body could help to review/queue this patch ? > > > > On 2021/6/29 22:05, Igor Mammedov wrote: >> On Thu, 24 Jun 2021 19:04:15 +0800 >> Li Zhijian wrote: >> >>> Signed-off-by: Li Zhijian >> Reviewed-by: Igor Mammedov >> >>> --- >>>   h

Re: [PATCH RFC v2 04/16] vfio-user: connect vfio proxy to remote server

> On Aug 24, 2021, at 7:15 AM, Stefan Hajnoczi wrote: > > On Mon, Aug 16, 2021 at 09:42:37AM -0700, Elena Ufimtseva wrote: >> @@ -3361,13 +3362,35 @@ static void vfio_user_pci_realize(PCIDevice *pdev, >> Error **errp) >> VFIOUserPCIDevice *udev = VFIO_USER_PCI(pdev); >> VFIOPCIDevice *

Re: [PATCH RFC v2 05/16] vfio-user: define VFIO Proxy and communication functions

> On Aug 24, 2021, at 8:14 AM, Stefan Hajnoczi wrote: > > On Mon, Aug 16, 2021 at 09:42:38AM -0700, Elena Ufimtseva wrote: >> @@ -62,5 +65,10 @@ typedef struct VFIOProxy { >> >> VFIOProxy *vfio_user_connect_dev(SocketAddress *addr, Error **errp); >> void vfio_user_disconnect(VFIOProxy *proxy);

Re: [PATCH RFC v2 06/16] vfio-user: negotiate version with remote server

> On Aug 24, 2021, at 8:59 AM, Stefan Hajnoczi wrote: > > On Mon, Aug 16, 2021 at 09:42:39AM -0700, Elena Ufimtseva wrote: >> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c >> index 7005d9f891..eae33e746f 100644 >> --- a/hw/vfio/pci.c >> +++ b/hw/vfio/pci.c >> @@ -3397,6 +3397,12 @@ static void vfi

Re: [PATCH RFC v2 07/16] vfio-user: get device info

> On Aug 24, 2021, at 9:04 AM, Stefan Hajnoczi wrote: > > On Mon, Aug 16, 2021 at 09:42:40AM -0700, Elena Ufimtseva wrote: >> +int vfio_user_get_info(VFIODevice *vbasedev) >> +{ >> +VFIOUserDeviceInfo msg; >> + >> +memset(&msg, 0, sizeof(msg)); >> +vfio_user_request_msg(&msg.hdr, VF

Re: [PATCH v6 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

On Thu, Aug 26, 2021 at 3:01 AM Philipp Tomsich wrote: > > The bitmanipulation ISA extensions will be ratified as individual > small extension packages instead of a large B-extension. The first > new instructions through the door (these have completed public review) > are Zb[abcs]. > > This adds

Re: [PATCH v6 02/14] target/riscv: Reassign instructions to the Zba-extension

On Thu, Aug 26, 2021 at 3:07 AM Philipp Tomsich wrote: > > The following instructions are part of Zba: > - add.uw (RV64 only) > - sh[123]add (RV32 and RV64) > - sh[123]add.uw (RV64-only) > - slli.uw (RV64-only) > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson Reviewed-by:

Re: [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits

On Thu, Aug 26, 2021 at 3:09 AM Philipp Tomsich wrote: > > For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding > space currently reserves a wider shamt-field (for use is a future RV128 > ISA), setting the additional bit to 1 will not map to slli.uw for RV64 > and needs to be tr

Re: [PATCH v6 04/14] target/riscv: Remove the W-form instructions from Zbs

On Thu, Aug 26, 2021 at 3:05 AM Philipp Tomsich wrote: > > Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form > instructions for Zbs (single-bit instructions). Remove them. > > Note that these instructions had already been removed for the 0.93 > version of the draft-B extensti

RE: [PATCH v2 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap

Thanks for the comments. We're sorry for the time it took you due to our lack of understanding. > As I've stated a few different times, the sve-max-vq property is of marginal > use, as > it only works for CPU models that support all vector lengths, including > non-power-of-2 lengths. This is bec

Re: [PATCH v6 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)

On Thu, Aug 26, 2021 at 3:13 AM Philipp Tomsich wrote: > > The Zb[abcs] ratification package does not include the proposed > shift-one instructions. There currently is no clear plan to whether > these (or variants of them) will be ratified as Zbo (or a different > extension) or what the timeframe

Re: [PATCH v6 06/14] target/riscv: Reassign instructions to the Zbs-extension

On Thu, Aug 26, 2021 at 3:05 AM Philipp Tomsich wrote: > > The following instructions are part of Zbs: > - b{set,clr,ext,inv} > - b{set,clr,ext,inv}i > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > > (no changes since v3) >

Re: [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc

On Tue, Aug 24, 2021 at 6:07 AM Richard Henderson wrote: > > Exit early if check_access fails. > Split out do_hlv, do_hsv, do_hlvx subroutines. > Use dest_gpr, get_gpr in the new subroutines. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson Reviewed-by: Alistair Franci

Re: [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV

On Tue, Aug 24, 2021 at 6:13 AM Richard Henderson wrote: > > Remove gen_get_gpr, as the function becomes unused. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c| 13 ++--- > target/riscv/insn_trans/trans_rvv.c.inc |

Re: [PATCH 0/3] Use meson_options.txt in the configure script

On 29/08/2021 23.22, Marc-André Lureau wrote: Hi Thomas On Sun, Aug 29, 2021 at 9:32 PM Thomas Huth > wrote: It's cumbersome to maintain the build options twice, one time in the configure script and one time in meson_options.txt. Thus let's add some logic t

Re: [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension

On Thu, Aug 26, 2021 at 3:08 AM Philipp Tomsich wrote: > > The following instructions are part of Zbc: > - clmul > - clmulh > - clmulr > > Note that these instructions were already defined in the pre-0.93 and > the 0.93 draft-B proposals, but had not been omitted in the earlier > addition of dr

Re: [PATCH v6 08/14] target/riscv: Reassign instructions to the Zbb-extension

On Thu, Aug 26, 2021 at 3:11 AM Philipp Tomsich wrote: > > This reassigns the instructions that are part of Zbb into it, with the > notable exceptions of the instructions (rev8, zext.w and orc.b) that > changed due to gorci, grevi and pack not being part of Zb[abcs]. > > Signed-off-by: Philipp Tom

Re: [PATCH v6 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci

On Thu, Aug 26, 2021 at 3:18 AM Philipp Tomsich wrote: > > The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a > orc.b instruction (equivalent to the orc.b pseudo-instruction built on > gorci from pre-0.93 draft-B) is available, mainly targeting > string-processing workloads. > > Thi

Re: [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro

On Thu, Aug 26, 2021 at 3:15 AM Philipp Tomsich wrote: > > With the changes to Zb[abcs], there's some encodings that are > different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, > we'll need a helper macro allowing us to select on RV32, as well. > > Signed-off-by: Philipp Tomsich > Re

Re: [PATCH v6 11/14] target/riscv: Add rev8 instruction, removing grev/grevi

On Thu, Aug 26, 2021 at 3:13 AM Philipp Tomsich wrote: > > The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a > rev8 instruction (equivalent to the rev8 pseudo-instruction built on > grevi from pre-0.93 draft-B) is available. > > This commit adds the new rev8 instruction and removes

Re: [PATCH v6 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh

On Thu, Aug 26, 2021 at 3:14 AM Philipp Tomsich wrote: > > The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a > zext.h instruction is provided (built on pack/packh from pre-0.93 > draft-B) is available. > > This commit adds zext.h and removes the pack* instructions. > > Note th

Re: [PATCH v6 13/14] target/riscv: Remove RVB (replaced by Zb[abcs]

On Thu, Aug 26, 2021 at 3:16 AM Philipp Tomsich wrote: > > With everything classified as Zb[abcs] and pre-0.93 draft-B > instructions that are not part of Zb[abcs] removed, we can remove the > remaining support code for RVB. > > Note that RVB has been retired for good and misa.B will neither mean

Re: [PATCH v3 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Sun, Aug 29, 2021 at 3:01 PM Anup Patel wrote: > > The RISC-V ACLINT is more modular and backward compatible with > original SiFive CLINT so instead of duplicating the original > SiFive CLINT implementation we upgrade the current SiFive CLINT > implementation to RISC-V ACLINT implementation. >

Re: [PATCH v4] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()

On Sat, Aug 28, 2021 at 1:28 AM David Hoppenbrouwers wrote: > > `muldiv64` would overflow in cases where the final 96-bit value does not > fit in a `uint64_t`. This would result in small values that cause an > interrupt to be triggered much sooner than intended. > > The overflow can be detected in

Re: [PATCH 5/5] qmp: Added qemu-ebpf-rss-path command.

Yuri Benditovich writes: > On Tue, Aug 24, 2021 at 9:41 AM Markus Armbruster wrote: >> >> Andrew Melnichenko writes: >> >> > Hi, >> > >> >> The helper may or may not be installed at the path compiled into QEMU. >> >> >> > Yes, so the helper will not be called - QEMU will try to initiate eBPF RS

[PATCH 00/48] tcg: optimize redundant sign extensions

Currently, we have support for optimizing redundant zero extensions, which I think was done with x86 and aarch64 in mind, which zero-extend all 32-bit operations into the 64-bit register. But targets like Alpha, MIPS, and RISC-V do sign-extensions instead. The last 5 patches address this. But bef

[PATCH 01/48] tcg/optimize: Rename "mask" to "z_mask"

Prepare for tracking different masks by renaming this one. Signed-off-by: Richard Henderson --- tcg/optimize.c | 142 + 1 file changed, 72 insertions(+), 70 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9876ac52a8..254f0b1b71 100

[PATCH 04/48] tcg/optimize: Change tcg_opt_gen_{mov,movi} interface

Adjust the interface to take the OptContext parameter instead of TCGContext or both. Signed-off-by: Richard Henderson --- tcg/optimize.c | 67 +- 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index

[PATCH 12/48] tcg/optimize: Split out finish_folding

Copy z_mask into OptContext, for writeback to the first output within the new function. Signed-off-by: Richard Henderson --- tcg/optimize.c | 49 + 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c inde

[PATCH 02/48] tcg/optimize: Split out OptContext

Provide what will become a larger context for splitting the very large tcg_optimize function. Signed-off-by: Richard Henderson --- tcg/optimize.c | 77 ++ 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize

[PATCH 15/48] tcg/optimize: Split out fold_const{1,2}

Split out a whole bunch of placeholder functions, which are currently identical. That won't last as more code gets moved. Use CASE_32_64_VEC for some logical operators that previously missed the addition of vectors. Signed-off-by: Richard Henderson --- tcg/optimize.c | 254

[PATCH 05/48] tcg/optimize: Move prev_mb into OptContext

This will expose the variable to subroutines that will be broken out of tcg_optimize. Signed-off-by: Richard Henderson --- tcg/optimize.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c73ec384f3..87f33521ad 100644 --- a/tcg/

[PATCH 08/48] tcg/optimize: Split out fold_call

Calls are special in that they have a variable number of arguments, and need to be able to clobber globals. Signed-off-by: Richard Henderson --- tcg/optimize.c | 63 -- 1 file changed, 41 insertions(+), 22 deletions(-) diff --git a/tcg/optimize.c

[PATCH 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov,movi}

This will allow callers to tail call to these functions and return true indicating processing complete. Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 39a65d305f..c4559d32be 10

[PATCH 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals

Rather than try to keep these up-to-date across folding, re-read nb_oargs at the end, after re-reading the opcode. A couple of asserts need dropping, but that will take care of itself as we split the function further. Signed-off-by: Richard Henderson --- tcg/optimize.c | 14 -- 1 fi

[PATCH 03/48] tcg/optimize: Remove do_default label

Break the final cleanup clause out of the main switch statement. When fully folding an opcode to mov/movi, use "continue" to process the next opcode, else break to fall into the final cleanup. Signed-off-by: Richard Henderson --- tcg/optimize.c | 190

[PATCH 29/48] tcg/optimize: Split out fold_mov

This is the final entry in the main switch that was in a different form. After this, we have the option to convert the switch into a function dispatch table. Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-)

[PATCH 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}

This puts the separate mb optimization into the same framework as the others. While fold_qemu_{ld,st} are currently identical, that won't last as more code gets moved. Signed-off-by: Richard Henderson --- tcg/optimize.c | 89 +- 1 file changed, 51

[PATCH 06/48] tcg/optimize: Split out init_arguments

There was no real reason for calls to have separate code here. Unify init for calls vs non-calls using the call path, which handles TCG_CALL_DUMMY_ARG. Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++-- 1 file changed, 11 insertions(+), 14 deletions(-) diff --gi

[PATCH 30/48] tcg/optimize: Split out fold_xx_to_i

Pull the "op r, a, a => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Signed-off-by: Richard Henderson --- tcg/optimize.c | 41 - 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/tcg/optimize.c b/tcg

[PATCH 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*

Return -1 instead of 2 for failure. This us to use comparisons against 0 for all cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 + 1 file changed, 74 insertions(+), 71 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c ind

[PATCH 07/48] tcg/optimize: Split out copy_propagate

Continue splitting tcg_optimize. Signed-off-by: Richard Henderson --- tcg/optimize.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index b1b5096a9d..a668c5f0df 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -611,6

[PATCH 16/48] tcg/optimize: Split out fold_setcond2

Reduce some code duplication by folding the NE and EQ cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 - 1 file changed, 72 insertions(+), 73 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 05de083d50..7de76b6de9 1

[PATCH 18/48] tcg/optimize: Split out fold_brcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 0ddeaf7e4f..9dfd172a34 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -714,6 +714,22 @@ static boo

[PATCH 34/48] tcg/optimize: Split out fold_to_not

Split out the conditional conversion from a more complex logical operation to a simple NOT. Create a couple more helpers to make this easy for the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 154 +++-- 1 file c

[PATCH 13/48] tcg/optimize: Use a boolean to avoid a mass of continues

Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d202515369..76f9772648 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -713,6 +713,7 @@ void tcg_optimize(TCGContext *s)

[PATCH 22/48] tcg/optimize: Split out fold_movcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 56 -- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index b72fe6e847..d9592a039c 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -919,6 +919

[PATCH 19/48] tcg/optimize: Split out fold_setcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9dfd172a34..58f03737d2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -935,6 +935,17 @@ static bool fold_qemu

[PATCH 36/48] tcg/optimize: Split out fold_xi_to_x

Pull the "op r, a, i => mov r, a" optimization into a function, and use them int the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 +- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/tcg/opt

[PATCH 26/48] tcg/optimize: Split out fold_count_zeros

Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++-- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 74c307951d..79e46fec23 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -875,6 +875,20 @@ static bool

[PATCH 17/48] tcg/optimize: Split out fold_brcond2

Reduce some code duplication by folding the NE and EQ cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 161 + 1 file changed, 83 insertions(+), 78 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 7de76b6de9..0ddeaf7e4f 1

[PATCH 20/48] tcg/optimize: Split out fold_mulu2_i32

Signed-off-by: Richard Henderson --- tcg/optimize.c | 37 + 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 58f03737d2..dbe283cedb 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -891,6 +891,24 @@ static

Re: QEMU-KVM offers OPAL firmware interface? OpenBSD guest support?

On 8/29/21 6:20 AM, Joseph wrote: >> runs Linux powernv bare metal on Power9 hardware. Each VM is a >> KVM-QEMU instance. > If you want to also run OpenBSD inside a VM, then OpenBSD must implement proper support to be able to run in the paravirtualized PAPR environment provided by K

[PATCH 21/48] tcg/optimize: Split out fold_addsub2_i32

Add two additional helpers, fold_add2_i32 and fold_sub2_i32 which will not be simple wrappers forever. Signed-off-by: Richard Henderson --- tcg/optimize.c | 70 +++--- 1 file changed, 44 insertions(+), 26 deletions(-) diff --git a/tcg/optimize.c b/tcg

[PATCH 27/48] tcg/optimize: Split out fold_bswap

Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 79e46fec23..1366bbaa17 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -843,6 +843,17 @@ static bool fold

[PATCH 24/48] tcg/optimize: Split out fold_extract, fold_sextract

Signed-off-by: Richard Henderson --- tcg/optimize.c | 48 ++-- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 866b77dad8..c3c66a949e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -885,6 +885,1

[PATCH 45/48] tcg/optimize: Propagate sign info for logical operations

Sign repetitions are perforce all identical, whether they are 1 or 0. Bitwise operations preserve the relative quantity of the repetitions. Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 + 1 file changed, 29 insertions(+) diff --git a/tcg/optimize.c b/tcg/

[PATCH 23/48] tcg/optimize: Split out fold_extract2

Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 ++- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d9592a039c..866b77dad8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -885,6 +885,25 @@ stat

[PATCH 33/48] tcg/optimize: Add type to OptContext

Compute the type of the operation early. There are at least 4 places that used a def->flags ladder to determine the type of the operation being optimized. There were two places that assumed !TCG_OPF_64BIT means TCG_TYPE_I32, and so could potentially compute incorrect results for vector operations

[PATCH 32/48] tcg/optimize: Split out fold_xi_to_i

Pull the "op r, a, 0 => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 +++- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize

[PATCH 44/48] tcg/optimize: Optimize sign extensions

Certain targets, like riscv, produce signed 32-bit results. This can lead to lots of redundant extensions as values are manipulated. Begin by tracking only the obvious sign-extensions, and converting them to simple copies when possible. Signed-off-by: Richard Henderson --- tcg/optimize.c | 129

[PATCH 25/48] tcg/optimize: Split out fold_deposit

Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c3c66a949e..74c307951d 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -880,6 +880,18 @@ static bool fold_c

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