Signed-off-by: Alexey Baturo <space.monkey.deliv...@gmail.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab8c81cb5e..fde96c21f2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
/* mmte is supposed to have pm.current hardwired to 1 */
env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
#endif
+ target_misa |= RVJ;
}
set_misa(env, target_misa);
@@ -618,6 +619,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
--
2.20.1
