On Thu, Aug 26, 2021 at 3:01 AM Philipp Tomsich
<philipp.toms...@vrull.eu> wrote:
>
> The bitmanipulation ISA extensions will be ratified as individual
> small extension packages instead of a large B-extension. The first
> new instructions through the door (these have completed public review)
> are Zb[abcs].
>
> This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
> these in target/riscv/cpu.[ch].
>
> Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Split off removal of 'x-b' property and 'ext_b' field into a separate
> patch to ensure bisectability.
>
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..c7bc1f9f44 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -585,6 +585,10 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> /* This is experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
> + DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
> + DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
> + DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
> + DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf1c899c00..7c4cd8ea89 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -293,6 +293,10 @@ struct RISCVCPU {
> bool ext_u;
> bool ext_h;
> bool ext_v;
> + bool ext_zba;
> + bool ext_zbb;
> + bool ext_zbc;
> + bool ext_zbs;
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> --
> 2.25.1
>
>
