From: Jan Luebbe
Break events are currently only handled by chardev/char-serial.c, so we
just ignore errors, which results in no behaviour change for other
chardevs.
Signed-off-by: Jan Luebbe
Message-id: 20210806144700.3751979-1-...@pengutronix.de
Reviewed-by: Peter Maydell
Signed-off-by: Pete
Implement the MVE VMLAS insn, which multiplies a vector by a vector
and adds a scalar.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 4
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 26 ++
target/ar
All the users of the vmlaldav formats have an 'x bit in bit 12 and an
'a' bit in bit 5; move these to the format rather than specifying them
in each insn pattern.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/mve.decode | 16
1 file changed, 8 inser
Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN.
These take a double-width input, narrow it (possibly saturating) and
store the result to either the top or bottom half of the output
element.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h
From: Guenter Roeck
Instantiate SAI1/2/3 as unimplemented devices to avoid Linux kernel crashes
such as the following.
Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b
pgd = (ptrval)
[d19b] *pgd=82711811, *pte=308a0653, *ppte=308a0453
Internal error: : 808 [#1] SMP ARM
On 25/08/2021 11:29, Philippe Mathieu-Daudé wrote:
On 8/25/21 11:51 AM, Mark Cave-Ayland wrote:
Commit 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property")
changed
the sun4m CPU reset code to use the start-powered-off property and so split the
creation of the CPU into separate i
Implement the MVE integer min/max across vector insns
VMAXV, VMINV, VMAXAV and VMINAV, which find the maximum
from the vector elements and a general purpose register,
and store the maximum back into the general purpose
register.
These insns overlap with VRMLALDAVH (they use what would
be RdaHi=0b1
The MVEGenDualAccOpFn is a bit misnamed, since it is used for
the "long dual accumulate" operations that use a 64-bit
accumulator. Rename it to MVEGenLongDualAccOpFn so we can
use the former name for the 32-bit accumulator insns.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
t
On Wed, Aug 25, 2021 at 12:29 PM Philippe Mathieu-Daudé wrote:
>
> Fixes: 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState
> property")
> Signed-off-by: Mark Cave-Ayland
> Signed-off-by: Philippe Mathieu-Daudé
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index f
Hi
On Wed, Aug 25, 2021 at 1:38 PM Stefan Reiter wrote:
> Commit cfb5387a1d 'hmp: remove "change vnc TARGET" command' claims to
> remove the HMP "change vnc" command, but doesn't actually do that.
> Instead if rewires it to use 'qmp_change_vnc_password', and in the
> process inverts the argument
Implement the MVE VMLADAV and VMLSLDAV insns. Like the VMLALDAV and
VMLSLDAV insns already implemented, these accumulate multiplied
vector elements; but they accumulate a 32-bit result rather than a
64-bit one.
Note that these encodings overlap with what would be RdaHi=0b111 for
VMLALDAV, VMLSLDA
Implement the MVE VMAXA and VMINA insns, which take the absolute
value of the signed elements in the input vector and then accumulate
the unsigned max or min into the destination vector.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 8
ta
Implement the MVE VMLA insn, which multiplies a vector by a scalar
and accumulates into another vector.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 4
target/arm/mve.decode | 1 +
target/arm/mve_helper.c| 5 +
target/arm/transla
Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so
as to predicate any element at index Rn or greater is predicated. As
with VPNOT, this insn itself is predicable and subject to beatwise
execution.
The calculation of the mask is the same as is used to determine
ltpmask in mve_el
On 8/16/21 2:10 AM, Philippe Mathieu-Daudé wrote:
> We already call check_cp1_enabled() earlier in the "pre-conditions"
> checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue.
> Remove the duplicated calls.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/tcg/translate.c
Implement the MVE 1-operand saturating operations VQABS and VQNEG.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 8
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 37 +
target/arm/tra
Implement the MVE VLDR/VSTR insns which do scatter-gather using base
addresses from Qm plus or minus an immediate offset (possibly with
writeback). Note that writeback is not predicated but it does have
to honour ECI state, so we have to add an eci_mask check to the
VSTR_SG macros (the VLDR_SG macr
Unlike A-profile, for M-profile the UDIV and SDIV insns can be
configured to raise an exception on division by zero, using the CCR
DIV_0_TRP bit.
Implement support for setting this bit by making the helper functions
raise the appropriate exception.
Signed-off-by: Peter Maydell
Reviewed-by: Richa
Implement the MVE interleaving load/store functions VLD2, VLD4, VST2
and VST4. VLD2 loads 16 bytes of data from memory and writes to 2
consecutive Qregs; VLD4 loads 16 bytes of data from memory and writes
to 4 consecutive Qregs. The 'pattern' field in the encoding
determines the offset into memor
Hi
On Wed, Aug 25, 2021 at 1:39 PM Stefan Reiter wrote:
> It is possible to specify more than one VNC server on the command line,
> either with an explicit ID or the auto-generated ones à la "default",
> "vnc2", "vnc3", ...
>
> It is not possible to change the password on one of these extra VNC
From: Eduardo Habkost
The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type
checking helper, preventing us from using a OBJECT_DEFINE* or
DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper.
If I understand the SBSA 6.0 specification correctly, the signal
being connected to IRQ
From: Guenter Roeck
Instantiate SAI1/2/3 and ASRC as unimplemented devices to avoid random
Linux kernel crashes, such as
Unhandled fault: external abort on non-linefetch (0x808) at 0xd1580010
pgd = (ptrval)
[d1580010] *pgd=8231b811, *pte=02034653, *ppte=02034453
Internal error: : 808 [#1] SMP AR
From: Yanan Wang
Commit 29e0447551
(docs/about/removed-features: Document removed CLI options from QEMU v3.1)
has recorded some CLI options as replaced/removed from QEMU v3.1, but one
of the subjects has missed the release record. Let's fix it.
Reported-by: Cornelia Huck
Signed-off-by: Yanan Wa
From: Sebastian Meyer
With gdb 9.0 and better it is possible to connect to a gdbstub
over unix sockets, which is better than a TCP socket connection
in some situations. The QEMU command line to set this up is
non-obvious; document it.
Signed-off-by: Sebastian Meyer
Message-id: 162867284829.2737
(meta note: patch does not apply anymore and needs to be refreshed)
On 12/08/2021 20.04, Daniel P. Berrangé wrote:
[...]
diff --git a/.gitlab-ci.d/rules.yml b/.gitlab-ci.d/rules.yml
new file mode 100644
index 00..3399722ca9
--- /dev/null
+++ b/.gitlab-ci.d/rules.yml
@@ -0,0 +1,116 @@
+
Some of the removed CLI options have been added to the wrong section
in the "Removed features" chapter - they've been put into the
"Related binaries" section instead. Move them now into the correct
"System emulator command line arguments" section.
Message-Id: <20210818112908.102205-1-th...@redhat.
+Leon3 maintainers
On Wed, Aug 25, 2021 at 12:39 PM Mark Cave-Ayland
wrote:
> On 25/08/2021 11:29, Philippe Mathieu-Daudé wrote:
> > On 8/25/21 11:51 AM, Mark Cave-Ayland wrote:
> >> Commit 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property")
> >> changed
> >> the sun4m CPU reset
From: "Wen, Jianxian"
Add property memory region which can connect with IOMMU region to support SMMU
translate.
Signed-off-by: Jianxian Wen
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 4c23c17b8e87e74e906a25a3254a03f4fa1fe...@shasxm03.verisilicon.com
Signed-off-by: Peter Maydell
---
hw/a
Hi Peter!
The following changes since commit f9baca549e44791be0dd98de15add3d8452a8af0:
Update version for v6.1.0 release (2021-08-24 17:59:52 +0100)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2021-08-25
for you to fetch changes up to 2e8801
On 8/13/21 1:01 PM, Philippe Mathieu-Daudé wrote:
> Raise Loongson-3A1000 SEGBITS from 40 to 48.
>
> Philippe Mathieu-Daudé (2):
> target/mips: Document Loongson-3A CPU definitions
> target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
Thanks, applied to mips-next.
From: Yanan Wang
There is a mixture of "since/removed in X.Y" vs "since/removed in X.Y.Z"
in the subjects in deprecated.rst/removed-features.rst. It will be better
to use an unified format. It seems unlikely that we will ever deprecate
something in a stable release, and even more unlikely that we
From: Daniel P. Berrangé
The sphinx-build is fairly verbose spitting out pages of output to the
console, which causes errors from other build commands to be scrolled
off the top of the terminal. This can leave the mistaken impression that
the build passed, when in fact there was a failure.
Signe
From: Yanan Wang
There are two places describing the same thing about deprecation
of invalid topologies of -smp CLI, so remove the duplicated one.
Signed-off-by: Yanan Wang
Reviewed-by: Cornelia Huck
Reviewed-by: Andrew Jones
Reviewed-by: Thomas Huth
Message-Id: <20210823030005.165668-2-wang
> On Aug 25, 2021, at 1:24 AM, Chen Zhang wrote:
>
>> On Tue, Aug 24, 2021 at 05:46:43PM -0400, Programmingkid wrote:
>>> Hi, I recently tried using the edid feature in QEMU for my Mac OS 10.8
>>> guest
>>> like this: -device VGA,edid=on,xres=1280,yres=800. When the guest operating
>>> syst
From: Daniel P. Berrangé
This splits the CI docs into one file talking about job setup and usage
and another file describing provisioning of custom runners.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Willian Rampazzo
Message-Id: <20210812180403.4129067-
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> nvme_create_queue_pair() does not return a boolean value (indicating
> eventual error) but a pointer, and is inconsistent in how it fills the
> error handler. To fulfill callers expectations, always set an error
> message on failure.
>
> Reported-by
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> Fix when building with -Wshorten-64-to-32:
>
> warning: implicit conversion loses integer precision: 'unsigned long' to
> 'int' [-Wshorten-64-to-32]
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Klaus Jensen
signature.asc
Descripti
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> Now that all qemu_vfio_dma_map() callers provide an Error* argument,
> fill it with relevant / more descriptive message. Reduce 'ret'
> (returned value) scope by returning errno directly to simplify
> (removing the goto / 'out' label).
>
> Signed-of
On 8/25/21 12:59 PM, Marc-André Lureau wrote:
Hi
On Wed, Aug 25, 2021 at 1:39 PM Stefan Reiter wrote:
It is possible to specify more than one VNC server on the command line,
either with an explicit ID or the auto-generated ones à la "default",
"vnc2", "vnc3", ...
It is not possible to change
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> qemu_vfio_add_mapping() returns a pointer to an indexed entry
> in pre-allocated QEMUVFIOState::mappings[], thus can not be NULL.
> Remove the pointless check.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> util/vfio-helpers.c | 4
> 1 fil
On Aug 25 13:53, Klaus Jensen wrote:
> On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> > qemu_vfio_add_mapping() returns a pointer to an indexed entry
> > in pre-allocated QEMUVFIOState::mappings[], thus can not be NULL.
> > Remove the pointless check.
> >
> > Signed-off-by: Philippe Mathieu-Daud
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> Simplify qemu_vfio_dma_[un]map() handlers by replacing a pair of
> qemu_mutex_lock/qemu_mutex_unlock calls by the WITH_QEMU_LOCK_GUARD
> macro.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Klaus Jensen
signature.asc
Description: PGP s
On Tue, 24 Aug 2021 21:48:29 -0300
Daniel Henrique Barboza wrote:
> qapi_event_send_mem_unplug_error() deals with @device being NULL by
> replacing it with an empty string ("") when emitting the event. Aside
> from the fact that this behavior (qapi visitor mapping NULL pointer to
> "") can be pat
On Tue, 24 Aug 2021 21:48:35 -0300
Daniel Henrique Barboza wrote:
> MEM_UNPLUG_ERROR is deprecated since the introduction of
> DEVICE_UNPLUG_GUEST_ERROR. Keep emitting both while the deprecation of
> MEM_UNPLUG_ERROR is pending.
>
> CC: Michael S. Tsirkin
> CC: Igor Mammedov
> Reviewed-by: Gre
On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
> We expect the first qemu_vfio_dma_map() to fail (indicating
> DMA mappings exhaustion, see commit 15a730e7a3a). Do not
> report the first failure as error, since we are going to
> flush the mappings and retry.
>
> This removes spurious error message
On Wed, Aug 25, 2021 at 02:30:11PM +1000, David Gibson wrote:
> On Tue, Aug 24, 2021 at 01:30:18PM -0300, Daniel Henrique Barboza wrote:
> > From: Gustavo Romero
> >
> > This patch adds handling of UMMCR0 and UMMCR2 user read which,
> > according to PowerISA 3.1, has some bits ommited to the
>
>
On 25/08/2021 11:43, Philippe Mathieu-Daudé wrote:
+Leon3 maintainers
Note that despite its presence in CPUSPARCState MXCC isn't part of the SPARC CPU but
defined as part of the sun4m architecture, so I'm not sure it even exists in LEON3
(which is likely another reason it was written the way
Markus Armbruster writes:
> Peter Xu writes:
>
>> On Mon, Aug 23, 2021 at 05:56:23PM -0400, Eduardo Habkost wrote:
>>> I don't have any other example, but I assume address assignment
>>> based on ordering is a common pattern in device code.
>>>
>>> I would take a very close and careful look at
From: Marc-André Lureau
DTC is widely available, we could consider to stop bundling it.
curl -s 'https://repology.org/api/v1/project/dtc' | \
jq -r 'group_by(.repo) | .[] | "\(.[0].repo): \(map(.version))"' | \
egrep -i
'ubuntu_18|debian_old|rhel|centos|bsd|suse_leap_15_2|sles|homebrew|p
From: David Gibson
> Hrm.. I'm a bit concerned about mkaing this a more widespread function,
> because it has a nasty edge case... which is basically unavoidable in an
> abs64()
> implementation. Specifically:
>
> abs64(0x800___0) == 0x800___ < 0
>
> At least in the mo
On 24/08/2021 21:11, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The definition of struct Int128 is currently independent of the host
endianness, causing different results when using the member s128 of
union ppc_vsr_t in big-endian builds with CONFIG_INT128 or
!CONFIG_INT128.
The
From: chunming
Add PL330 DMA controller to test SMMU v3 connection and function.
The default SID for PL330 is 1 but we test other values, it works well.
Signed-off-by: chunming
---
hw/arm/virt.c | 92 ++-
include/hw/arm/virt.h | 1 +
2 files cha
From: chunming
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: chunming
---
hw/arm/smmuv3.c | 46
> Hi, I recently tried using the edid feature in QEMU for my Mac OS 10.8 guest
> like this: -device VGA,edid=on,xres=1280,yres=800. When the guest operating
> system loaded there were no additional options available in the Display
> settings. Would you know what is wrong?
>
> Thank you.
You nee
JR opcode (Jump Register) only takes 1 argument, $rs.
JALR (Jump And Link Register) takes 3: $rs, $rd and $hint.
Commit 6af0bf9c7c3 added their processing into decode_opc() as:
case 0x08 ... 0x09: /* Jumps */
gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);
having both opcodes
From: chunming
. Add "smmuv3_sidmap" to set non PCI/PCIe devices SID value
. Pass non PCI/PCIe devices SID value to SMMU v3 model creation
. Store SMMU v3 device in virtual machine then non PCI/PCIe can get its
memory region later
Signed-off-by: chunming
---
hw/arm/virt.c | 18 +
Extract the NEC Vr54xx helper definitions to
'vendor-vr54xx_helper.h'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201120210844.2625602-15-f4...@amsat.org>
---
target/mips/helper.h| 18 +++---
target/mips/tcg/vr54xx_helper.h.in
The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:
Open 6.2 development tree (2021-08-25 10:25:12 +0100)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20210825
for you to fetch changes up to
We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210801234202.3167676-4-f4...@amsat.org>
Reviewed-by: Richard Henderson
---
target/mips/tcg/mips64r6.decode | 27 ---
.../
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
opcodes to decodetree") we misplaced the decoder call. Move
it to the correct place.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210801234202.3167676-3-f4...@amsat.org>
Reviewed-by: Richard Henderson
---
target/mips/tcg/trans
From: chunming
Replace "smmuv3_flush_config" with "g_hash_table_foreach_remove".
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
Signed-off-by: chunming
---
hw/arm/smmuv3.c | 35 ++-
include/hw/arm/smmu-common.h | 5
We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210801234202.3167676-5-f4...@amsat.org>
Reviewed-by: Richard Henderson
---
ta
gen_helper_1e2i() is unused since commit 33a07fa2db6
("target/mips: reimplement SC instruction emulation
and use cmpxchg"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-3-f4...@amsat.org>
---
target/mips/tcg/translate.c | 6
The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210801235926.3178085-3-f4...@amsat.org>
Reviewed-by: Richard Henderson
---
target/mips/tcg/translate.h| 1 +
target/mips/tcg/vr54xx.decode
From: chunming
The current SMMU v3 model only support PCI/PCIe devices, so we update it for
non-PCI/PCIe devices.
. Add independent IOMMU memory regions for non-PCI/PCIe devices
. Add SID value property setting for non-PCI/PCIe devices
. Add PL330 DMA controller into "virt" machine and con
Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Huacai Chen
Message-Id: <20210813110149.1432692-2-f4...@amsat.org>
---
target/mips/cpu-defs.c.inc | 4 ++--
1 file
$rt register is used read-only, so we can replace tcg_const_i32()
temporary by tcg_constant_i32().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-4-f4...@amsat.org>
---
target/mips/tcg/translate.c | 14 ++
1 file changed, 2 i
Convert the following Integer Multiply-Accumulate opcodes:
* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCUUnsigned multiply, accumulate, and move LO
Since all opcodes ar
check_insn() checks for any bit in the set, and INSN_R5900 is
just another bit added to the set. No need to special-case it.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210801234202.3167676-2-f4...@amsat.org>
Reviewed-by: Richard Henderson
---
target/mips/tcg/translate.c | 8 ++--
To be able to split some code calling the gen_helper() macros
out of the huge translate.c, we need to define them in the
'translate.h' local header.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-9-f4...@amsat.org>
---
target/mips/tcg/tr
Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210818164321.2474534-5-f4...@amsat.or
Convert the following Integer Multiply-Accumulate opcodes:
* MULHIMultiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU
Plain copy/paste of the TRANS() macro introduced in the PPC
commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer
loads to decodetree") to the MIPS target.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210808173018.90960-
In all call sites the last argument is always used as a
read-only value, so we can replace tcg_const_i32() temporary
by tcg_constant_i32().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-5-f4...@amsat.org>
---
target/mips/tcg/translate.c
Extract NEC Vr54xx helpers from op_helper.c to a new file:
'vr54xx_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201120210844.2625602-14-f4...@amsat.org>
---
target/mips/tcg/op_helper.c | 118 --
target/mips/tcg/vr54xx
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> dtstdc: DFP Test Data Class
> dtstdcq: DFP Test Data Class Quad
> dtstdg: DFP Test Data Group
> dtstdgq: DFP Test Data Group Quad
>
> Signed-off-by: Luis Pires
> ---
> target/ppc/dfp_helper.c |
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove one use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by: Phi
gen_helper_0e0i() is one-line long and is only used twice:
simply inline it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-7-f4...@amsat.org>
---
target/mips/tcg/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
Convert the following Integer Multiply-Accumulate opcodes:
* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply, negate, accumulate, and move HI
* MSACHIU Unsigned multiply, negate, accumulate, and move HI
* MSACUUnsigned multiply, negate, accumulate, a
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> dqua: DFP Quantize
> dquaq: DFP Quantize Quad
> drrnd: DFP Reround
> drrndq: DFP Reround Quad
>
> Signed-off-by: Luis Pires
> ---
> target/ppc/dfp_helper.c | 8 ++---
> target/ppc/helper.h
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove another use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by:
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Huacai Chen
Mes
Add the inlined cpu_is_bigendian() function in "translate.h".
Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210818164321.2474534-6-f4...@amsat.org>
---
target/mips/tcg/translate.h
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> ddedpd: DFP Decode DPD To BCD
> ddedpdq: DFP Decode DPD To BCD Quad
> denbcd: DFP Encode BCD To DPD
> denbcdq: DFP Encode BCD To DPD Quad
> dscli: DFP Shift Significand Left Immediate
> dscliq: DFP Shift S
We already call check_cp1_enabled() earlier in the "pre-conditions"
checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue.
Remove the duplicated calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Huacai Chen
Message-Id: <20210816001031.1720432-1-f4...@amsat.org>
---
target/mips
gen_helper_0e3i() is unused since commit 895c2d04359
("target-mips: switch to AREG0 free mode"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-2-f4...@amsat.org>
---
target/mips/tcg/translate.c | 6 --
1 file changed, 6 d
gen_helper_1e1i() is one-line long and is used in one place:
simply inline it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-6-f4...@amsat.org>
---
target/mips/tcg/translate.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
On 25/08/2021 13:43, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
DTC is widely available, we could consider to stop bundling it.
curl -s 'https://repology.org/api/v1/project/dtc' | \
jq -r 'group_by(.repo) | .[] | "\(.[0].repo): \(map(.version))"' | \
egrep -i
'ubuntu
On 8/25/21 2:43 PM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> DTC is widely available, we could consider to stop bundling it.
>
> curl -s 'https://repology.org/api/v1/project/dtc' | \
>jq -r 'group_by(.repo) | .[] | "\(.[0].repo): \(map(.version))"' | \
>egrep -i
excp/err are temporaries input, so we can replace tcg_const_i32()
calls by tcg_constant_i32() equivalent.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210816205107.2051495-8-f4...@amsat.org>
---
target/mips/tcg/translate.c | 7 ++-
1 file changed, 2 in
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
As a first step, inline the GET_OFFSET() macro, calling
cpu_is_bigendian() to get the 'direction' of the offset.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2021
On 8/25/21 1:34 PM, Klaus Jensen wrote:
> On Aug 24 16:11, Philippe Mathieu-Daudé wrote:
>> Now that all qemu_vfio_dma_map() callers provide an Error* argument,
>> fill it with relevant / more descriptive message. Reduce 'ret'
>> (returned value) scope by returning errno directly to simplify
>> (re
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> dadd: DFP Add
> daddq: DFP Add Quad
> dsub: DFP Subtract
> dsubq: DFP Subtract Quad
> dmul: DFP Multiply
> dmulq: DFP Multiply Quad
> ddiv: DFP Divide
> ddivq: DFP Divide Quad
> diex: DFP Insert Biased Exp
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> dquai: DFP Quantize Immediate
> dquaiq: DFP Quantize Immediate Quad
> drintx: DFP Round to FP Integer With Inexact
> drintxq: DFP Round to FP Integer With Inexact Quad
> drintn: DFP Round to FP Integer Wit
Using a custom timeout is useful to continue fuzzing complex devices,
even after we run into some slow code-path. However, simply adding a
fixed timeout to each input effectively caps the maximum input
length/number of operations at some artificial value. There are two
major problems with this:
1.
On 8/24/21 4:27 PM, Luis Pires wrote:
> Move the following instructions to decodetree:
> dctdp: DFP Convert To DFP Long
> dctqpq: DFP Convert To DFP Extended
> drsp:DFP Round To DFP Short
> drdpq: DFP Round To DFP Long
> dcffix: DFP Convert From Fixed
> dcffixq: DFP Convert From Fixed Qua
From: Qiuhao Li
To keep me cc-ed when something changes. Suggested by Alexander.
https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg03631.html
Signed-off-by: Qiuhao Li
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alexander Bulekov
Reviewed-by: Darren Kenny
---
MAINTAINERS | 1 +
We have some configs for devices such as the AC97 and ES1370 that were
not matching memory-regions correctly, because the configs provided
lowercase names. To resolve these problems and prevent them from
occurring again in the future, convert both the pattern and names to
lower-case, prior to check
By default, -fsanitize=fuzzer instruments all code with coverage
information. However, this means that libfuzzer will track coverage over
hundreds of source files that are unrelated to virtual-devices. This
means that libfuzzer will optimize inputs for coverage observed in timer
code, memory APIs e
Using ITIMER_VIRTUAL is a bad idea, if the fuzzer hits a blocking
syscall - e.g. ppoll with a NULL timespec. This causes timeout issues
while fuzzing some block-device code. Fix that by using wall-clock time.
This might cause inputs to timeout sometimes due to scheduling
effects/ambient load, but i
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