Re: [PATCH] target/arm: Take an exception if PSTATE.IL is set

On 8/17/21 6:21 AM, Peter Maydell wrote: In v8A, the PSTATE.IL bit is set for various kinds of illegal exception return or mode-change attempts. We already set PSTATE.IL (or its AArch32 equivalent CPSR.IL) in all those cases, but we weren't implementing the part of the behaviour where attempting

Re: [PATCH] target/arm: Do hflags rebuild in cpsr_write()

On 8/17/21 10:26 AM, Peter Maydell wrote: On Tue, 17 Aug 2021 at 21:18, Peter Maydell wrote: Currently we rely on all the callsites of cpsr_write() to rebuild the cached hflags if they change one of the CPSR bits which we use as a TB flag and cache in hflags. This is a bit awkward when we wan

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On 8/17/21 12:32 PM, Paolo Bonzini wrote: On 17/08/21 01:53, Steve Rutherford wrote: Separately, I'm a little weary of leaving the migration helper mapped into the shared address space as writable. A related question here is what the API should be for how the migration helper sees the memor

[PATCH v2 00/21] target/riscv: Use tcg_constant_*

Replace use of tcg_const_*, which makes a copy into a temp which must be freed, with direct use of the constant. Reorg handling of $zero, with different accessors for source and destination. Reorg handling of csrs, passing the actual write_mask instead of a regno. Use more helpers for RVH expans

[PATCH v2 01/21] target/riscv: Use tcg_constant_*

Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c| 36 -- target/riscv/insn_trans/trans_rvf.c.inc | 3 +- target/ris

[PATCH v2 02/21] target/riscv: Clean up division helpers

Utilize the condition in the movcond more; this allows some of the setcond that were feeding into movcond to be removed. Do not write into source1 and source2. Re-name "condN" to "tempN" and use the temporaries for more than holding conditions. Signed-off-by: Richard Henderson --- target/riscv/

[PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM

Move these helpers near their use by the trans_* functions within insn_trans/trans_rvm.c.inc. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 112 target/riscv/insn_trans/trans_rvm.c.inc | 112 2 files changed, 112

[PATCH v2 06/21] target/riscv: Remove gen_arith_div*

Use ctx->w and the enhanced gen_arith function. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 42 - target/riscv/insn_trans/trans_rvm.c.inc | 16 +- 2 files changed, 8 insertions(+), 50 deletions(-) diff --git a/target/riscv/trans

[PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB

Move these helpers near their use by the trans_* functions within insn_trans/trans_rvb.c.inc. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 233 --- target/riscv/insn_trans/trans_rvb.c.inc | 234 2 files changed, 234 i

[PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers

Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Signed-off-by: Richard Henderson --- target/riscv/tr

[PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

Signed-off-by: Richard Henderson --- target/riscv/translate.c| 58 - target/riscv/insn_trans/trans_rva.c.inc | 18 target/riscv/insn_trans/trans_rvb.c.inc | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 32 +++--- target/riscv/insn_trans

[PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu

Split out gen_mulh and gen_mulhu and use the common helper. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvm.c.inc | 40 +++-- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr

[PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith*

Most arithmetic does not require extending the inputs. Exceptions include division, comparison and minmax. Begin using ctx->w, which allows elimination of gen_addw, gen_subw, gen_mulw. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 69 +++-- t

[PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary

Use ctx->w for ctpopw, which is the only one that can re-use the generic algorithm for the narrow operation. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 14 ++ target/riscv/insn_trans/trans_rvb.c.inc | 24 +--- 2 files changed, 1

[PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rva.c.inc | 47 ++--- 1 file changed, 19 insertions(+), 28 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 3cc3c3b073..6ea07d89b0 100644 --- a

[PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations

These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 110 +--- target

[PATCH v2 12/21] target/riscv: Add gen_greviw

Replicate the bswap special case from gen_grevi for the word-sized operation. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/in

[PATCH v2 13/21] target/riscv: Use get_gpr in branches

Narrow the scope of t0 in trans_jalr. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++--- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc in

[PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV

Remove gen_get_gpr, as the function becomes unused. Signed-off-by: Richard Henderson --- target/riscv/translate.c| 13 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 74 +++-- 2 files changed, 26 insertions(+), 61 deletions(-) diff --git a/target/riscv/trans

[PATCH v2 15/21] target/riscv: Reorg csr instructions

Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only regi

[PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 23 ++- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index af7694ed29..d5a036b1f3 100644 --- a/t

[PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 36 + 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index af3e0bc0e6..f616a26c82 100644 --- a

[PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.c.inc | 146 1 file changed, 70 insertions(+), 76 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index fb9f7f9c00..bddbd418d9 100644 --- a

[PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 125 1 file changed, 60 insertions(+), 65 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 11b9b3f90b..db9ae15755 100644 --- a

[PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc

Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Signed-off-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvh.c.inc | 266 +--- 2 files cha

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, Aug 17, 2021 at 9:32 AM Paolo Bonzini wrote: > > On 17/08/21 01:53, Steve Rutherford wrote: > > Separately, I'm a little weary of leaving the migration helper mapped > > into the shared address space as writable. > > A related question here is what the API should be for how the migration >

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, Aug 17, 2021 at 1:50 PM Tobin Feldman-Fitzthum wrote: > > > On 8/17/21 12:32 PM, Paolo Bonzini wrote: > > There's three possibilities for this: > > > > 1) the easy one: the bottom 4G of guest memory are mapped in the > > mirror VM 1:1. The ram_addr_t-based addresses are shifted by either

Re: [PULL 24/27] accel/tcg: Move breakpoint recognition outside translation

On 8/17/21 5:39 AM, Richard Henderson wrote: Hmm, you're correct that we get this wrong. We probably didn't do these in the right priority order before this series, though, and I dunno whether we get the insn-abort vs swstep ordering right either... And you're correct that we got it wrong bef

[ANNOUNCE] QEMU 6.1.0-rc4 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the fifth release candidate for the QEMU 6.1 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-6.1.0-rc4.tar.xz http://downl

Re: [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

On 8/17/21 11:17 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 58 - > target/riscv/insn_trans/trans_rva.c.inc | 18 > target/riscv/insn_trans/trans_rvb.c.inc | 4 +- > target/riscv/insn_trans/tr

Re: [PATCH 0/2] target/arm: Implement remaining HSTR functionality

On 8/16/21 8:03 AM, Peter Maydell wrote: Peter Maydell (2): target/arm: Implement HSTR.TTEE target/arm: Implement HSTR.TJDBX Reviewed-by: Richard Henderson r~

Re: [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM

On 8/17/21 11:17 PM, Richard Henderson wrote: > Move these helpers near their use by the trans_* > functions within insn_trans/trans_rvm.c.inc. > > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 112 > target/riscv/insn_trans/trans_rvm

Re: [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB

On 8/17/21 11:17 PM, Richard Henderson wrote: > Move these helpers near their use by the trans_* > functions within insn_trans/trans_rvb.c.inc. > > Signed-off-by: Richard Henderson > --- > target/riscv/translate.c| 233 --- > target/riscv/insn_trans/trans_rvb.

Re: [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc

On 8/17/21 11:18 PM, Richard Henderson wrote: > Exit early if check_access fails. > Split out do_hlv, do_hsv, do_hlvx subroutines. > Use dest_gpr, get_gpr in the new subroutines. > > Signed-off-by: Richard Henderson > --- > target/riscv/insn32.decode | 1 + > target/riscv/insn_tra

Re: [PATCH v3] block/file-win32: add reopen handlers

On 8/17/21 10:21 PM, Viktor Prutyanov wrote: > Make 'qemu-img commit' work on Windows. > > Command 'commit' requires reopening backing file in RW mode. So, > add reopen prepare/commit/abort handlers and change dwShareMode > for CreateFile call in order to allow further read/write reopening. > > R

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford wrote: > > 1) the easy one: the bottom 4G of guest memory are mapped in the mirror > > VM 1:1. The ram_addr_t-based addresses are shifted by either 4G or a > > huge value such as 2^42 (MAXPHYADDR - physical address reduction - 1). > > This even le

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Wed, 2021-08-18 at 00:37 +0200, Paolo Bonzini wrote: > On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford > wrote: > > > 1) the easy one: the bottom 4G of guest memory are mapped in the > > > mirror > > > VM 1:1. The ram_addr_t-based addresses are shifted by either 4G > > > or a > > > huge valu

Re: [PATCH RFC v2 01/16] vfio-user: introduce vfio-user protocol specification

On Mon, 16 Aug 2021 09:42:34 -0700 Elena Ufimtseva wrote: > +Authentication > +-- > + > +For ``AF_UNIX``, we rely on OS mandatory access controls on the socket files, > +therefore it is up to the management layer to set up the socket as required. > +Socket types than span guests or hos

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, Aug 17, 2021 at 3:57 PM James Bottomley wrote: > Realistically, migration is becoming a royal pain, not just for > confidential computing, but for virtual functions in general. I really > think we should look at S3 suspend, where we shut down the drivers and > then reattach on S3 resume a

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, Aug 17, 2021 at 10:51 PM Tobin Feldman-Fitzthum wrote: > This is essentially what we do in our prototype, although we have an > even simpler approach. We have a 1:1 mapping that maps an address to > itself with the cbit set. During Migration QEMU asks the migration > handler to import/expo

Re: [PATCH v3 09/10] virtiofsd: Optionally fill lo_inode.fhandle

On Tue, Aug 17, 2021 at 03:45:19PM -0400, Vivek Goyal wrote: > On Tue, Aug 17, 2021 at 10:27:16AM +0200, Hanna Reitz wrote: > > On 16.08.21 21:44, Vivek Goyal wrote: > > > On Wed, Aug 11, 2021 at 08:41:18AM +0200, Hanna Reitz wrote: > > > > > > [..] > > > > > > But given the inotify complications,

[PATCH 0/4] target/arm: Fix insn exception priorities

As discussed earlier today at https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg02686.html Raise pc alignment faults. Fix single-step and pc-align priority over breakpoints. Not yet fixing insn abort priority over breakpoints. r~ Peter Maydell (1): target/arm: Take an exception if PST

[PATCH 2/4] target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn

It is confusing to have different exits from translation for various conditions in separate functions. Merge disas_a64_insn into its only caller. Standardize on the "s" name for the DisasContext, as the code from disas_a64_insn had more instances. Signed-off-by: Richard Henderson --- target/ar

[PATCH 3/4] target/arm: Take an exception if PC is misaligned

For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNDEF

[PATCH 4/4] target/arm: Suppress bp for exceptions with more priority

Both single-step and pc alignment faults have priority over breakpoint exceptions. Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..3

[PATCH 1/4] target/arm: Take an exception if PSTATE.IL is set

From: Peter Maydell In v8A, the PSTATE.IL bit is set for various kinds of illegal exception return or mode-change attempts. We already set PSTATE.IL (or its AArch32 equivalent CPSR.IL) in all those cases, but we weren't implementing the part of the behaviour where attempting to execute an instru

[PATCH v4] hw/dma/pl330: Add memory region to replace default

Add configurable property memory region which can connect with IOMMU region to support SMMU translate. Signed-off-by: Jianxian Wen --- v3 -> v4 (after review of Philippe Mathieu-Daudé): - Avoid adding unnecessary AS, add AS if we connect with IOMMU region. v2 -> v3 (after review of Philippe Mat

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Tue, 2021-08-17 at 16:10 -0700, Steve Rutherford wrote: > On Tue, Aug 17, 2021 at 3:57 PM James Bottomley > wrote: > > Realistically, migration is becoming a royal pain, not just for > > confidential computing, but for virtual functions in general. I > > really think we should look at S3 suspe

Re: [RFC] vfio/migration: reduce the msix virq setup cost in resume phase

在 2021/8/18 4:26, Alex Williamson 写道: > On Fri, 13 Aug 2021 12:06:14 +0800 > "Longpeng(Mike)" wrote: > >> In migration resume phase, all unmasked msix vectors need to be >> setup when load the VF state. However, the setup operation would >> takes longer if the VF has more unmasked vectors. >>

[Bug 1858814] Re: 'make -C roms efi' does not update edk2 submodules

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1858814 Title: 'make -C ro

[Bug 1880763] Re: Missing page crossing check in use_goto_tb() for rx target

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1880763 Title: Missing pag

Re: [RFC] vfio/migration: reduce the msix virq setup cost in resume phase

在 2021/8/18 11:50, Longpeng (Mike, Cloud Infrastructure Service Product Dept.) 写道: > > > 在 2021/8/18 4:26, Alex Williamson 写道: >> On Fri, 13 Aug 2021 12:06:14 +0800 >> "Longpeng(Mike)" wrote: >> >>> In migration resume phase, all unmasked msix vectors need to be >>> setup when load the VF sta

Re: [RFC PATCH: v3 1/2] add mi device in qemu

On Aug 3 12:54, Padmakar Kalghatgi wrote: > From: padmakar > > This patch contains the implementation of certain commands > of nvme-mi specification.The MI commands are useful to > manage/configure/monitor the device.Eventhough the MI commands > can be sent via the inband NVMe-MI send/recieve c

Re: [PATCH v2] tests/acceptance: Test powernv machines

On 17/08/2021 11.30, Cédric Le Goater wrote: Fetch the OpenPOWER images to boot the powernv8 and powernv9 machines with a simple PCI layout. Cc: Cleber Rosa Cc: Philippe Mathieu-Daudé Cc: Wainer dos Santos Moschetta Signed-off-by: Cédric Le Goater --- Since v2: - Change the skiboot.lid

Re: [PATCH 04/19] target/ppc: PMU Book3s basic insns count for pseries TCG

On Tue, Aug 17, 2021 at 06:30:37AM -0300, Daniel Henrique Barboza wrote: > > > On 8/16/21 11:59 PM, David Gibson wrote: > > On Mon, Aug 16, 2021 at 02:53:13PM -0300, Daniel Henrique Barboza wrote: > > > > > > > > > On 8/10/21 12:39 AM, David Gibson wrote: > > > > On Mon, Aug 09, 2021 at 10:10:4

Re: [RFC PATCH 00/13] Add support for Mirror VM.

On Mon, Aug 16, 2021 at 04:53:17PM -0700, Steve Rutherford wrote: > Separately, I'm a little weary of leaving the migration helper mapped > into the shared address space as writable. Since the migration threads > will be executing guest-owned code, the guest could use these threads > to do whatever

Re: [PATCH-for-6.1 v2] softmmu/physmem: fix wrong assertion in qemu_ram_alloc_internal()

On 16.08.21 22:52, Peter Xu wrote: On Thu, Aug 05, 2021 at 11:23:50AM +0200, David Hildenbrand wrote: When adding RAM_NORESERVE, we forgot to remove the old assertion when adding the updated one, most probably when reworking the patches or rebasing. We can easily crash QEMU by adding -object

Re: [PULL 00/11] Optional gitlab-CI and doc fixes for -rc4

On 16/08/2021 13.11, Daniel P. Berrangé wrote: On Mon, Aug 16, 2021 at 06:22:46AM -0400, Alexander Bulekov wrote: On 210816 1001, Peter Maydell wrote: On Sat, 14 Aug 2021 at 07:10, Thomas Huth wrote: Hi Peter, in case we're going to have an -rc4, here's a pull request that contains the fi

Re: [PATCH RESEND 1/2] memory: Name all the memory listeners

On 17.08.21 03:35, Peter Xu wrote: Provide a name field for all the memory listeners. It can be used to identify which memory listener is which. Signed-off-by: Peter Xu --- accel/hvf/hvf-accel-ops.c | 1 + accel/kvm/kvm-all.c | 7 +-- hw/i386/xen/xen-hvm.c

Re: [PATCH v3] vga: don't abort when adding a duplicate isa-vga device

On 16/08/2021 15.55, Jose R. Ziviani wrote: If users try to add an isa-vga device that was already registered, still in command line, qemu will crash: $ qemu-system-mips64el -M pica61 -device isa-vga RAMBlock "vga.vram" already registered, abort! Aborted (core dumped) That particular board regi

Re: [PATCH RESEND 2/2] memory: Add tracepoint for dirty sync

On 17.08.21 03:37, Peter Xu wrote: Trace at memory_region_sync_dirty_bitmap() for log_sync() or global_log_sync() on memory regions. One trace line should suffice when it finishes, so as to estimate the time used for each log sync process. I wonder if a start/finish would be even nicer. At lea

Re: [PATCH v3] vga: don't abort when adding a duplicate isa-vga device

On 17/08/2021 08:25, Thomas Huth wrote: On 16/08/2021 15.55, Jose R. Ziviani wrote: If users try to add an isa-vga device that was already registered, still in command line, qemu will crash: $ qemu-system-mips64el -M pica61 -device isa-vga RAMBlock "vga.vram" already registered, abort! Aborted

Re: [PATCH] net/colo: check vnet_hdr_support flag when using virtio-net

On 8/17/2021 2:01 PM, Tao Xu wrote: On 8/16/2021 10:58 AM, Jason Wang wrote: 在 2021/8/6 下午2:08, Tao Xu 写道: When COLO use only one vnet_hdr_support parameter between COLO network filter(filter-mirror, filter-redirector or filter-rewriter and colo-compare, packet will not be parsed correctly

Re: [PATCH v2] hw/intc/sifive_clint: Fix overflow in sifive_clint_write_timecmp()

On Tue, Aug 17, 2021 at 2:38 AM David Hoppenbrouwers wrote: > > `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This > resulted in high values such as `UINT64_MAX` being converted to `-1`, > which caused an immediate timer interrupt. > > By limiting `next` to `INT64_MAX` no over

Re: [PATCH v3] vga: don't abort when adding a duplicate isa-vga device

On 8/17/21 9:36 AM, Mark Cave-Ayland wrote: > On 17/08/2021 08:25, Thomas Huth wrote: > >> On 16/08/2021 15.55, Jose R. Ziviani wrote: >>> If users try to add an isa-vga device that was already registered, >>> still in command line, qemu will crash: >>> >>> $ qemu-system-mips64el -M pica61 -device

Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Currently we implement the RAS register block within the NVIC device. > It isn't really very tightly coupled with the NVIC proper, so instead > move it out into a sysbus device of its own and have the top level > ARMv7M container create it and map it

Re: [PATCH v3 09/10] virtiofsd: Optionally fill lo_inode.fhandle

On 16.08.21 21:44, Vivek Goyal wrote: On Wed, Aug 11, 2021 at 08:41:18AM +0200, Hanna Reitz wrote: [..] But given the inotify complications, there’s really a good reason we should use mountinfo. It’s a bit tricky because our sandboxing prevents easy access to mountinfo, but if that’s the only

Re: [PATCH] qemu-storage-daemon: Only display FUSE help when FUSE is built-in

On 16.08.21 20:04, Philippe Mathieu-Daudé wrote: When configuring QEMU with --disable-fuse, the qemu-storage-daemon still reports FUSE command line options in its help: $ qemu-storage-daemon -h Usage: qemu-storage-daemon [options] QEMU storage daemon --export [type=]fuse,id=,node-

Re: [RFC PATCH 00/13] Add support for Mirror VM.

* Steve Rutherford (srutherf...@google.com) wrote: > On Mon, Aug 16, 2021 at 6:37 AM Ashish Kalra wrote: > > > > From: Ashish Kalra > > > > This is an RFC series for Mirror VM support that are > > essentially secondary VMs sharing the encryption context > > (ASID) with a primary VM. The patch-set

Re: [PULL 24/30] spapr_pci: populate ibm,loc-code

On 8/16/21 6:37 AM, David Gibson wrote: > From 705a10b1cfbe6bcdde37f37f3548845970dc4986 Mon Sep 17 00:00:00 2001 > From: David Gibson > Date: Tue, 10 Aug 2021 14:28:19 +1000 > Subject: [PATCH] spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with > g_autofree > MIME-Version: 1.0 > Content-Ty

[PATCH 2/2] monitor: Report EBADFD if fdset contains invalid FD

When opening a path that starts with "/dev/fdset/" the control jumps into qemu_parse_fdset() and then into monitor_fdset_dup_fd_add(). In here, corresponding fdset is found and then all FDs from the set are iterated over trying to find an FD that matches expected access mode. For instance, if calle

[PATCH 1/2] chardev: Propagate error from logfile opening

If a chardev has a logfile the file is opened using qemu_open_old() which does the job, but since @errp is not propagated into qemu_open_internal() we lose much more accurate error and just report "Unable to open logfile $errno". When using plain files, it's probably okay as nothing complex is hap

[PATCH 0/2] Two chardev with fdset fixes

I was working on libvirt, trying to make it pass a pre-opened FD for a chardev's logfile. I've spent non-negligible amount of time trying to figure out why I was getting EACCESS error when QEMU definitely was able to access the FD. Well, found the problem and here is my attempt to save future me fr

Re: Picture missing in About dialog on cocoa ui

On Mon, 16 Aug 2021 at 21:55, Programmingkid wrote: > > > > > On Jul 8, 2021, at 2:38 PM, Programmingkid > > wrote: > > > > > > > >> On Jul 8, 2021, at 1:50 PM, Peter Maydell wrote: > >> > >> On Thu, 8 Jul 2021 at 17:28, Programmingkid > >> wrote: > >>> The problem with e31746ecf8dd2f25f687c9

Re: [PATCH 0/7] floppy: build as modules.

Hi John, On 8/16/21 11:55 PM, John Snow wrote: > On Thu, Aug 5, 2021 at 3:12 AM Gerd Hoffmann > wrote: > > On Wed, Aug 04, 2021 at 05:19:02PM +0200, Philippe Mathieu-Daudé wrote: > > +Mark > > > > On 8/4/21 4:27 PM, Gerd Hoffmann wrote: > > > Some co

[Bug 1846816] Re: Booting error on AIX 6.1 "Illegal Trap Instruction Interrupt in Kernel""

qemu-system-ppc64 should support AIX 5.3/6.1/7.1. If those OSes don't have virtio, then provide another way which simulates the machine's way to support the disk accessing. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.

Re: [PATCH 0/7] Add vmnet.framework based network backend

Hi Roman, Sorry for the late reply. In my series of patches I partially reuse Phillip Tennen's work that you have mentioned https://mail.gnu.org/archive/html/qemu-devel/2021-02/msg05874.html. The main idea and provided feature is the same, so please select the series on your choice. I just can say

Re: [PATCH 1/2] chardev: Propagate error from logfile opening

On 8/17/21 10:56 AM, Michal Privoznik wrote: > If a chardev has a logfile the file is opened using > qemu_open_old() which does the job, but since @errp is not > propagated into qemu_open_internal() we lose much more accurate > error and just report "Unable to open logfile $errno". When > using pl

Re: [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object

On 10:33 Thu 12 Aug , Peter Maydell wrote: > There's no particular reason why the NVIC should be owning the > SysTick device objects; move them into the ARMv7M container object > instead, as part of consolidating the "create the devices which are > built into an M-profile CPU and map them into

Re: [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m

On 10:33 Thu 12 Aug , Peter Maydell wrote: > @@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error > **errp) > qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); > qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); > > +/* > + * We map various devices int

Re: [PATCH] hw: ppc: sam460ex: Disable Ethernet devicetree nodes

On Tue, 17 Aug 2021, David Gibson wrote: On Mon, Aug 16, 2021 at 12:21:33PM +0200, BALATON Zoltan wrote: On Mon, 16 Aug 2021, David Gibson wrote: On Sun, Aug 15, 2021 at 07:59:15PM -0700, Guenter Roeck wrote: IBM EMAC Ethernet controllers are not emulated by qemu. If they are enabled in device

Re: [PATCH for-6.2 1/2] include/qemu/int128.h: introduce bswap128s

On 8/16/21 9:13 PM, matheus.fe...@eldorado.org.br wrote: > From: Matheus Ferst > > Introduces bswap128s based on bswap128. Since bswap128 is defined using > int128_* methods available in either CONFIG_INT128 or !CONFIG_INT128 > builds, place both outside of #ifdef CONFIG_INT128. > > Signed-off-b

Re: [PATCH 2/7] net/vmnet: add new netdevs to qapi/net

Hi Eric, Thank you for your review. сб, 7 авг. 2021 г. в 00:19, Eric Blake : > On Thu, Jun 17, 2021 at 05:32:41PM +0300, Vladislav Yaroshchuk wrote: > > Created separate netdev per each vmnet operating mode > > because they use quite different settings. Especially since > > macOS 11.0 (vmnet.fram

Re: [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Add the usual-style QEMU interface comment documenting what > properties, etc, this device exposes. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/timer/armv7m_systick.h | 7 +++ > 1 file changed, 7 insertions(+

Re: [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks

On 10:33 Thu 12 Aug , Peter Maydell wrote: > The v7M systick timer can be programmed to run from either of > two clocks: > * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) > * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) > > Our implementation currently hardwires the exter

Re: [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Create input clocks on the armv7m container object which pass through > to the systick timers, so that users of the armv7m object can specify > the clocks being used. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/a

Re: [PATCH 04/19] target/ppc: PMU Book3s basic insns count for pseries TCG

On 8/16/21 11:59 PM, David Gibson wrote: On Mon, Aug 16, 2021 at 02:53:13PM -0300, Daniel Henrique Barboza wrote: On 8/10/21 12:39 AM, David Gibson wrote: On Mon, Aug 09, 2021 at 10:10:42AM -0300, Daniel Henrique Barboza wrote: The PMCC (PMC Control) bit in the MMCR0 register controls whe

[PATCH v2] tests/acceptance: Test powernv machines

Fetch the OpenPOWER images to boot the powernv8 and powernv9 machines with a simple PCI layout. Cc: Cleber Rosa Cc: Philippe Mathieu-Daudé Cc: Wainer dos Santos Moschetta Signed-off-by: Cédric Le Goater --- Since v2: - Change the skiboot.lid file to use the one shipped with QEMU tests/a

Re: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Wire up the cpuclk for the systick devices to the SSE object's > existing mainclk clock. > > We do not wire up the refclk because the SSE subsystems do not > provide a refclk. (This is documented in the IoTKit and SSE-200 > TRMs; the SSE-300 TRM do

Re: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Connect up the armv7m clocks on the mps2-an385/386/500/511. > > Connect up the armv7m object's clocks on the MPS boards defined in > mps2.c. The documentation for these FPGA images doesn't specify what > systick reference clock is used (if any), so

Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize

On 10:33 Thu 12 Aug , Peter Maydell wrote: > In the realize methods of the stm32f100 and stm32f205 SoC objects, we > call g_new() to create new MemoryRegion objjects for the sram, flash, > and flash_alias. This is unnecessary (and leaves open the > possibility of leaking the allocations if we

Re: [PATCH] hw: ppc: sam460ex: Disable Ethernet devicetree nodes

On Tue, 17 Aug 2021 at 10:25, BALATON Zoltan wrote: > We could also modify the pc-bios/canyonlands.dts to comment out the > ethernet ports from it or add the disabled properties there, maybe also > adding a comment that explains these are not emulated in QEMU but to me > keeping the dts unmodified

Re: [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always > runs the systick refclk at 1/8 the frequency of the main CPU clock, > so the board code only needs to provide a single sysclk clock. > > Because there is only one board using th

Re: [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always > runs the systick refclk at 1/8 the frequency of the main CPU clock, > so the board code only needs to provide a single sysclk clock. > > Because there is only one board using th

Re: [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Delete the trailing blank line at the end of the source file. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/stm32vldiscovery.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm

Re: [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk

On 10:33 Thu 12 Aug , Peter Maydell wrote: > Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always > runs the systick refclk at 1/8 the frequency of the main CPU clock, > so the board code only needs to provide a single sysclk clock. > > Because there is only one board using th

Re: [PATCH 1/2] chardev: Propagate error from logfile opening

On Tue, Aug 17, 2021 at 12:56 PM Michal Privoznik wrote: > If a chardev has a logfile the file is opened using > qemu_open_old() which does the job, but since @errp is not > propagated into qemu_open_internal() we lose much more accurate > error and just report "Unable to open logfile $errno". W

Re: [PATCH 2/2] monitor: Report EBADFD if fdset contains invalid FD

Hi On Tue, Aug 17, 2021 at 12:56 PM Michal Privoznik wrote: > When opening a path that starts with "/dev/fdset/" the control > jumps into qemu_parse_fdset() and then into > monitor_fdset_dup_fd_add(). In here, corresponding fdset is found > and then all FDs from the set are iterated over trying

Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider

On 8/12/21 11:33 AM, Peter Maydell wrote: > It is quite common for a clock tree to involve possibly programmable > clock multipliers or dividers, where the frequency of a clock is for > instance divided by 8 to produce a slower clock to feed to a > particular device. > > Currently we provide no

Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device

On 8/17/21 10:25 AM, Luc Michel wrote: > On 10:33 Thu 12 Aug , Peter Maydell wrote: >> Currently we implement the RAS register block within the NVIC device. >> It isn't really very tightly coupled with the NVIC proper, so instead >> move it out into a sysbus device of its own and have the to

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