在 2021/7/2 下午2:12, Bin Meng 写道:
On Fri, Jul 2, 2021 at 1:47 PM Jason Wang wrote:
在 2021/7/2 下午12:43, Bin Meng 写道:
On Fri, Jul 2, 2021 at 11:29 AM Jason Wang wrote:
在 2021/7/1 下午5:46, Bin Meng 写道:
From: Christina Wang
The initial value of VLAN Ether Type (VET) register is 0x8100, as per
On 02.07.21 04:48, Wang, Wei W wrote:
On Thursday, July 1, 2021 10:22 PM, David Hildenbrand wrote:
On 01.07.21 14:51, Peter Xu wrote:
Spoiler alert: the introduction of clean bitmaps partially broke free page
hinting
already (as clearing happens deferred -- and might never happen if we don't
mi
On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei wrote:
>
>
> On 2021/7/2 下午1:38, Alistair Francis wrote:
> > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang wrote:
> >> LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道：
> >>>
> >>> On 2021/4/20 上午7:23, Alistair Francis wrote:
> On Fri, Apr 9, 2021 at 5:52 PM LIU Zh
On Tue, 29 Jun 2021 at 20:26, Richard Henderson
wrote:
>
> The following changes since commit 13d5f87cc3b94bfccc501142df4a7b12fee3a6e7:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-axp-20210628'
> into staging (2021-06-29 10:02:42 +0100)
>
> are available in the Git repository
On Sun, Jun 27, 2021 at 10:06 PM Bin Meng wrote:
>
> The following check:
>
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-
On Thu, 2021-07-01 at 12:51 +0200, Thomas Huth wrote:
> On 29/06/2021 16.19, Cho, Yu-Chen wrote:
> > move everything related to translate, as well as HELPER code in tcg/
> >
> > mmu_helper.c stays put for now, as it contains both TCG and KVM code.
> >
> > The internal.h file is renamed to s390x-i
On Mon, Jun 28, 2021 at 12:29 AM Bin Meng wrote:
>
> This adds detailed documentation for RISC-V `virt` machine,
> including the following information:
>
> - Supported devices
> - Hardware configuration information
> - Boot options
> - Running Linux kernel
> - Running U-Boot
>
> Signed-o
On Thu, 2021-07-01 at 14:36 +0200, Thomas Huth wrote:
> On 29/06/2021 16.19, Cho, Yu-Chen wrote:
> > Now that we have moved cpu-dump functionality out of helper.c,
> > we can make the module sysemu-only.
> >
> > Signed-off-by: Claudio Fontana
> > Signed-off-by: Cho, Yu-Chen
> > Acked-by: Corneli
On Thu, 2021-07-01 at 14:35 +0200, Thomas Huth wrote:
> On 29/06/2021 16.19, Cho, Yu-Chen wrote:
> > Splitting this functionality also allows us to make helper.c sysemu-
> > only.
> >
> > Signed-off-by: Claudio Fontana
> > Signed-off-by: Cho, Yu-Chen
> > Acked-by: Cornelia Huck
> > ---
> > ta
On 29/06/2021 16.19, Cho, Yu-Chen wrote:
split sysemu part of cpu models,
also create a tiny _user.c with just the (at least for now),
empty implementation of apply_cpu_model.
Signed-off-by: Claudio Fontana
Signed-off-by: Cho, Yu-Chen
---
MAINTAINERS | 1 +
target/s39
This adds description of the execlog TCG plugin with an example.
Signed-off-by: Alexandre Iooss
---
docs/devel/tcg-plugins.rst | 24
1 file changed, 24 insertions(+)
diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
index 18c6581d85..c1e589693c 100644
Log instruction execution and memory access to a file.
This plugin can be used for reverse engineering or for side-channel analysis
using QEMU.
Signed-off-by: Alexandre Iooss
Reviewed-by: Alex Bennée
---
MAINTAINERS | 1 +
contrib/plugins/Makefile | 1 +
contrib/plugins/execl
execlog is a plugin that logs executed instructions with some useful
metadata including memory access.
The output of the plugin is designed to be usable with other tools. For
example it could be used with a side-channel leakage model to create
side-channel traces from QEMU for security evaluation.
On 07/02/2021 04:31 AM, Philippe Mathieu-Daudé wrote:
> On 6/28/21 2:04 PM, Song Gao wrote:
>> This patch implement fixed point arithemtic instruction translation.
>>
>> This includes:
>> - ADD.{W/D}, SUB.{W/D}
>> - ADDI.{W/D}, ADDU16ID
>> - ALSL.{W[U]/D}
>> - LU12I.W, LU32I.D LU52I.D
>> - SLT[U]
On 7/2/21 10:15 AM, Song Gao wrote:
> On 07/02/2021 04:31 AM, Philippe Mathieu-Daudé wrote:
>> On 6/28/21 2:04 PM, Song Gao wrote:
>>> This patch implement fixed point arithemtic instruction translation.
>>>
>>> This includes:
>>> - ADD.{W/D}, SUB.{W/D}
>>> - ADDI.{W/D}, ADDU16ID
>>> - ALSL.{W[U]/D
On 6/18/21 9:29 PM, Richard Henderson wrote:
> Create and record the two signal trampolines.
> Use them when the guest does not use SA_RESTORER.
>
> Cc: Mark Cave-Ayland
> Signed-off-by: Richard Henderson
> ---
> linux-user/sparc/target_signal.h | 4
> linux-user/sparc/signal.c| 3
while at it just call rbd_get_size and avoid rbd_stat.
Signed-off-by: Peter Lieven
---
block/rbd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index b4caea4f1b..1f8dc84079 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -968,15 +968,14 @@ stat
Signed-off-by: Peter Lieven
---
block/rbd.c | 252 +++-
1 file changed, 90 insertions(+), 162 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index 1f8dc84079..be0471944a 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -66,22 +66,6 @@ typedef enu
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
---
block/rbd.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/block/rbd.c b/block/rbd.c
index 6b1cbe1d75..b4caea4f1b 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -90,6 +90,7 @@ typedef struct BDRVRBD
this series migrates the qemu rbd driver from the old aio emulation
to native coroutines and adds write zeroes support which is important
for block operations.
To achive this we first bump the librbd requirement to the already
outdated luminous release of ceph to get rid of some wrappers and
ifdef
even luminous (version 12.2) is unmaintained for over 3 years now.
Bump the requirement to get rid of the ifdef'ry in the code.
Qemu 6.1 dropped the support for RHEL-7 which was the last supported
OS that required an older librbd.
Signed-off-by: Peter Lieven
---
block/rbd.c | 120 ---
librbd supports 1 byte alignment for all aio operations.
Currently, there is no API call to query limits from the ceph backend.
So drop the bdrv_refresh_limits completely until there is such an API call.
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
---
block/rbd.c | 9 -
1 fil
Hi, Philippe,
On 07/02/2021 04:51 PM, Philippe Mathieu-Daudé wrote:
> On 7/2/21 10:15 AM, Song Gao wrote:
>> On 07/02/2021 04:31 AM, Philippe Mathieu-Daudé wrote:
>>> On 6/28/21 2:04 PM, Song Gao wrote:
This patch implement fixed point arithemtic instruction translation.
This includ
this patch wittingly sets BDRV_REQ_NO_FALLBACK and silently ignores
BDRV_REQ_MAY_UNMAP
for older librbd versions.
The rationale for this is as following (citing Ilya Dryomov current RBD
maintainer):
---8<---
a) remove the BDRV_REQ_MAY_UNMAP check in qemu_rbd_co_pwrite_zeroes()
and as a conseq
From: Christina Wang
The initial value of VLAN Ether Type (VET) register is 0x8100, as per
the manual and real hardware.
While Linux e1000 driver always writes VET register to 0x8100, it is
not always the case for everyone. Drivers relying on the reset value
of VET won't be able to transmit and
From: Christina Wang
In the legacy RX descriptor mode, VLAN tag was saved to d->special
by e1000e_build_rx_metadata() in e1000e_write_lgcy_rx_descr(), but
it was then zeroed out again at the end of the call, which is wrong.
Fixes: c89d416a2b0f ("e1000e: Don't zero out buffer address in rx descri
I'm going to send yet another series aiming to fix the DMA
reentrancy problem, which is based on these patches. Since
they are already reviewed, send them apart as a preparatory
series.
Since v2:
- Rebased, fixing conflicts in:
. hw/display/virtio-gpu.c
. hw/ide/ahci.c
. hw/net/allwinner-sun
Let devices specify transaction attributes when calling
dma_memory_read() or dma_memory_write().
Patch created mechanically using spatch with this script:
@@
expression E1, E2, E3, E4;
@@
(
- dma_memory_read(E1, E2, E3, E4)
+ dma_memory_read(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED)
|
From: Christina Wang
The initial value of VLAN Ether Type (VET) register is 0x8100, as per
the manual and real hardware.
While Linux e1000e driver always writes VET register to 0x8100, it is
not always the case for everyone. Drivers relying on the reset value
of VET won't be able to transmit and
Let devices specify transaction attributes when calling
dma_memory_set().
Reviewed-by: Richard Henderson
Reviewed-by: Li Qiang
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/spapr_vio.h | 3 ++-
include/sysemu/dma.h | 3 ++-
hw/nvram/fw_cfg.c
We will add the MemTxAttrs argument to dma_memory_rw() in
the next commit. Since dma_memory_rw_relaxed() is only used
by dma_memory_rw(), modify it first in a separate commit to
keep the next commit easier to review.
Reviewed-by: Richard Henderson
Reviewed-by: Li Qiang
Reviewed-by: Edgar E. Igle
Let devices specify transaction attributes when calling
dma_memory_rw().
Reviewed-by: Richard Henderson
Reviewed-by: Li Qiang
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 3 ++-
include/sysemu/dma.h | 11 ++-
hw/intc/spapr_xive.c
Let devices specify transaction attributes when calling
dma_memory_valid().
Reviewed-by: Richard Henderson
Reviewed-by: Li Qiang
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/spapr_vio.h | 2 +-
include/sysemu/dma.h | 4 ++--
2 files changed, 3
Let devices specify transaction attributes when calling
dma_memory_map().
Patch created mechanically using spatch with this script:
@@
expression E1, E2, E3, E4;
@@
- dma_memory_map(E1, E2, E3, E4)
+ dma_memory_map(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED)
Reviewed-by: Richard Henderson
ping ping!
On 25.06.2021 11:52, Denis Plotnikov wrote:
On vhost-user-blk migration, qemu normally sends a number of commands
to enable logging if VHOST_USER_PROTOCOL_F_LOG_SHMFD is negotiated.
Qemu sends VHOST_USER_SET_FEATURES to enable buffers logging and
VHOST_USER_SET_FEATURES per each start
It's possible that dies parameter is explicitly specified as "dies=0"
in the cmdline, if so we will wrongly calculate the other ommited
parameters such as "sockets = maxcpus / (dies * cores * threads);"
with a zeroed dies value.
So perform zero-check (default the value to 1 if zeroed) for -smp die
Since a machine type does not support topology parameter of dies,
it's probably more reasonable to reject any explicit specification
to avoid possible confuse, including "dies=0" and "dies=1" although
they won't affect the calculation of non-PC machines.
Also a comment of struct SMPConfiguration i
Hello,
Here are some smp parsing fix and improvement, most of which is about
the smp parsing helpers. This series was arranged based on the latest
QEMU code since commit d940d468e29b.
Description:
Patch #1 improves the calculation of maxcpus.
Patch #2 and #3 adds the missing zero-check for values
We are currently using maxcpus to calculate value of sockets but using
cpus to calculate value of cores/threads. This makes cmdlines like
"-smp 8,maxcpus=12,cores=4" work while "-smp 8,maxcpus=12,sockets=3"
break the invalid cpu topology check.
This patch allows us to uniformly use maxcpus to calc
We currently perform zero-check (default the value to 1 if zeroed)
for the computed values of cores/threads, to make sure they are at
least 1. For consistency, we probably should also default sockets
to 1 if the computed value is zero. Note that this won't affect
any existing working cmdlines but w
Now that all the possible topology parameters are integrated in struct
CpuTopology, tweak the order of topology members to be "cpus/sockets/
dies/cores/threads/maxcpus" for readability and consistency. We also
tweak the comment by adding explanation of dies parameter.
Signed-off-by: Yanan Wang
--
It is currently allowed to explicitly specified the topology parameters
as 0 in the -smp cmdlines, such as -smp cpus=8,maxcpus=0,sockets=0. And
for the values of cpus/sockets/cores/threads, we always determine that
they are ommited if either set to 0 in the cmdline(e.g. sockets=0) or
just not expli
On Wed, 30 Jun 2021 at 13:02, Daniel P. Berrangé wrote:
>
> The following changes since commit 13d5f87cc3b94bfccc501142df4a7b12fee3a6e7:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-axp-20210628'
> into staging (2021-06-29 10:02:42 +0100)
>
> are available in the Git repositor
On Fri, Jul 02, 2021 at 06:07:38PM +0800, Yanan Wang wrote:
> Since a machine type does not support topology parameter of dies,
> it's probably more reasonable to reject any explicit specification
> to avoid possible confuse, including "dies=0" and "dies=1" although
> they won't affect the calculat
On Thu, Jul 01, 2021 at 09:49:10PM +, Jiang Wang wrote:
Datagram sockets are connectionless and unreliable.
The sender does not know the capacity of the receiver
and may send more packets than the receiver can handle.
Add two more dedicate virtqueues for datagram sockets,
so that it will not
On Wed, Jun 23 2021, Ilya Leoshkevich wrote:
> qemu-s390x puts a wrong value into SIGILL's siginfo_t's psw.addr: it
> should be a pointer to the instruction following the illegal
> instruction, but at the moment it is a pointer to the illegal
> instruction itself. This breaks OpenJDK, which relie
Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.
Signed-off-by: Peter Maydell
---
hw/gpio/pl061.c | 70 ++--
hw/gpio/tr
From: Maxim Uvarov
qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.
Signed-off-by: Maxim Uvarov
Reviewed-by: Peter Maydell
Message-id: 20210625111842.379
Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.
Signed-off-by: Peter Maydell
---
hw/gpio/pl061.c | 27 +--
hw/gpio/trace-events | 6 ++
2 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/hw/gpio/pl061.c b/hw/gpio/p
Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch(). Clean
this up to use just a switch, using case ranges.
This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on
This series fixes a bug reported by Maxim where the virt board's
functionality intended to allow a guest in the Secure world to
shutdown or reset the system was broken. Patch 1 from Maxim (seen
already on-list) fixes a silly cut-n-paste error in the gpio-pwr
device. The rest of the series fixes the
The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties. Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that tri
The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.
For the plain PL061, continue to assume that lines h
The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns. Currently our implem
Add a comment documenting the "QEMU interface" of this device:
which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
Signed-off-by: Peter Maydell
---
hw/gpio/pl061.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index f3b80c7776f..06a1b82a503 1
The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR. We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up. Add a comment noting
this omission.
Signe
For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do ca
On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>
> even luminous (version 12.2) is unmaintained for over 3 years now.
> Bump the requirement to get rid of the ifdef'ry in the code.
> Qemu 6.1 dropped the support for RHEL-7 which was the last supported
> OS that required an older librbd.
>
> S
The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly. Expand the comment describing this,
including a sketch of the theoretical correct way to do it.
Signed-off-by: Peter Maydell
---
Given the stellaris board is old and not very useful these days,
I didn't think
On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>
> while at it just call rbd_get_size and avoid rbd_stat.
>
> Signed-off-by: Peter Lieven
> ---
> block/rbd.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index b4caea4f1b..1f8dc8407
On 7/2/21 12:40 PM, Peter Maydell wrote:
> Convert the use of the DPRINTF debug macro in the PL061 model to
> use tracepoints.
>
> Signed-off-by: Peter Maydell
> ---
> hw/gpio/pl061.c | 27 +--
> hw/gpio/trace-events | 6 ++
> 2 files changed, 15 insertions(+),
On 7/2/21 12:40 PM, Peter Maydell wrote:
> Add tracepoints for reads and writes to the PL061 registers. This requires
> restructuring pl061_read() to only return after the tracepoint, rather
> than having lots of early-returns.
>
> Signed-off-by: Peter Maydell
> ---
> hw/gpio/pl061.c | 70 +
On 7/2/21 12:40 PM, Peter Maydell wrote:
> The PL061 comes out of reset with all its lines configured as input,
> which means they might need to be pulled to 0 or 1 depending on the
> 'pullups' and 'pulldowns' properties. Currently we do not assert
> these lines on reset; they will only be set whe
On 7/2/21 12:40 PM, Peter Maydell wrote:
> The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
> reset value for GPIOPUR. We can get away with not letting the board
> configure the PUR reset value because we don't actually wire anything
> up to the lines which should reset to pul
On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>
> Signed-off-by: Peter Lieven
> ---
> block/rbd.c | 252 +++-
> 1 file changed, 90 insertions(+), 162 deletions(-)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index 1f8dc84079..be0471944a 10064
Cleber Rosa writes:
> TL;DR: this should allow the QEMU maintainer to push to the staging
> branch, and have custom jobs running on the project's aarch64 and
> s390x machines. Jobs in this version are allowed to fail, to allow
> for the inclusion of the novel machines/jobs without CI disruptio
Hi Peter,
On 7/2/21 12:40 PM, Peter Maydell wrote:
> Currently the pl061_read() and pl061_write() functions handle offsets
> using a combination of three if() statements and a switch(). Clean
> this up to use just a switch, using case ranges.
>
> This requires that instead of catching accesses t
Am 19.05.2021 um 13:25 hat Ilya Dryomov geschrieben:
> Jason has moved on from working on RBD and Ceph. I'm taking over
> his role upstream.
>
> Signed-off-by: Ilya Dryomov
Thanks, applied to the block branch.
Kevin
Am 27.06.2021 um 15:46 hat Ilya Dryomov geschrieben:
> On Sun, Jun 27, 2021 at 1:46 PM Or Ozeri wrote:
> >
> > Starting from ceph Pacific, RBD has built-in support for image-level
> > encryption.
> > Currently supported formats are LUKS version 1 and 2.
> >
> > There are 2 new relevant librbd API
On Fri, 2 Jul 2021 at 12:02, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 7/2/21 12:40 PM, Peter Maydell wrote:
> > Currently the pl061_read() and pl061_write() functions handle offsets
> > using a combination of three if() statements and a switch(). Clean
> > this up to use just a switch,
Le 02/07/2021 à 12:34, Cornelia Huck a écrit :
> On Wed, Jun 23 2021, Ilya Leoshkevich wrote:
>
>> qemu-s390x puts a wrong value into SIGILL's siginfo_t's psw.addr: it
>> should be a pointer to the instruction following the illegal
>> instruction, but at the moment it is a pointer to the illegal
Igor Mammedov 于2021年6月25日周五 下午5:19写道：
>
> it replaces error-prone pointer arithmetic for build_header() API,
> with 2 calls to start and finish table creation,
> which hides offsets magic from API user.
>
> Signed-off-by: Igor Mammedov
> ---
> CC: qemu-...@nongnu.org
> CC: drjo...@redhat.com
> CC
On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>
> this patch wittingly sets BDRV_REQ_NO_FALLBACK and silently ignores
> BDRV_REQ_MAY_UNMAP
> for older librbd versions.
>
> The rationale for this is as following (citing Ilya Dryomov current RBD
> maintainer):
> ---8<---
> a) remove the BDRV
On 01/07/2021 20:23, Connor Kuehl wrote:
> On 6/24/21 3:20 AM, Dov Murik wrote:
>> Add the sev_add_kernel_loader_hashes function to calculate the hashes of
>> the kernel/initrd/cmdline and fill a designated OVMF encrypted hash
>> table area. For this to work, OVMF must support an encrypted area
From: Marc-André Lureau
Before commit 49afbca3b00e8e517d54964229a794b51768deaf ("virtio-gpu: drop
use_virgl_renderer"), use_virgl_renderer was preventing calling GL
functions from non-GL context threads. The innocuously looking
g->parent_obj.use_virgl_renderer = false;
was set the first time
On Fri, Jul 2, 2021 at 11:09 AM Peter Lieven wrote:
>
> this series migrates the qemu rbd driver from the old aio emulation
> to native coroutines and adds write zeroes support which is important
> for block operations.
>
> To achive this we first bump the librbd requirement to the already
> outda
Thanks for your answers
On Fri, Jul 02, 2021 at 12:07:49AM +0200, Philippe Mathieu-Daudé wrote:
On 7/1/21 9:48 PM, Connor Kuehl wrote:
On 6/30/21 7:01 AM, Federico Vaga wrote:
Hello,
I can't find this information on the website, so here I am.
I developed a QEMU device that virtualises a PCI
From: Patrick Venture
Add line item reference to quanta-gbs-bmc machine.
Signed-off-by: Patrick Venture
Reviewed-by: Cédric Le Goater
Message-id: 20210615192848.1065297-3-vent...@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell
---
docs/system/arm/nuvoton.rst | 5
From: Patrick Venture
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
entry.
Signed-off-by: Patrick Venture
Reviewed-by: Cédric Le Goater
Message-id: 20210615192848.1065297-2-vent...@google.com
Signed-off-by: Peter Maydell
---
docs/system/arm/aspeed.rst | 1 +
1 file chang
ydell/qemu-arm.git
tags/pull-target-arm-20210702
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
target-arm queue:
* more MVE instruct
From: Joe Komlodi
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.
To avoid this, we check to see what NaN mode we're running in before we call
fl
From: Maxim Uvarov
qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.
Signed-off-by: Maxim Uvarov
Reviewed-by: Peter Maydell
Message-id: 20210625111842.379
From: Philippe Mathieu-Daudé
Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:
(1/1)
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
console: [0.00] Booting Linux on physical CPU 0xf00
console: [0.000
From: Nolan Leake
This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.
The watchdog timer functionality is not yet
In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector. This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.
Signed-off-by: Peter Maydell
Reviewed-by: Ri
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
* the 32x32 multiply of elements was being done as 32x32->32,
not 32x32->64
* we were incorrectly maintaining the accumulator in its full
72-bit form across all 4 beats of the insn; in the pseudocode
it
Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().
(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)
Signed-off-by: Peter Maydell
Reviewed
Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-11-peter.mayd...@linaro.org
---
target/arm/helper-mve.h| 8
target/arm/mve.decode | 9
targ
The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE. Move the implementation to translate.c, with a
prototype in translate.h.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 2021062
Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI. As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 202106
Implement the MVE VHLL (vector shift left long) insn. This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Mess
The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 2
The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers. They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.
Impl
Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
do_srshr() is borrowed from sve_helper.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-13-peter.mayd...@linaro.org
---
target/arm/helper-mve.h| 3
Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-7-peter.mayd...@lina
Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.
These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.
The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-8-peter.mayd...
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
do_urshr() is borrowed from sve_helper.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-12-peter.mayd...@linaro.org
---
target/arm/helper-mve.h| 10 ++
target/arm/mve.decod
Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-14-peter.mayd..
Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210628135835.6690-19-peter.mayd...@linaro.org
---
target/arm/helper-mve.h | 2 ++
target/arm/translate.h | 1 +
target/ar
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