>From the semihosting point of view what we want to know is the current
mode of the processor. Unify this into a single helper and allow us to
use the same GET/SET_ARG helpers for the rest of the code. Having the
helper will also be useful later.
Note: we aren't currently testing riscv32 due to mi
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
contrib/vhost-user-gpu/vugpu.h | 1 +
contrib/vhost-user-gpu/vhost-user-gpu.c | 27 -
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/contrib/vhost-user-gpu/vugpu.h b/contrib/vhost-us
Hi,
Change from the last version include tweaking the test to be a little
less asnprintf heavy and also don't rely on brk() to do it's job. It
also threw up a linux-user failure for RiscV which didn't have the
needed TaskState info set. The series now applies cleanly to master.
The following patc
On 3/12/21 11:00 AM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Track multiple callers blocking requests.
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/ui/console.c b/
As per the spec:
the PARAMETER REGISTER contains the address of a pointer to a
four-field data block.
So we need to follow arg0 and place the results of SYS_HEAPINFO there.
Fixes: 3c37cfe0b1 ("semihosting: Change internal common-semi interfaces to use
CPUState *")
Bug: https://bugs.launchpa
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
contrib/vhost-user-gpu/vugpu.h | 4 ++-
contrib/vhost-user-gpu/vhost-user-gpu.c | 46 +++--
2 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/contrib/vhost-user-gpu/vugpu.h b/contrib/vhost-
Query the SYS_HEAPINFO semicall and do some basic verification of the
information via libc calls.
Signed-off-by: Alex Bennée
---
v5
- drop asnprintf, just mix printf output
- don't use brk() but do sanity check
---
.../multiarch/arm-compat-semi/semihosting.c | 44 ++-
1 fi
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
include/ui/console.h | 2 ++
ui/console.c | 11 +++
ui/dbus-console.c| 5 -
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/ui/console.h b/include/ui/console.h
index 31141955d9..0ad0d3a
11.03.2021 06:15, Mahmoud Mandour wrote:
Replaced various qemu_mutex_lock/qemu_mutex_unlock calls with
lock guard macros (QEMU_LOCK_GUARD() and WITH_QEMU_LOCK_GUARD).
This slightly simplifies the code by eliminating calls to
qemu_mutex_unlock and eliminates goto paths.
Signed-off-by: Mahmoud Man
On 3/12/21 1:03 PM, leirao wrote:
> From: "Rao, Lei"
>
> When we use continuous dirty memory copy for flushing ram cache on
> secondary VM, we can also clean up the bitmap of contiguous dirty
> page memory. This also can reduce the VM stop time during checkpoint.
>
> Signed-off-by: Lei Rao
> --
Am 11.03.2021 um 18:24 hat Paolo Bonzini geschrieben:
> Extend the ObjectOption code that was added in the previous patch to
> enable passing JSON to -object. Even though we cannot yet add
> non-scalar properties with the human-friendly comma-separated syntax,
> they can now be added as JSON.
>
>
From: Marc-André Lureau
There is no support for other PIXMAN formats atm.
Signed-off-by: Marc-André Lureau
---
contrib/vhost-user-gpu/vhost-user-gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/vhost-user-gpu/vhost-user-gpu.c
b/contrib/vhost-user-gpu/vhost-use
> +offset = colo_bitmap_find_dirty(ram_state, block, offset,
> + &num);
IIUC, this return value would pass to the next round as start index, so you
should skip the already checked one.
Thanks
On 3/12/21 5:56 PM, Rao, Lei wrote:
> How about redefine a function named packet_new_no
This patch add vnc_display_reload_certs() to support
update x509 certificates.
Signed-off-by: Zihao Chang
Reviewed-by: Daniel P. Berrang??
---
include/ui/console.h | 1 +
ui/vnc.c | 28
2 files changed, 29 insertions(+)
diff --git a/include/ui/console.
This patch adds reload interface for QCryptoTLSCredsClass and implements
the interface for QCryptoTLSCredsX509.
Signed-off-by: Zihao Chang
---
crypto/tlscredsx509.c | 48 +++
include/crypto/tlscreds.h | 8 ---
2 files changed, 53 insertions(+), 3 dele
On 3/12/21 9:36 AM, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
>> On 7/7/20 11:24 PM, Markus Armbruster wrote:
>>> From: Vladimir Sementsov-Ogievskiy
>>>
>>> Script adds ERRP_GUARD() macro invocations where appropriate and
>>> does corresponding changes in code (look for details
This patch provides a new qmp to reload display configuration
without restart VM, but only reloading the vnc tls certificates
is implemented.
Example:
{"execute": "display-reload", "arguments":{"type": "vnc", "tls-certs": true}}
Signed-off-by: Zihao Chang
---
monitor/qmp-cmds.c | 15 +++
On 3/12/21 11:07 AM, Paolo Bonzini wrote:
> On 12/03/21 10:58, Claudio Fontana wrote:
>> Not really, but I have been using the accel class init function on x86 to
>> register the TCG OPS,
>>
>> and this instead requires a bit more thought for ARM,
>>
>> because we currently register for the ARM M
On 12/03/21 11:25, Claudio Fontana wrote:
We can register them from there if needed I think,, but where ever we
do it, we still have to point to the one set of ops or the other,
depending on the cpu model that is finally chosen.
So when we attach the tcg cpu accelerator object to the cpu, we
cur
On Fri, Mar 12, 2021 at 12:12:03AM +0900, Akihiko Odaki wrote:
> Based-on: <20210310042348.21931-1-akihiko.od...@gmail.com>
> Signed-off-by: Akihiko Odaki
Well, the comments should not describe what the code is doing, that is
usually pretty clear from reading the code. The comment should say
*wh
ping
Patchew page:
https://patchew.org/QEMU/20210303095910.78277-1-lekir...@yandex-team.ru
03.03.2021, 13:01, "Alexey Kirillov" :
> This patch series introduces a new QMP command "query-netdev" to get
> information about currently attached backend network devices (netdevs).
>
> Also, since the "
Arguably the target_cpu_copy_regs function for each architecture is
misnamed as a number of the architectures also take the opportunity to
fill out the TaskState structure. This could arguably be factored out
into common code but that would require a wider audit of the
architectures. For now just r
On Fri, 12 Mar 2021 at 10:31, Alex Bennée wrote:
>
> Query the SYS_HEAPINFO semicall and do some basic verification of the
> information via libc calls.
Are we both testing system emulation and linux-user, or just one of the two?
(Not that I want to hold this up if we're only testing one, but cov
On 12/03/2021 10.22, Thomas Huth wrote:
Make it clear that these files are related to benchmarks by moving
them into a new folder called "bench".
Signed-off-by: Thomas Huth
---
Based-on: 20210310063314.1049838-1-th...@redhat.com
tests/{ => bench}/atomic64-bench.c | 0
tests/{ =>
09.03.2021 20:34, Kevin Wolf wrote:
The image streaming block job restricts shared permissions of the nodes
it accesses. This can obviously fail when other users already got these
permissions. &error_abort is therefore wrong and can crash. Handle these
errors gracefully and just fail starting the
Am 11.03.2021 um 18:24 hat Paolo Bonzini geschrieben:
> The command-line creation test is using QemuOpts. Switch it to keyval,
> since the emulator has some special needs and thus the last user of
> user_creatable_add_opts will go away with the next patch.
>
> Signed-off-by: Paolo Bonzini
Revie
On 10/03/2021 17.46, Paolo Bonzini wrote:
"make check-speed" has been broken since the removal of ninja2make
last October. It was just a backwards-compatibility alias for
"make bench-speed", which in turn is in principle a subset of
"make bench". Advertise the latter and drop "make check-speed"
This series supports reload x509 certificates for vnc
1. Support reload x509 certificates.
2. Support reload vnc certificates.
3. Add new qmp display-reload and implement reload x509 certificates
for vnc.
Example:
{"execute": "display-reload", "arguments":{"type": "vnc", "tls-certs": true}}
Zihao
Public bug reported:
version: QEMU emulator version 5.2.0 (Debian 1:5.2+dfsg-6)
command line: qemu-system-aarch64 \
-machine virt,virtualization=on,graphics=on,usb=on -cpu cortex-a57 -smp
2 -m 2G \
-device virtio-blk-device,drive=hd0 \
-drive if=none,format=raw,id=hd0,file
On Fri, 12 Mar 2021 at 10:29, Alex Bennée wrote:
>
> As per the spec:
>
> the PARAMETER REGISTER contains the address of a pointer to a
> four-field data block.
>
> So we need to follow arg0 and place the results of SYS_HEAPINFO there.
>
> Fixes: 3c37cfe0b1 ("semihosting: Change internal commo
On Thu, Mar 11, 2021 at 06:29:53PM +, Daniel P. Berrangé wrote:
> Currently when resizing the VNC desktop we get a thin black bar down the
> right hand side of the screen 93% of the time, because the VNC server
> rounds up the display to a multiple of 16. This series solves this
> problem by fi
The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
SHA2, RSA and other cryptographic algorithms.
This initial model implements a subset of the device's functionality;
currently only direct access (non-scatter gather) hashing.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric
v3: Rework qtest to not use libqtest-single.h, rebase to avoid LPC
conflicts.
v2: Address review from Andrew and Philippe. Adds a qtest.
This adds a model for the ASPEED hash and crypto engine (HACE) found on
all supported ASPEED SoCs.
The model uses Qemu's gcrypto API to perform the SHA and MD5
My best guess is that the PCI I/O port handling in qemu only returns
data for ports that are connected to an actual device.
In this case, the kernel attempts to access a 8250 serial port at an
address where none exists. While this is also a bug in the kernel, a
real PCI implementation would not ca
Add the hash and crypto engine model to the Aspeed socs.
Reviewed-by: Andrew Jeffery
Signed-off-by: Joel Stanley
---
v3: Rebase on upstream
---
docs/system/arm/aspeed.rst | 2 +-
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast2600.c | 14 ++
hw/arm/aspeed_soc.c
Hi,
> The "dbus" ui/display backend exports the QEMU consoles over a currently
> unstable D-Bus protocol defined in ui/dbus-display1.xml (it is subject
> to changes at each releases, so only client shipped with the same QEMU
> release will be fully compatible).
Hmm, so we get a new protocol her
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
test fails.
Signed-off
Le 12/03/2021 à 11:15, Philippe Mathieu-Daudé a écrit :
> On 3/10/21 10:52 PM, Laurent Vivier wrote:
>> Peter,
>>
>> my "git publish" has failed at patch 20 with:
>>
>> Requested action aborted
>> Mails per session limit exceeded.
>>
>> I think my email provider has added new limits :(
>
> With GM
Hi,
On 16/02/2021 17:16, Peter Maydell wrote:
> From: Richard Henderson
>
> A proper syndrome is required to fill in the proper si_code.
> Use page_get_flags to determine permission vs translation for user-only.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> Message-id: 2
Patchew URL:
https://patchew.org/QEMU/20210312100108.2706195-1-marcandre.lur...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210312100108.2706195-1-marcandre.lur...@redhat.com
Subject: [PATCH 00/27] Add
On 12.03.21 10:09, Vladimir Sementsov-Ogievskiy wrote:
11.03.2021 22:58, Max Reitz wrote:
On 05.03.21 18:35, Vladimir Sementsov-Ogievskiy wrote:
There is a bug in qcow2: host cluster can be discarded (refcount
becomes 0) and reused during data write. In this case data write may
pollute another
On Fri, Mar 12, 2021 at 02:00:41PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
The whole series calls for a splitup. First the bugfixes, which we
should be able to fast-track for 6.0. Next the ui opengl changes. For
those a cover letter would be nice, describing the ove
On Fri, Mar 12, 2021 at 2:12 PM Philippe Mathieu-Daudé
wrote:
> On 3/12/21 11:00 AM, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Track multiple callers blocking requests.
> >
> > Signed-off-by: Marc-André Lureau
> > ---
> > ui/console.c | 17 +
> > 1
Quote docs/devel/style.rst (section "Automatic memory deallocation"):
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
Initialize @name properly to get rid of the compilation error (using
gcc-7.3.0 on CentOS):
../h
Peter Maydell writes:
> On Fri, 12 Mar 2021 at 10:31, Alex Benn=C3=A9e wro=
> te:
>>
>> Query the SYS_HEAPINFO semicall and do some basic verification of the
>> information via libc calls.
>
> Are we both testing system emulation and linux-user, or just one of the two=
> ?
Currently just linu
On Fri, 12 Mar 2021 at 11:24, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Fri, 12 Mar 2021 at 10:31, Alex Benn=C3=A9e wro=
> > te:
> >>
> >> Query the SYS_HEAPINFO semicall and do some basic verification of the
> >> information via libc calls.
> >
> > Are we both testing system emula
Hi
On Fri, Mar 12, 2021 at 3:03 PM Gerd Hoffmann wrote:
> Hi,
>
> > The "dbus" ui/display backend exports the QEMU consoles over a currently
> > unstable D-Bus protocol defined in ui/dbus-display1.xml (it is subject
> > to changes at each releases, so only client shipped with the same QEMU
> >
On 12/03/2021 11.57, Joel Stanley wrote:
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces u
Hi
On Fri, Mar 12, 2021 at 3:18 PM Gerd Hoffmann wrote:
> On Fri, Mar 12, 2021 at 02:00:41PM +0400, marcandre.lur...@redhat.com
> wrote:
> > From: Marc-André Lureau
>
> The whole series calls for a splitup. First the bugfixes, which we
> should be able to fast-track for 6.0. Next the ui openg
Am I missing it, or does the kernel's logging for data aborts not print
the FAR_EL1 value ?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1918917
Title:
synchronous about on accessing unused I/O po
Hi Alex,
are you also seeing this for make check-tcg on master?
make[2]: Entering directory
'/home/claudio/git/qemu-pristine/qemu/build-x86/tests/tcg/x86_64-softmmu'
timeout 15 /home/claudio/git/qemu-pristine/qemu/build-x86/qemu-system-x86_64
-monitor none -display none -chardev file,path=memo
Oh, I understand what you mean, and will change it in V3.
Thanks,
Lei.
-Original Message-
From: lizhij...@fujitsu.com
Sent: Friday, March 12, 2021 6:23 PM
To: Rao, Lei ; Zhang, Chen ;
jasow...@redhat.com; quint...@redhat.com; dgilb...@redhat.com;
pbonz...@redhat.com; lukasstra...@web.
On Tue, 9 Mar 2021 16:04:36 -0500
Chris Browy wrote:
Hi Chris,
As for patch 1, description needed here. Let's move this series towards
the form needed for a final submission.
2 features, 2 patches... If nothing else makes each one small enough to be
suitable for review with morning coffee :)
On 3/12/21 11:39 AM, Paolo Bonzini wrote:
> On 12/03/21 11:25, Claudio Fontana wrote:
>> We can register them from there if needed I think,, but where ever we
>> do it, we still have to point to the one set of ops or the other,
>> depending on the cpu model that is finally chosen.
>>
>> So when we
On Tue, 9 Mar 2021 15:33:49 -0500
Chris Browy wrote:
> Version 3 patch series for PCIe DOE for PCIe and CXL 2.0 implements
> all planned functionality.
>
> Based on QEMU version:
> https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4
>
> Summary:
> 1: PCIe DOE support for Discovery
>- Support
On Thu, Mar 11, 2021 at 02:53:15PM +0200, Maxim Levitsky wrote:
On Thu, 2021-03-04 at 11:15 +0100, Stefano Garzarella wrote:
On Wed, Mar 03, 2021 at 02:07:24PM +0200, Maxim Levitsky wrote:
> On Tue, 2021-03-02 at 15:52 +0100, Stefano Garzarella wrote:
> > On Mon, Mar 01, 2021 at 02:56:40PM +0200
On 12/03/21 12:51, Claudio Fontana wrote:
seems to me we already have, as the accel class init, fe, for x86/tcg:
static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
{
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
#ifndef CONFIG_USER_ONLY
acc->cpu_realizefn = tcg_cpu_realizef
From: Miroslav Rezanina
When declaring g_autofree variable without inicialization, compiler
will raise "may be used uninitialized in this function" warning due
to automatic free handling. This usage can cause gfree using unknown.
Such behavior can be dangerous and exploitable.
Add inicialization
From: Miroslav Rezanina
There are two different versions of prototype for tcg_out_op and
tcg_out_vec_op functions:
1) using const TCGArg *args and const int *const_args arguments
2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int
const_args[TCG_MAX_OP_ARGS]
aguments.
This duality cau
On 3/12/21 6:53 AM, Cédric Le Goater wrote:
On 3/12/21 2:55 AM, David Gibson wrote:
On Tue, 9 Mar 2021 18:26:35 +0100
Cédric Le Goater wrote:
On 3/9/21 6:08 PM, Daniel Henrique Barboza wrote:
On 3/9/21 12:33 PM, Cédric Le Goater wrote:
On 3/8/21 6:13 PM, Greg Kurz wrote:
On Wed, 3 Mar
On 29/01/2021 17.46, Jagannathan Raman wrote:
Hi,
This is the v21 of the patchset. This version has the following changes:
[PATCH v18 08/20] io: add qio_channel_readv_full_all_eof &
qio_channel_readv_full_all helpers
- Separates out the error handling for (len = 0) & (len < 0
12.03.2021 14:17, Max Reitz wrote:
On 12.03.21 10:09, Vladimir Sementsov-Ogievskiy wrote:
11.03.2021 22:58, Max Reitz wrote:
On 05.03.21 18:35, Vladimir Sementsov-Ogievskiy wrote:
There is a bug in qcow2: host cluster can be discarded (refcount
becomes 0) and reused during data write. In this
10.03.2021 12:32, Roman Kagan wrote:
NBD connect coroutine takes an extra in_flight reference as if it's a
request handler. This prevents drain from completion until the
connection coroutine is releases the reference.
When NBD is configured to reconnect, however, this appears to be fatal
to the
12.03.2021 15:32, Vladimir Sementsov-Ogievskiy wrote:
12.03.2021 14:17, Max Reitz wrote:
On 12.03.21 10:09, Vladimir Sementsov-Ogievskiy wrote:
11.03.2021 22:58, Max Reitz wrote:
On 05.03.21 18:35, Vladimir Sementsov-Ogievskiy wrote:
There is a bug in qcow2: host cluster can be discarded (ref
On Fri, 12 Mar 2021 at 00:18, Philippe Mathieu-Daudé wrote:
>
> If the SSECounter link is absent, we set an error message
> in sse_timer_realize() but forgot to propagate this error.
> Add the missing 'return'.
>
> Fixes: CID 1450755 (Null pointer dereferences)
> Signed-off-by: Philippe Mathieu-Da
12.03.2021 15:32, Vladimir Sementsov-Ogievskiy wrote:
12.03.2021 14:17, Max Reitz wrote:
On 12.03.21 10:09, Vladimir Sementsov-Ogievskiy wrote:
11.03.2021 22:58, Max Reitz wrote:
On 05.03.21 18:35, Vladimir Sementsov-Ogievskiy wrote:
There is a bug in qcow2: host cluster can be discarded (ref
On Wed, 10 Mar 2021 at 13:52, Andrew Jones wrote:
>
> This series fixes IPA limit setting for mach-virt KVM guests. The
> first patch restores the setting of IPA limits for values greater
> than 40 (the default) when necessary. The second patch ensures values
> less than 40 may also be used. The d
On Thu, 11 Mar 2021 at 18:08, Hao Wu wrote:
>
> This patch set implements the Tachometer (a.k.a Multi Functional Timer/MFT)
> device in NPCM7XX SoC. This device is used by NPCM7XX boards to measure
> the RPM of PWM fans.
>
> To provide the RPM of a certain fan, since RPM = MAX_RPM * duty_percentag
On 10/01/2020 16.30, Marc-André Lureau wrote:
Let's factor out the code to format a help string for a property. We
are going to reuse it in qdev next, which will bring some consistency.
Signed-off-by: Marc-André Lureau
---
include/qom/object.h| 13 +
qom/object_interfaces.c |
Hi
On Fri, Mar 12, 2021 at 4:54 PM Thomas Huth wrote:
> On 10/01/2020 16.30, Marc-André Lureau wrote:
> > Let's factor out the code to format a help string for a property. We
> > are going to reuse it in qdev next, which will bring some consistency.
> >
> > Signed-off-by: Marc-André Lureau
> >
On Fri, 12 Mar 2021 09:18:39 -0300
Daniel Henrique Barboza wrote:
>
>
> On 3/12/21 6:53 AM, Cédric Le Goater wrote:
> > On 3/12/21 2:55 AM, David Gibson wrote:
> >> On Tue, 9 Mar 2021 18:26:35 +0100
> >> Cédric Le Goater wrote:
> >>
> >>> On 3/9/21 6:08 PM, Daniel Henrique Barboza wrote:
> >>>
On Tue, 9 Mar 2021 at 11:45, Klaus Jensen wrote:
>
> From: Klaus Jensen
>
> ZASL (Zone Append Size Limit) is defined exactly like MDTS (Maximum Data
> Transfer Size), that is, it is a value in units of the minimum memory
> page size (CAP.MPSMIN) and is reported as a power of two.
>
> The 'mdts' n
On Tue, 9 Mar 2021 at 11:46, Klaus Jensen wrote:
>
> From: Minwoo Im
>
> This patch supports Namespace Attachment command for the pre-defined
> nvme-ns device nodes. Of course, attach/detach namespace should only be
> supported in case 'subsys' is given. This is because if we detach a
> namespa
Support JSON for --object in all tools and in HMP object_add in the same
way as it is supported in qobject_input_visitor_new_str().
Signed-off-by: Kevin Wolf
---
Based-on: <20210311144811.313451-1-kw...@redhat.com>
qom/object_interfaces.c | 32 +---
1 file changed, 2
On 2021/3/12 4:44 下午, Paolo Bonzini wrote:
On 12/03/21 07:16, Jason Wang wrote:
From: Paolo Bonzini
When a network or network device is created from the command line or
HMP,
QemuOpts ensures that the id passes the id_wellformed check. However,
QMP skips this:
$ qemu-system-x86_64 -qmp
On 3/12/21 1:18 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/12/21 6:53 AM, Cédric Le Goater wrote:
>> On 3/12/21 2:55 AM, David Gibson wrote:
>>> On Tue, 9 Mar 2021 18:26:35 +0100
>>> Cédric Le Goater wrote:
>>>
On 3/9/21 6:08 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/9/21
On Thu, 11 Mar 2021 14:27:46 +0100
Cornelia Huck wrote:
> The single-frame z15 is called "z15 T02".
>
> Signed-off-by: Cornelia Huck
> ---
> target/s390x/cpu_models.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
Based-on: <20210310042348.21931-1-akihiko.od...@gmail.com>
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 035f96aab04..35fdc92a51f 100644
--- a/ui/cocoa.m
+++ b/ui
QEMU ppce500 machine can dynamically instantiate an eTSEC device
if "-device eTSEC" is given to QEMU.
This series updates the fixed-link ethernet PHY driver as well as
the Freescale eTSEC driver to support the QEMU ppce500 board.
3 patches related to fixed phy in v1 are dropped in v2 as the chang
On 3/11/21 8:19 PM, David Gibson wrote:
On Thu, Mar 11, 2021 at 05:50:42PM -0300, Daniel Henrique Barboza wrote:
On 3/9/21 3:22 AM, Markus Armbruster wrote:
Cc: Paolo and Julia in addition to Igor, because the thread is wandering
towards DeviceState member pending_deleted_event.
Cc: Laine fo
On 3/12/21 1:02 PM, Paolo Bonzini wrote:
> On 12/03/21 12:51, Claudio Fontana wrote:
>> seems to me we already have, as the accel class init, fe, for x86/tcg:
>>
>> static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
>> {
>> AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>>
>> #ifndef
On 05.03.21 18:35, Vladimir Sementsov-Ogievskiy wrote:
Implement cache for small sequential unaligned writes, so that they may
be cached until we get a complete cluster and then write it.
The cache is intended to be used for backup to qcow2 compressed target
opened in O_DIRECT mode, but can be r
On 3/12/21 12:05 PM, Laurent Vivier wrote:
> Le 12/03/2021 à 11:15, Philippe Mathieu-Daudé a écrit :
>> On 3/10/21 10:52 PM, Laurent Vivier wrote:
>>> Peter,
>>>
>>> my "git publish" has failed at patch 20 with:
>>>
>>> Requested action aborted
>>> Mails per session limit exceeded.
>>>
>>> I think
On 11.03.21 14:27, Cornelia Huck wrote:
The single-frame z15 is called "z15 T02".
Signed-off-by: Cornelia Huck
Acked-by: Christian Borntraeger
---
target/s390x/cpu_models.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu
On 3/12/21 1:03 PM, mreza...@redhat.com wrote:
> From: Miroslav Rezanina
>
> When declaring g_autofree variable without inicialization, compiler
> will raise "may be used uninitialized in this function" warning due
> to automatic free handling. This usage can cause gfree using unknown.
> Such beh
2021-03-11 18:55:27 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210312-1
for you to fetch changes up to 41f09f2e9f09e4dd386d84174a6dcb5136af17ca:
hw/display/pxa2xx: Inline template header (2021-03-12 13:2
From: "Edgar E. Iglesias"
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-by: Edgar E. Iglesia
From: Eric Auger
With -Werror=maybe-uninitialized configuration we get
../hw/i386/intel_iommu.c: In function ‘vtd_context_device_invalidate’:
../hw/i386/intel_iommu.c:1888:10: error: ‘mask’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
1888 | mask = ~mask;
|
From: "Edgar E. Iglesias"
Connect the support for the Versal Accelerator RAMs (XRAMs).
Reviewed-by: Luc Michel
Acked-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
Message-id: 20210308224637.2949533-3-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
docs/system/arm/xlnx-vers
From: Eric Auger
If the asid is not set, do not attempt to locate the key directly
as all inserted keys have a valid asid.
Use g_hash_table_foreach_remove instead.
Signed-off-by: Eric Auger
Message-id: 20210309102742.30442-5-eric.au...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Pete
From: Eric Auger
As of today, the driver can invalidate a number of pages that is
not a power of 2. However IOTLB unmap notifications and internal
IOTLB invalidations work with masks leading to erroneous
invalidations.
In case the range is not a power of 2, split invalidations into
power of 2 in
From: Eric Auger
Currently get_naturally_aligned_size() is used by the intel iommu
to compute the maximum invalidation range based on @size which is
a power of 2 while being aligned with the @start address and less
than the maximum range defined by @gaw.
This helper is also useful for other iomm
From: Richard Henderson
With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that ar
From: Richard Henderson
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson
Message-id: 20210309155305.11301-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/sve_
From: Eric Auger
Convert all sid printouts to sid=0x%x.
Signed-off-by: Eric Auger
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210309102742.30442-8-eric.au...@redhat.com
Signed-off-by: Peter Maydell
---
hw/arm/trace-events | 24
1 file changed, 12 insertions(+),
From: Eric Auger
Unmap notifiers work with an address mask assuming an
invalidation range of a power of 2. Nothing mandates this
in the VIRTIO-IOMMU spec.
So in case the range is not a power of 2, split it into
several invalidations.
Signed-off-by: Eric Auger
Reviewed-by: Peter Xu
Message-id:
From: Richard Henderson
Wrote too much with punpk1 with vl % 512 != 0.
Reviewed-by: Peter Maydell
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20210309155305.11301-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/sve_helper.c | 4 ++--
From: Richard Henderson
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson
Message-id: 20210309155305.11301-8-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/sve_
From: Richard Henderson
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson
Message-id: 20210309155305.11301-7-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/sve_
From: Richard Henderson
Wrote too much with low-half zip (zip1) with vl % 512 != 0.
Adjust all of the x + (y << s) to x | (y << s) as a style fix.
We only ever have exact overlap between D, M, and N. Therefore
we only need a single temporary, and we do not need to check for
partial overlap.
R
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