Hi
On Sun, Feb 14, 2021 at 3:20 AM Laurent Vivier wrote:
> Le 04/11/2020 à 08:46, Marc-André Lureau a écrit :
> >
> >
> > On Mon, Oct 26, 2020 at 1:16 PM AlexChen alex.c...@huawei.com>> wrote:
> >
> > Fix some error style problems found by checkpatch.pl <
> http://checkpatch.pl>.
> >
> >
On Wed, 13 Jan 2021 10:46:32 +0800
leirao wrote:
> From: "Rao, Lei"
>
> If we don't disable the feature of auto-converge for live migration
> before entering COLO mode, it will continue to run with COLO running,
> and eventually the system will hang due to the CPU throttle reaching
> DEFAULT_MI
Hello,
This series is to support Asymmetric Namespace Access(ANA).
`ana` parameter to the `nvme-subsys` device will turn all the
controllers in the subsystem to support multipath I/O with ANA. Once
ana is enabled, `nvme-ns` device can have `ana.grpid` for the ANA group
ID. All this information
Recently we have been able to introduce multipath I/O with namespace
sharing with a single host. One of the major feature for the multipath
I/O is Asymmetric Namespace Access: so-called ANA.
Also, the multipath I/O is one of the most major path for the host
system where this feature addition migh
Human Monitor Interface(HMP) is there for easy human debugging. This
patch added a HMP command 'nvme_ana_inject_state'. This can be executed
from the QEMU monitor. This command will have the following syntax:
# nvme_ana_inject_state
(qemu) nvme_ana_inject_state nvme0 1 inacce
Vincent Fazio writes:
> From: Vincent Fazio
>
> Previously, pgd_find_hole_fallback assumed that if the build host's libc
> had MAP_FIXED_NOREPLACE defined that the address returned by mmap would
> match the requested address. This is not a safe assumption for Linux
> kernels prior to 4.17
It
Vincent Fazio writes:
> From: Vincent Fazio
>
> Previously, if the build host's libc did not define MAP_FIXED_NOREPLACE
> or if the running kernel didn't support that flag, it was possible for
> pgd_find_hole_fallback to munmap an incorrect address which could lead to
> SIGSEGV if the range ha
On Fri, 29 Jan 2021 02:57:57 +
"Rao, Lei" wrote:
> The state will be set RUN_STATE_COLO in colo_do_checkpoint_transaction(). If
> the guest executes power off or shutdown at this time and the QEMU main
> thread will call vm_shutdown(), it will set the state to RUN_STATE_SHUTDOWN.
> The stat
On Wed, 13 Jan 2021 10:46:25 +0800
leirao wrote:
> The series of patches include:
> Fixed some bugs of qemu crash.
> Optimized some code to reduce the time of checkpoint.
> Remove some unnecessary code to improve COLO.
>
The rest of the patches look good to me. Can you address
Le 14/02/2021 à 12:24, Alex Bennée a écrit :
>
> Vincent Fazio writes:
>
>> From: Vincent Fazio
>>
>> Previously, pgd_find_hole_fallback assumed that if the build host's libc
>> had MAP_FIXED_NOREPLACE defined that the address returned by mmap would
>> match the requested address. This is not a
On Sun, Feb 14, 2021 at 6:50 AM Laurent Vivier wrote:
>
> Le 14/02/2021 à 12:24, Alex Bennée a écrit :
> >
> > Vincent Fazio writes:
> >
> >> From: Vincent Fazio
> >>
> >> Previously, pgd_find_hole_fallback assumed that if the build host's libc
> >> had MAP_FIXED_NOREPLACE defined that the addre
Hello,
This series has been discussed and reviewed in [1]. This is the second
series to support Advanced Command Retry Enable(ACRE).
At the first shot, It was designed to provide HMP commands to inject
artificial state to the NVMe device. But, as discussed, rather than
making a device with a ar
Set CRDT1(Command Retry Delay Time 1) in the Identify controller data
structure to milliseconds units of 100ms by the given value of
'cmd-retry-delay' parameter which is newly added. If
cmd-retry-delay=1000, it will be set CRDT1 to 10. This patch only
considers the CRDT1 without CRDT2 and 3 for t
From: Phillip Tennen
This patch implements a new netdev device, reachable via -netdev
vmnet-macos, that’s backed by macOS’s vmnet framework.
The vmnet framework provides native bridging support, and its usage in
this patch is intended as a replacement for attempts to use a tap device
via the tun
On Thu, Nov 8, 2018 at 7:45 PM Fredrik Noring wrote:
>
> Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
> supporting the n32 ABI.
>
> Signed-off-by: Fredrik Noring
> ---
> linux-user/mips64/target_elf.h | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Philippe Mat
Hi!
As known for a long time, qemu's linux-user, when invoked in context of
binfmt-misc mechanism,
does not preserve the original argv[0] element, so some software which relies
on argv[0] is
not functioning under qemu-user. When run this way, argv[0] of the program
being run under
qemu-user p
On Sun, Feb 14, 2021 at 11:17 PM Philippe Mathieu-Daudé wrote:
>
> On Thu, Nov 8, 2018 at 7:45 PM Fredrik Noring wrote:
Oops, an old patch from 2018 and was never applied?
> >
> > Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
> > supporting the n32 ABI.
> >
> > Signed-o
Patchew URL:
https://patchew.org/QEMU/27dfe8eb-adce-8db4-f28b-c42858b08...@msgid.tls.msk.ru/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 27dfe8eb-adce-8db4-f28b-c42858b08...@msgid.tls.msk.ru
Subject: RFC: linux-user
On Sun, Feb 14, 2021 at 1:56 PM Bin Meng wrote:
>
> Hi Alexander,
>
> On Fri, Feb 12, 2021 at 5:25 AM Alexander Bulekov wrote:
> >
> > On 210211 1154, Alexander Bulekov wrote:
> > ...
> > > I applied this along with <20210208193450.2689517-1-f4...@amsat.org>
> > > "hw/sd/sdhci: Do not modify Bloc
On 2/11/21 1:50 PM, Alessandro Di Federico via wrote:
> +%define parse.error detailed
/usr/share/bison/skeletons/bison.m4:1033: error: invalid error_verbose value:
/usr/share/bison/skeletons/bison.m4:1033: the top level
/home/rth/qemu/git-hex/target/hexagon/idef-parser/idef-parser.y:35.1-28: error
On 2/7/21 9:45 PM, Taylor Simpson wrote:
> Define types used in files imported from the Hexagon architecture library
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/hex_arch_types.h | 38 ++
> 1 file changed, 38 insertions(+)
> create mode 100644 tar
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +uint32_t extension_valid:1; /* Has a constant extender attached */
> +uint32_t which_extended:1;/* If has an extender, which immediate */
> +uint32_t is_endloop:1; /* This is an end of loop */
...
> +uint32_t pkt_has_cof:1;
Le 14/02/2021 à 16:17, Philippe Mathieu-Daudé a écrit :
> On Thu, Nov 8, 2018 at 7:45 PM Fredrik Noring wrote:
>>
>> Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
>> supporting the n32 ABI.
>>
>> Signed-off-by: Fredrik Noring
>> ---
>> linux-user/mips64/target_elf.h | 3
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +const RegField reg_field_info[] = {
> +#define DEF_REG_FIELD(TAG, START, WIDTH)\
> + { START, WIDTH },
> +#include "reg_fields_def.h.inc"
> + { 0, 0 }
> +#undef DEF_REG_FIELD
> +};
What is the purpose of the 0,0 entry? Surely you don't act
The R5900 CPU was removed some time ago (frankly I don't remember
why). This series add it back, but to prove it works, we also add
testing at the end.
The main motivation is to have MIPS R5900 coverage, but to be able
to run real world r5900 binaries, I had to implement more opcodes.
42 patches
64-bit MIPS targets lost setup_frame() during the refactor in commit
8949bef18b9. Restore it declaring TARGET_ARCH_HAS_SETUP_FRAME, to be
able to build the o32 ABI target.
Fixes: 8949bef18b9 ("linux-user: move mips/mips64 signal.c parts to mips
directory")
Reviewed-by: Richard Henderson
Reviewed
The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.
Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.
When the code is similar to the GPR lower halves, m
TCG displays the upper halve registers with the same name
as their lower halves. Rename the upper halves with the
'[hi]' suffix.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/targ
o32 ABI syscalls start at offset 4000.
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/syscall_nr.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 4
target/mips/translate.c | 18 ++
2 files changed, 22 insertions(+)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3014c20cadb..468e29d7578 100644
--- a/target/mips/translate.h
+++ b
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 +++
target/mips/translate.c | 25 -
target/mips/tx79_translate.c | 14 ++
3 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/target/mips/tx79.decode b/target/mips/tx
We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 1 +
target/mips/translate.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mi
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
v3: Use missing rt, optimize (Richard)
---
target/mips/translate.c | 34 ---
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/target/mips
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed
Introduce the 'Parallel Extend Lower' opcodes:
- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 ++
target/mips/tx79_translate.c | 7
Introduce the 'Parallel Subtract' opcodes:
- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel Subtract Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 6
target/mips/tx79_translate.c | 61 ++
Introduce the PEXTUW opcode (Parallel Extend Upper from Word).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 4
target/mips/tx79_translate.c | 26 ++
2 files changed, 30 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx7
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 5 +
target/mips/translate.c | 39
target/mips/tx79_translate.c | 22
Introduce the 'Parallel Compare for Greater Than' opcodes:
- PCGTB (Parallel Compare for Greater Than Byte)
- PCGTH (Parallel Compare for Greater Than Halfword)
- PCGTW (Parallel Compare for Greater Than Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 +++
t
Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW
(Parallel Exchange Even Word) opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 2 ++
target/mips/tx79_translate.c | 70
2 files changed, 72 insertions(+)
diff -
Introduce the parallel logic opcodes:
- PAND (Parallel AND)
- POR (Parallel OR)
- PXOR (Parallel XOR)
- PNOR (Parallel NOR)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 4 +++
target/mips/tx79_translate.c | 54
2 files chang
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 6 +++
target/mips/translate.c | 84
tar
Introduce the PINTEH opcode (Parallel Interleave Even Halfword).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 45
2 files changed, 46 insertions(+)
diff --git a/target/mips/tx79.decode b/target
Introduce the PROT3W opcode (Parallel Rotate 3 Words).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 28
2 files changed, 29 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
Introduce the 'Parallel Compare for Equal' opcodes:
- PCEQB (Parallel Compare for Equal Byte)
- PCEQH (Parallel Compare for Equal Halfword)
- PCEQW (Parallel Compare for Equal Word)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 ++
target/mips/tx79_translate.c |
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().
As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.
Signed-off-by: Philippe Mathieu-Dau
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index bc91ac4f
Introduce the SQ opcode (Store Quadword).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 27 +++
2 files changed, 28 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index b5396f48
Introduce the PPACW opcode (Parallel Pack to Word).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 30 ++
2 files changed, 31 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
i
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 160 -
target/mips/tx79_translate.c | 188 +++
From: Fredrik Noring
Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
supporting the n32 ABI.
Signed-off-by: Fredrik Noring
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id:
<5bea109f0c140da6a821aa7f9705d4b371
From: Fredrik Noring
The R5900 reports itself as MIPS III but does not implement DMULT.
Verify that DMULT is emulated properly in user mode by multiplying
two 64-bit numbers to produce a 128-bit number.
Signed-off-by: Fredrik Noring
Message-Id:
Signed-off-by: Philippe Mathieu-Daudé
---
test
Now than SQ is properly implemented, we can move the RDHWR
kludge required to have usermode working with recent glibc.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 56
target/mips/tx79_translate.c | 34 +-
2 fil
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/attribs.h | 35 +++
> target/hexagon/attribs_def.h.inc | 97
>
> 2 files changed, 132 insertions(+)
Now that we have the minimum prerequisites to support the
R5900 CPU, we can reintroduce it.
While we are reverting commit 823f2897bdd ("Disable R5900
support"), we effectively cherry-pick commit ed4f49ba9bb
("target/mips: Define the R5900 CPU").
This reverts commit 823f2897bdd78185f3ba33292a25105
The Avocado Test::fetch_asset() is handy to download artifacts
before running tests. The current class is named Test but only
tests system emulation. As we want to test user emulation,
refactor the common code as QemuBaseTest.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qe
MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data
model, allowing 64-bit arithmetic and data movement instructions.
Since this ABI seems to have only ever been used for the
development of the PS2 with the "Sony Linux Toolkit for
Playstation 2" targetting the R5900 CPU (little-endian),
w
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/configure.sh | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index e1b70e25f23..64796ee11fc 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -57,6 +57,
Introduce the LQ opcode (Load Quadword) and remove unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 8
target/mips/translate.c | 16 ++--
target/mips/tx79_translate.c | 35 +++
3 files changed, 4
Add a Docker image providing cross toolchain for the MIPS R5900 CPU
(used on the Sony PS2).
This image is based on Gentoo and the toolchain is built using crossdev.
Recipe from:
https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg03944.html
Suggested-by: Fredrik Noring
Signed-off-by: Phi
Make pick_default_qemu_bin() generic to find qemu-system or
qemu-user binaries.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/acceptance/avocado_qemu/__init__.py
b/tests/ac
Pass EXTRA_FILES to tests/docker/docker.py to use its --extra-files
command line option.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/containers.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 90fac85ce46..587bd4ba
On 2/8/21 6:46 AM, Taylor Simpson wrote:
> Enable multiarch tests for Hexagon
> Modify tests/tcg/configure.sh
> Add reference files to tests/tcg/hexagon
>
> Signed-off-by: Taylor Simpson
> ---
> tests/tcg/configure.sh| 4 +-
> tests/tcg/hexagon/Makefile.target | 30 ++
> tests/tcg
Similarly to the 'System' Test base class with methods for testing
system emulation, the QemuUserTest class contains methods useful to
test user-mode emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 15 +++
1 file changed, 15 insertions
Run some integration tests for the r5900o32el-linux-user target.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 7d7559416e3..ba2c9ac0b4d 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.ym
Add a job to build the Gentoo based MIPS R5900 cross-toolchain image.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/containers.yml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 587bd4ba2e3..f441e608446 100644
-
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 10 ++
> 1 file changed, 10 insertions(+)
Tested-by: Philippe Mathieu-Daudé
Test BusyBox on the R5900 CPU with 2 different binaries:
- o32 32-bit (statically linked)
- o32 64-bit (dynamically linked, uses multimedia instructions)
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
tests/acceptance/mips_r5900_ps2.py | 69
Add a job to build the MIPS r5900o32el (linux-user) target
and run the TCG tests.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 12
1 file changed, 12 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 28a83afb914..7d7559416e3 100644
--- a/.gitlab-ci.yml
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/14/21 6:58 PM, Philippe Mathieu-Daudé wrote:
> The R5900 CPU was removed some time ago (frankly I don't remember
> why). This series add it back, but to prove it works, we also add
> testing at the end.
>
> The main motivation is to have MIPS R5900 coverage, but to be able
> to run real world
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Add an unsigned inequality operation. Do not fill in all of
> the variations until we have a call for them.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Philip
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +#define DECODE_MAPPED_REG(REGNO, NAME) \
> +insn->regno[REGNO] = DECODE_REGISTER_##NAME[insn->regno[REGNO]];
The macro argument is not a regno, but an operand number.
> +static inline int decode_opcode_can_jump(int opcode)
> +{
> +if ((GET_ATTRI
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/printinsn.h | 27 +
> target/hexagon/printinsn.c | 146
> +
> 2 files changed, 173 insertions(+)
> create m
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Change these to sar/shl to emphasize the signed shift.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 8
> softmmu/physmem.c | 4 ++--
> target/ppc/int_helper.c | 4 ++--
> tests/test-int128.c | 44
On 10/21/20 6:51 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/fpu/softfloat.h| 5 -
> fpu/softfloat-specialize.c.inc | 12
> 2 files changed, 4 insertions(+), 13 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, 12 Feb 2021 at 23:24, Eric Blake wrote:
>
> The following changes since commit eac92d316351b855ba79eb374dd21cc367f1f9c1:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging (2021-02-11
> 19:57:50 +)
>
> are available in the Git reposit
Hi Alessandro!
On 2/8/21 6:46 AM, Taylor Simpson wrote:
> From: Alessandro Di Federico
>
> Signed-off-by: Alessandro Di Federico
> Tested-by: Taylor Simpson
> ---
> .../debian-hexagon-cross-build-local.docker| 18 +++
> .../debian-hexagon-cross.build-toolchain.sh| 141
>
On 2/8/21 1:54 PM, Philippe Mathieu-Daudé wrote:
> On 2/8/21 1:50 PM, Claudio Fontana wrote:
>> On 2/5/21 9:14 PM, Richard Henderson wrote:
>>> On 2/4/21 6:39 AM, Claudio Fontana wrote:
@@ -6725,10 +6722,8 @@ static void x86_cpu_initfn(Object *obj)
x86_cpu_load_model(cpu, xcc->mo
Add a very quick test that runs a busybox binary in bFLT format:
$ avocado --show=app run -t linux_user tests/acceptance/load_bflt.py
JOB ID : db94d5960ce564c50904d666a7e259148c27e88f
JOB LOG: ~/avocado/job-results/job-2019-06-25T10.52-db94d59/job.log
(1/1) tests/acceptance/load_b
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c)
> +{
> +uint64_t tmpa, tmpb, tmpc;
> +tmpa = fGETUWORD(0, a);
> +tmpb = fGETUWORD(0, b);
> +tmpc = tmpa + tmpb + c;
> +tmpa = fGETUWORD(1, a);
> +tmpb = fGETUWORD(1, b);
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +uint64_t conv_sf_to_8u(float32 in, float_status *fp_status);
> +uint32_t conv_sf_to_4u(float32 in, float_status *fp_status);
> +int64_t conv_sf_to_8s(float32 in, float_status *fp_status);
> +int32_t conv_sf_to_4s(float32 in, float_status *fp_status);
> +
On 2/11/21 1:50 PM, Alessandro Di Federico via wrote:
> From: Alessandro Di Federico
>
> This patchset introduces the idef-parser for target/hexagon.
> It is based on "[PATCH v8 00/35] Hexagon patch series".
>
> `idef-parser` is a build-time tool built using flex and bison. Its aim
> is to gener
From: Klaus Jensen
A Write Zeroes commands should not be counted in either the 'Data Units
Written' or in 'Host Write Commands' SMART/Health Information Log page.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/block
From: Klaus Jensen
The PRP and SGL mapping functions does not have any particular need for
the entire NvmeRequest as a parameter. Clean it up.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 61 ++-
hw/block/trace-events | 4 +--
2 files changed
From: Klaus Jensen
This is RFC v3 of a series that adds support for metadata and end-to-end data
protection.
First, on the subject of metadata, in v1, support was restricted to
extended logical blocks, which was pretty trivial to implement, but
required special initialization and broke DULBE. In
From: Klaus Jensen
The 'len' member of the nvme_compare_ctx struct is redundant since the
same information is available in the 'iov' member.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw
From: Klaus Jensen
Fix missing sign inversion.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6ed5fbf5426d..d73dac413d4e 100644
--- a/hw/block/nvme.c
+++ b/hw/bl
From: Klaus Jensen
The nvme_dma function doesn't just do DMA (QEMUSGList-based) memory transfers;
it also handles QEMUIOVector copies.
Introduce the NvmeTxDirection enum and rename to nvme_tx. Remove mapping
of PRPs/SGLs from nvme_tx and instead assert that they have been mapped
previously. This
From: Klaus Jensen
Add support for metadata in the form of extended logical blocks as well
as a separate buffer of data. The new `ms` nvme-ns device parameter
specifies the size of metadata per logical block in bytes. The `mset`
nvme-ns device parameter controls whether metadata is transfered as
From: Minwoo Im
This patch introduces multiple LBA formats supported with the typical
logical block sizes of 512 bytes and 4096 bytes as well as metadata
sizes of 0, 8, 16 and 64 bytes. The format will be chosed based on the
lbads and ms parameters of the nvme-ns device.
Signed-off-by: Minwoo Im
From: Klaus Jensen
Add support for namespaces formatted with protection information. The
type of end-to-end data protection (i.e. Type 1, Type 2 or Type 3) is
selected with the `pi` nvme-ns device parameter. If the number of
metadata bytes is larger than 8, the `pil` nvme-ns device parameter may
From: Klaus Jensen
Introduce NvmeSg and try to deal with that pesky qsg/iov duality that
haunts all the memory-related functions.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 17 -
hw/block/nvme.c | 191 ++--
2 files changed, 117 insertions
From: Minwoo Im
Format NVM admin command can make a namespace or namespaces to be
with different LBA size and metadata size with protection information
types.
This patch introduces Format NVM command with LBA format, Metadata, and
Protection Information for the device. The secure erase operation
From: Klaus Jensen
Verify is not subject to MDTS, so a single Verify command may result in
excessive amounts of allocated memory. Impose a limit on the data size
by adding support for TP 4040 ("Non-MDTS Command Size Limits").
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 1 +
include
From: Gollu Appalanaidu
See NVM Express 1.4, section 6.14 ("Verify Command").
Signed-off-by: Gollu Appalanaidu
[k.jensen: rebased, refactored for e2e]
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 1 +
include/block/nvme.h | 2 +
hw/block/nvme.c | 148
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Python scripts generate the following files
> helper_protos_generated.h.inc
> For each instruction we create DEF_HELPER function prototype
> helper_funcs_generated.c.inc
> For each instruction we create the helper function definitio
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> Run the C preprocessor across the instruction definition and encoding
> files to expand macros and prepare the iset.py file. The resulting
> fill contains python data structures used to build the decode tree.
>
> Signed-off-by: Taylor Simpson
> Reviewed
On 2/7/21 9:46 PM, Taylor Simpson wrote:
> +#define DF_NAN 0xULL
> +#define DF_INF 0x7ff0ULL
> +#define DF_MINUS_INF 0xfff0ULL
> +#define DF_MAXF0x7fefULL
> +#define DF_MINUS_MAXF 0xffefULL
...
> +#define SF_
1 - 100 of 122 matches
Mail list logo
