We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/translate.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index f47b5f2c8d0..2a1d8f570bb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int
sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
extern TCGv bcond;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a5cf1742a8b..be40f79229f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,7 +2179,7 @@ enum {
/* global register indices */
TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
+TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
--
2.26.2
