On 2020/12/31 5:22, Michael S. Tsirkin wrote:
> On Tue, Dec 29, 2020 at 02:41:42PM +0100, Igor Mammedov wrote:
>> On Wed, 23 Dec 2020 17:08:31 +0800
>> Jiahui Cen wrote:
>>
>>> There may be some differences in pci resource assignment between guest os
>>> and firmware.
>>>
>>> Eg. A Bridge with
Hi Eduardo,
On 2020/12/25 2:06, Eduardo Habkost wrote:
>>
>> The most time-consuming operation in haxm is ioctl(HAX_VM_IOCTL_VCPU_CREATE).
>> Saddly this can not be split.
>>
>> Even if we fix the problem in haxm, other accelerators may also have
>> this problem. So I think if we can make the x86
On 12/30/20 11:16 PM, Chris Hofstaedtler wrote:
> Cocoa support was always shown as "no", even it if was enabled.
>
> Fixes: b4e312e953b ("configure: move cocoa option to Meson")
> Cc: Paolo Bonzini
> Cc: Peter Maydell
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Chris Hofstaedtler
> ---
> m
On 12/17/20 6:28 AM, Bin Meng wrote:
> From: Bin Meng
>
> For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
>
> 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second
> word.
> 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second
v2 of https://patchew.org/QEMU/cover.1608937677.git.bala...@eik.bme.hu/
with added Tested-by from Guenter and revised patch 2 as suggested by
Philippe.
Regards,
BALATON Zoltan
BALATON Zoltan (3):
ppc4xx: Move common dependency on serial to common option
sam460ex: Remove FDT_PPC dependency fro
All machines that select SERIAL also select PPC4XX so we can just add
this common dependency there once.
Signed-off-by: BALATON Zoltan
---
hw/ppc/Kconfig | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index dd86e664d2..8548f42b0d 100644
--
Avoid mapping multiple interrupts to the same irq. Instead map them to
the 4 PCI interrupts and use an or-gate in the board to connect them
to the interrupt controller. This does not fix any known problem but
does not seem to cause a new problem either and may be cleaner at least.
Signed-off-by: B
Dependency on FDT_PPC was added in commit b0048f76095
("hw/ppc/Kconfig: Only select FDT helper for machines using it") but
it does not seem to be really necessary so remove it again.
Signed-off-by: BALATON Zoltan
---
v2: Do not remove PPC405, reworded commit message
hw/ppc/Kconfig | 1 -
1 file
From: Bin Meng
This updates the flash information table to include various ISSI
flashes that are supported by upstream U-Boot and Linux kernel.
Signed-off-by: Bin Meng
---
hw/block/m25p80.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.
From: Bin Meng
This adds the missing SPI support to the `sifive_u` machine in the QEMU
mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU `sifive_u` out of the box. This allows users to
develop and test the recommended RISC-V boot flow with a real w
From: Bin Meng
After the card is put into SPI mode, CRC check for all commands
including CMD0 will be done according to CMD59 setting. But this
command is currently unimplemented. Simply allow the decoding of
CMD59, but the CRC check is still ignored.
Signed-off-by: Bin Meng
---
hw/sd/sd.c |
From: Bin Meng
This adds the ISSI SPI flash support. The number of dummy cycles in
fast read, fast read dual output and fast read quad output commands
is currently using the default 8. Per the datasheet [1], the number
of dummy cycles configurable, but this is not modeled.
For flash whose size i
From: Bin Meng
Import CRC16 calculation routines from Linux kernel v5.10:
include/linux/crc-ccitt.h
lib/crc-ccitt.c
to QEMU:
include/qemu/crc-ccitt.h
util/crc-ccitt.c
Signed-off-by: Bin Meng
---
include/qemu/crc-ccitt.h | 33 ++
util/crc-ccitt.c | 127 +
From: Bin Meng
Per the "Physical Layer Specification Version 8.00" chapter 7.5.1,
"Command/Response", there is a minimum 8 clock cycles (Ncr) before
the card response shows up on the data out line. However current
implementation jumps directly to the sending response state after
all 6 bytes comma
From: Bin Meng
This adds the SiFive SPI controller model for the FU540 SoC.
The direct memory-mapped SPI flash mode is unsupported.
Signed-off-by: Bin Meng
---
include/hw/ssi/sifive_spi.h | 47 ++
hw/ssi/sifive_spi.c | 290
hw/ssi/Kconfig
From: Bin Meng
commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()")
changed the 16-bit CRC to be stored at offset 64. In fact, this CRC
calculation is completely wrong. From the original codes, it wants
to calculate the CRC16 of the first 64 bytes of sd->data[], however
pa
From: Bin Meng
At present the codes use hardcoded numbers (0xff/0xfe) for the dummy
value and block start token. Replace them with macros, and add more
tokens for multiple block write.
Signed-off-by: Bin Meng
---
hw/sd/ssi-sd.c | 30 +-
1 file changed, 21 insertion
From: Bin Meng
Per the SD spec, a valid data block is suffixed with a 16-bit CRC
generated by the standard CCITT polynomial x16+x12+x5+1. This part
is currently missing in the ssi-sd state machine. Without it, all
data block transfer fails in guest software because the expected
CRC16 is missing o
From: Bin Meng
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng
---
include/hw/riscv/sifive_u.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/s
From: Bin Meng
In the case of a multiple block read operation every transfered
block has its suffix of CRC16. Update the state machine logic to
handle multiple block read.
This also fixed the wrong command index for STOP_TRANSMISSION,
the required command to interupt the multiple block read comm
From: Bin Meng
At present the single/multiple block write in SPI mode is blocked
by sd_normal_command(). Remove the limitation.
Signed-off-by: Bin Meng
---
hw/sd/sd.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 1ada616e1e..67e5f7c05d 100644
--- a/hw/sd/
From: Bin Meng
This adds detailed documentation for RISC-V `sifive_u` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Machine-specific options
- Running Linux kernel
- Running VxWorks kernel
- Running U-Boot, and with an alt
From: Bin Meng
The single block read (CMD17) codes are the same as the multiple
block read (CMD18). Merge them into one. The same applies to single
block write (CMD24) and multiple block write (CMD25).
Signed-off-by: Bin Meng
---
hw/sd/sd.c | 47 ---
From: Bin Meng
Add 2 more states for the block write operation. The SPI host needs
to send a data start tocken to start the transfer, and the data block
written to the card will be acknowledged by a data response tocken.
Signed-off-by: Bin Meng
---
hw/sd/ssi-sd.c | 37
From: Bin Meng
At present there is a data_ready() callback for the SD data read
path. Let's add a receive_ready() for the SD data write path.
Signed-off-by: Bin Meng
---
include/hw/sd/sd.h | 2 ++
hw/sd/core.c | 13 +
hw/sd/sd.c | 6 ++
3 files changed, 21 inse
From: Bin Meng
This adds the QSPI2 controller to the SoC, and connnects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
From: Bin Meng
QEMU conding convention prefers spaces over tabs.
Signed-off-by: Bin Meng
---
include/hw/sd/sd.h | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index 59d108d453..05ef9b73e5
From: Bin Meng
For a multiple block write operation, each block begins with a multi
write start token. Unlike the SD mode that the multiple block write
ends when receiving a STOP_TRAN command (CMD12), a special stop tran
tocken is used to signal the card.
Emulating this by manually sending a CMD
Hello,
I've just sent this but my messages to you are bouncing with:
: Host or domain name not found. Name service
error for name=gibson.dropbear.id.au type=MX: Host not found, try again
after trying for a week so you may have missed it even though I've cc'd
you.
I've also noticed that m
From: Bin Meng
Signed-off-by: Bin Meng
---
docs/system/targets.rst | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 560783644d..564cea9a9b 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targ
From: Bin Meng
This adds the QSPI0 controller to the SoC, and connnects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.
With this commit, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU 'sifive_u' out of the box. This
From: Bin Meng
Add RISC-V system emulator documentation for generic information.
`Board-specific documentation` and `RISC-V CPU features` are only
a placeholder and will be added in the future.
Signed-off-by: Bin Meng
---
docs/system/target-riscv.rst | 62
During migrations, after each iteration, cpu_throttle_set() is called,
which irrespective of input, re-arms the timer according to value of
new_throttle_pct. This causes cpu_throttle_thread() to be delayed in
getting scheduled and consqeuntly lets guest run for more time than what
the throttle valu
On Fri, 18 Dec 2020 at 08:27, Thomas Huth wrote:
>
> Hi!
>
> The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/x86-next-pull-request'
> into staging (2020-12-17 18:53:36 +)
>
> are available in the Gi
On Wed, 16 Dec 2020 at 16:09, Stefan Hajnoczi wrote:
>
> The "simple" backend is actually more complicated to use than the "log"
> backend. Update the quickstart documentation to feature the "log"
> backend instead of the "simple" backend.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Stefan H
On Wed, Dec 30, 2020 at 2:17 PM Chris Hofstaedtler
wrote:
>
> Without this, meson fails with "curses package not usable" when using
ncurses
> 6.2. Apparently the wide functions (addwstr, etc) are hidden behind the
extra
> define, and meson does not define it at that detection stage.
>
> Regression
On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan wrote:
>
> Avoid mapping multiple interrupts to the same irq. Instead map them to
> the 4 PCI interrupts and use an or-gate in the board to connect them
> to the interrupt controller. This does not fix any known problem but
> does not seem to cause a ne
On Fri, 25 Dec 2020 at 23:45, BALATON Zoltan via wrote:
> For the Bamboo board we have 4 interrupts connected to the PCI bus in the
> board but also have a comment in ppc4xx_pci.c near the above function
> saying:
>
> /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
> *
On Thu, 31 Dec 2020 at 15:11, Peter Maydell wrote:
>
> On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan wrote:
> >
> > Avoid mapping multiple interrupts to the same irq. Instead map them to
> > the 4 PCI interrupts and use an or-gate in the board to connect them
> > to the interrupt controller. This
On Fri, 18 Dec 2020 at 10:26, Laurent Vivier wrote:
>
> The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f:
>
> Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' int=
> o staging (2020-12-15 21:24:31 +)
>
> are available in the Git repository at
On 12/31/20 12:11 PM, BALATON Zoltan via wrote:
> Dependency on FDT_PPC was added in commit b0048f76095
> ("hw/ppc/Kconfig: Only select FDT helper for machines using it") but
> it does not seem to be really necessary so remove it again.
>
> Signed-off-by: BALATON Zoltan
> ---
> v2: Do not remove
On 12/31/20 1:59 AM, Rémi Denis-Courmont wrote:
> Le jeudi 31 décembre 2020, 00:38:14 EET Richard Henderson a écrit :
>> On 12/30/20 2:10 PM, Richard Henderson wrote:
>>> On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
From: Rémi Denis-Courmont
Signed-off-by: Rémi Denis-C
On 12/31/20 1:55 AM, Rémi Denis-Courmont wrote:
> Le jeudi 31 décembre 2020, 00:10:09 EET Richard Henderson a écrit :
>> On 12/18/20 6:33 AM, remi.denis.courm...@huawei.com wrote:
>>> From: Rémi Denis-Courmont
>>>
>>> Signed-off-by: Rémi Denis-Courmont
>>> ---
>>>
>>> target/arm/helper.c | 14 ++
Public bug reported:
I am on commit 65a3c5984074313602fb5f61cc5f464abfb020c7 (latest as far
as I know). I compiled qemu with --enable-debug.
I'm trying to run a userspace CRIS binary (`./qemu-cris -cpu crisv10
./basic`), but this segfaults. When opening the coredump in gdb, I get
gdb-peda$ bt
#0
** Tags added: linux-user
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1909770
Title:
qemu-cris segfaults upon loading userspace binary
Status in QEMU:
New
Bug description:
I am on commit 65
On Fri, 18 Dec 2020 at 10:41, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17
>
Sounds like it's probably the bug where we don't correctly handle ELF BSS
segments which have no content in the file at all (ie they're just "zero this
memory" with no content). If so, this patch (currently in review) will fix it:
https://patchew.org/QEMU/c9106487-dc4d-120a-bd48-665b3c617...@gmai
That did indeed fix it, thank you!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1909770
Title:
qemu-cris segfaults upon loading userspace binary
Status in QEMU:
New
Bug description:
I am on
On Thu, 31 Dec 2020, Peter Maydell wrote:
On Wed, 16 Dec 2020 at 16:09, Stefan Hajnoczi wrote:
The "simple" backend is actually more complicated to use than the "log"
backend. Update the quickstart documentation to feature the "log"
backend instead of the "simple" backend.
Suggested-by: Peter
On Thu, 31 Dec 2020, Peter Maydell wrote:
On Thu, 31 Dec 2020 at 15:11, Peter Maydell wrote:
On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan wrote:
Avoid mapping multiple interrupts to the same irq. Instead map them to
the 4 PCI interrupts and use an or-gate in the board to connect them
to the
On Thu, 31 Dec 2020, BALATON Zoltan via wrote:
On Thu, 31 Dec 2020, Peter Maydell wrote:
On Thu, 31 Dec 2020 at 15:11, Peter Maydell
wrote:
On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan wrote:
Avoid mapping multiple interrupts to the same irq. Instead map them to
the 4 PCI interrupts and use
Patches I wrote while reviewing/testing Jiaxun's v3 [1] trying
to understand the problem with "Fixup pci.lomem mapping" [2].
The issue should be fixed by patch #8 of this series:
'Remap PCI "lo" regions when PCIMAP reg is modified'.
The rest are cleanups patches.
Happy new year,
Phil.
[1] https
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index a99eced0657..0634f3289c4 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -189,12 +189,6 @@ FIELD(BONGENCFG, PCI
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 0634f3289c4..efeba29011f 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -463,8 +463,8 @@ static
Use the PCI_DEVFN() macro to replace the '0x28' magic value,
this way it is clearer we access PCI function #0 of slot #5.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index fe94e6740b5..104c58331d0 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -244,7 +244,6 @@
Replace pci_set_byte(PCI_INTERRUPT_PIN) by
pci_config_set_interrupt_pin().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 4c903d4f682..fe94e6740b5 100644
--- a/
This model is not complete for big-endian targets,
do not allow its use.
Signed-off-by: Philippe Mathieu-Daudé
---
Yes I must improve that, I know =) However enough for now
to post the following patches.
---
hw/pci-host/bonito.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --g
Per the datasheet (Chapter 5.2. "Power-on settable configuration
register - bonponcfg"), the bonponcfg can only be modified using
"pull-up on the corresponding IOD0-15 signal". Do not allow
update of this register by the CPU.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 2 +-
Rename PCI host side related helpers as 'bonito_host_*'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index d91ed82c99e..45f31512b25 100644
--- a/h
Per the datasheet (Chapter 5.7.1. "PCI address regions"),
the PCIMAP register:
Map the 64Mbyte regions marked "PCI_Lo" in the CPU's memory map,
each of which can be assigned to any 64 Mbyte-aligned region of
PCI memory. The address appearing on the PCI bus consists of the
low 26 bits of th
As it doesn't make sens to create the TYPE_BONITO_PCI_HOST_BRIDGE
PCI function device without its host side, create it in the host
realize(). This will allow to inline bonito_init() in few commits.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 14 ++
1 file changed
Rename north bridge related helpers as 'bonito_northbridge_*'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index a091ef15d27..d91ed82c99e 100644
--- a/h
Rename PCI function related helpers as 'bonito_pci_*'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 45f31512b25..06f5e683c81 100644
--- a/hw/pci-ho
As we use BonitoState for the whole device, rename
the PCI function device as BonitoPciState.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/pci-host/bonito.c b/h
Remove bonito_init() by inlining it.
Signed-off-by: Philippe Mathieu-Daudé
---
TBC next year.
---
include/hw/mips/mips.h | 3 ---
hw/mips/fuloong2e.c| 7 ++-
hw/pci-host/bonito.c | 15 ---
3 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/include/hw/mips/mip
The PCI regions belong to the 'host' device, not the PCI function.
Move the PCI regions creation there.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonit
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 35 +--
1 file changed, 1 insertion(+), 34 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 4dcaa2fa8bb..c09d54cca82 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bon
Declare TYPE_BONITO_PCI_HOST_BRIDGE in the new "hw/pci-host/bonito.h"
header, so we can inline the bonito_init() call in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci-host/bonito.h | 34 ++
hw/pci-host/bonito.c | 16 +---
The 'north bridge' is not part of the PCI function,
so create and map it in bonito_host_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonit
On Fri, 18 Dec 2020 at 12:10, Kevin Wolf wrote:
>
> The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17
> 18:53:36 +)
>
> are available in the Git repositor
71 matches
Mail list logo
