On Thu, 31 Dec 2020 at 15:11, Peter Maydell <peter.mayd...@linaro.org> wrote: > > On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan <bala...@eik.bme.hu> wrote: > > > > Avoid mapping multiple interrupts to the same irq. Instead map them to > > the 4 PCI interrupts and use an or-gate in the board to connect them > > to the interrupt controller. This does not fix any known problem but > > does not seem to cause a new problem either and may be cleaner at least. > > > > Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu> > > Tested-by: Guenter Roeck <li...@roeck-us.net> > > So, this patch is a behavioural change, but I think it's > probably a change to the right behaviour. The difference > is relatively slight, but you would see it if there are two > different PCI cards and they both assert a different PCI > interrupt, and then one of them lowers the interrupt > before the other:
This turns out to be wrong -- I hadn't looked at the QEMU PCI code, but it has an internal implementation of logic that gives the same behaviour as an explicit OR gate. Basically pci_change_irq_level() tracks how many assert/deasserts of the (mapped) IRQ lines have happened, so it only calls the controller's set_irq function when the count of asserted inputs goes down to 0. So both the current code and this patch's change are functionally correct. I'm not sure which would be nominally closer to the "real hardware": the 440ex CPU/SoC datasheet lists a single PCI0INT signal, but it says it is an output, not an input, so I'm pretty sure there's something I don't understand about PCI here. (Also, unlike the 440EP it provides PCI Express as well as PCI.) thanks -- PMM
