On Mon, Oct 19, 2020 at 03:18:11PM +0100, Peter Maydell wrote:
> On Mon, 19 Oct 2020 at 14:40, Andrew Jones wrote:
> >
> > On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> > > Well, ID regs are special in the architecture -- they always exist
> > > and must RAZ/WI, even if they're
For nested groups like:
{
[
pattern 1
pattern 2
]
pattern 3
}
the intended behaviour is that patterns 1 and 2 must not
overlap with each other; if the insn matches neither then
we fall through to pattern 3 as the next thing in the
outer overlapping group.
Currently we
On 10/15/20 7:32 AM, Claudio Fontana wrote:
> Claudio Fontana (3):
> accel/tcg: split CpusAccel into three TCG variants
> accel/tcg: split tcg_start_vcpu_thread
> accel/tcg: rename tcg-cpus functions to match module name
Reviewed-by: Richard Henderson
r~
v8.1M implements a new 'branch future' feature, which is a
set of instructions that request the CPU to perform a branch
"in the future", when it reaches a particular execution address.
In hardware, the expected implementation is that the information
about the branch location and destination is cach
The BLX immediate insn in the Thumb encoding always performs
a switch from Thumb to Arm state. This would be totally useless
in M-profile which has no Arm decoder, and so the instruction
does not exist at all there. Make the encoding UNDEF for M-profile.
(This part of the encoding space is used fo
v8.1M's "low-overhead-loop" extension has three instructions
for looping:
* DLS (start of a do-loop)
* WLS (start of a while-loop)
* LE (end of a loop)
The loop-start instructions are both simple operations to start a
loop whose iteration count (if any) is in LR. The loop-end
instruction handl
This patchseries implements various minor v8.1M new features,
notably the branch-future and low-overhead-loop extensions.
(None of this will get enabled until we have enough to implement
a CPU model which has v8.1M, which will be the Cortex-M55, but
as usual we can get stuff into the tree graduall
>From v8.1M, disabled-coprocessor handling changes slightly:
* coprocessors 8, 9, 14 and 15 are also governed by the
cp10 enable bit, like cp11
* an extra range of instruction patterns is considered
to be inside the coprocessor space
We previously marked these up with TODO comments; implem
v8.1M brings four new insns to M-profile:
* CSEL : Rd = cond ? Rn : Rm
* CSINC : Rd = cond ? Rn : Rm+1
* CSINV : Rd = cond ? Rn : ~Rm
* CSNEG : Rd = cond ? Rn : -Rm
Implement these.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/t32.decode | 3 +++
target/arm
M-profile CPUs with half-precision floating point support should
be able to write to FPSCR.FZ16, but an M-profile specific masking
of the value at the top of vfp_set_fpscr() currently prevents that.
This is not yet an active bug because we have no M-profile
FP16 CPUs, but needs to be fixed before w
The t32 decode has a group which represents a set of insns
which overlap with B_cond_thumb because they have [25:23]=111
(which is an invalid condition code field for the branch insn).
This group is currently defined using the {} overlap-OK syntax,
but it is almost entirely non-overlapping patterns
On Mon, Oct 19, 2020 at 03:58:40PM +0100, Dave Martin wrote:
> On Mon, Oct 19, 2020 at 03:18:11PM +0100, Peter Maydell wrote:
> > On Mon, 19 Oct 2020 at 14:40, Andrew Jones wrote:
> > >
> > > On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> > > > Well, ID regs are special in the ar
On Wed, 14 Oct 2020 at 22:36, Philippe Mathieu-Daudé wrote:
>
> The time to transmit a char is expressed in nanoseconds, not in ticks.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/strongarm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/strongarm.c
If the M-profile low-overhead-branch extension is implemented, FPSCR
bits [18:16] are a new field LTPSIZE. If MVE is not implemented
(currently always true for us) then this field always reads as 4 and
ignores writes.
These bits used to be the vector-length field for the old
short-vector extensio
On Thu, 8 Oct 2020 at 17:14, Philippe Mathieu-Daudé wrote:
>
> While APEI is a generic ACPI feature (usable by X86 and ARM64), only
> the 'virt' machine uses it, by enabling the RAS Virtualization. See
> commit 2afa8c8519: "hw/arm/virt: Introduce a RAS machine option").
>
> Restrict the APEI table
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
squash the ID register fields so that we don't advertise it to the
guest. This code was written for A-profile and needs some tweaks to
work correctly on M-profile:
* A-profile only fields should not be zeroed on M-profile:
-
t; git log -1
commit ba2a9a9e6318bfd93a2306dec40137e198205b86 (HEAD -> master,
origin/master, origin/HEAD)
Merge: 22d30b340a bb997e5c96
Author: Peter Maydell
Date: Mon Oct 19 11:46:03 2020 +0100
Merge remote-tracking branch
'remotes/mcayland/tags/qemu-macppc-20201019' into
On 10/5/20 9:56 PM, Luc Michel wrote:
Those reset values have been extracted from a Raspberry Pi 3 model B
v1.2, using the 2020-08-20 version of raspios. The dump was done using
the debugfs interface of the CPRMAN driver in Linux (under
'/sys/kernel/debug/clk'). Each exposed clock tree stage (PLL
On 10/19/20 8:12 AM, Peter Maydell wrote:
> v8.1M's "low-overhead-loop" extension has three instructions
> for looping:
> * DLS (start of a do-loop)
> * WLS (start of a while-loop)
> * LE (end of a loop)
>
> The loop-start instructions are both simple operations to start a
> loop whose iteratio
On 10/16/20 7:10 PM, Philippe Mathieu-Daudé wrote:
On 10/11/20 8:26 PM, Luc Michel wrote:
On 18:18 Sat 10 Oct , Philippe Mathieu-Daudé wrote:
On 10/10/20 3:57 PM, Luc Michel wrote:
Those reset values have been extracted from a Raspberry Pi 3 model B
v1.2, using the 2020-08-20 version of ra
Kevin Wolf writes:
> Am 16.10.2020 um 19:10 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> Now bdrv_append returns status and we can drop all the local_err things
>> around it.
>>
>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>> Reviewed-by: Greg Kurz
>> Reviewed-by: Alberto Garcia
>> ---
On Sat, 10 Oct 2020 at 14:57, Luc Michel wrote:
>
> v2 -> v3:
> - patch 03: moved clock_new definition to hw/core/clock.c [Phil]
> - patch 03: commit message typo [Clement]
> - patch 10: clarifications around the CM_CTL/CM_DIBV mux registers.
> reg_cm replaced with reg_ctl and
On Sat, 10 Oct 2020 at 21:37, Philippe Mathieu-Daudé wrote:
>
> In this series we implement the COMPARE registers of the
> SYS_timer, since they are used by Linux.
>
> This fixes the hang reported by Niek here:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg682090.html
>
Applied to targ
On Fri, 16 Oct 2020 at 22:07, Richard Henderson
wrote:
>
> Since the FAR_ELx fix at 38d931687fa1, it is reported that
> page granularity flushing is broken.
>
> This makes sense, since TCG will record the entire virtual
> address in its TLB, not simply the 56 significant bits.
> With no other TCG
Cc'ing Markus/John/Paolo
On 10/19/20 5:33 PM, Emmanuel Blot wrote:
Hi,
I’m using the current master (ba2a9a9e)
I tried to build with both ‘ninja’ and also with ‘make’, as I’m not sure
of the current status of the meson refactoring.
The build fails with a weird error message:
ld: file not fo
On Mon, 19 Oct 2020 at 12:26, Philippe Mathieu-Daudé wrote:
>
> bcm2835_cprman_internals.h is only include by bcm2835_cprman.c
> and contains various static array definitions. Make it an
> included source file (using the .c.inc extension).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> I'm sen
On 10/19/20 5:53 PM, Peter Maydell wrote:
On Mon, 19 Oct 2020 at 12:26, Philippe Mathieu-Daudé wrote:
bcm2835_cprman_internals.h is only include by bcm2835_cprman.c
and contains various static array definitions. Make it an
included source file (using the .c.inc extension).
Signed-off-by: Phil
On Oct 19 11:50, Klaus Jensen wrote:
> On Oct 19 11:17, Dmitry Fomichev wrote:
> > +static bool nvme_finalize_zoned_write(NvmeNamespace *ns, NvmeRequest *req,
> > + bool failed)
> > +{
> > +NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
> > +NvmeZone *zone;
> >
On Tue 06 Oct 2020 11:10:01 AM CEST, Kashyap Chamarthy wrote:
> Hi, folks
>
> If this was already discussed on the list, please point me to the
> thread. I took a quick look at my local archives, I didn't find any,
> besides patches to tests.
I think this is the last time that I was discussed:
On 10/9/20 1:21 AM, Havard Skinnemoen via wrote:
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
Signed-off-by: Havard Skinnemoen
---
hw/timer/npcm7xx_timer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, Oct 9, 2020 at 5:55 PM Cleber Rosa wrote:
>
> On with certain versions of "pip", package installations will attempt
> to create wheels. And, on environments without a "complete" Python
> installation (as described in the acceptance tests requirements docs),
> that will fail.
>
> pycdlib,
On 10/19/20 8:13 AM, Peter Maydell wrote:
> M-profile CPUs with half-precision floating point support should
> be able to write to FPSCR.FZ16, but an M-profile specific masking
> of the value at the top of vfp_set_fpscr() currently prevents that.
> This is not yet an active bug because we have no M
Ping for review?
On 10/12/20 2:49 PM, Philippe Mathieu-Daudé wrote:
Since v1:
- Fixed patch #1 subject (Kevin)
In order to use inclusive terminology, rename SSI 'slave' as
'peripheral', following the resolution Paolo pointed in [*]:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-name
On 10/19/20 8:13 AM, Peter Maydell wrote:
> If the M-profile low-overhead-branch extension is implemented, FPSCR
> bits [18:16] are a new field LTPSIZE. If MVE is not implemented
> (currently always true for us) then this field always reads as 4 and
> ignores writes.
>
> These bits used to be the
On 10/19/20 8:12 AM, Peter Maydell wrote:
> From v8.1M, disabled-coprocessor handling changes slightly:
> * coprocessors 8, 9, 14 and 15 are also governed by the
>cp10 enable bit, like cp11
> * an extra range of instruction patterns is considered
>to be inside the coprocessor space
>
> W
On 10/19/20 6:02 AM, Daniel P. Berrangé wrote:
On Mon, Oct 19, 2020 at 11:45:09AM +0200, Andrea Bolognani wrote:
On Wed, 2020-10-14 at 10:29 -0400, John Snow wrote:
Python infrastructure as it exists today is not capable reliably of
single-sourcing a package version from a parent directory. The
On Tue, 15 Sep 2020 at 18:52, Philippe Mathieu-Daudé wrote:
>
> This is the QEMU equivalent of this Linux commit (but 7 years later):
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f7025a43a9da2
>
> The MTD subsystem has its own small museum of ancient NANDs
>
On 19/10/2020 11.51, Philippe Mathieu-Daudé wrote:
> Commit 7998beb9c2e removed the ram_size initialization in the
> arm_boot_info structure, however it is used by arm_load_kernel().
>
> Initialize the field to fix:
>
> $ qemu-system-arm -M n800 -append 'console=ttyS1' \
> -kernel meego-arm
Am 19.10.2020 um 17:45 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 16.10.2020 um 19:10 hat Vladimir Sementsov-Ogievskiy geschrieben:
> >> Now bdrv_append returns status and we can drop all the local_err things
> >> around it.
> >>
> >> Signed-off-by: Vladimir Sementsov-Ogiev
On Mon, 19 Oct 2020, Mark Cave-Ayland wrote:
On 19/10/2020 15:00, Markus Armbruster wrote:
BALATON Zoltan via writes:
On Mon, 19 Oct 2020, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 10/12/20 1:50 PM, BALATON Zoltan via wrote:
On Mon, 12 Oct 2020, David Gibson wrote:
On Mon
On Mon, Oct 12, 2020 at 12:35 AM Cleber Rosa wrote:
>
> When parsing the topology, the right default value of 1 is given to
> dies, but if an invalid number such as 0 is given, QEMU will crash
> with a floating point exception.
>
> The alternative approach is to silently set dies to a valid value,
On 10/15/2020 4:36 PM, Alex Williamson wrote:
> On Thu, 8 Oct 2020 12:32:35 -0400
> Steven Sistare wrote:
>> On 8/24/2020 6:30 PM, Alex Williamson wrote:
>>> On Wed, 19 Aug 2020 17:52:26 -0400
>>> Steven Sistare wrote:
On 8/17/2020 10:42 PM, Alex Williamson wrote:
> On Mon, 17 Aug 20
On Mon, Oct 19, 2020 at 01:30:39PM +0200, Klaus Jensen wrote:
> @@ -328,7 +328,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1,
> uint64_t prp2,
> trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
>
> if (unlikely(!prp1)) {
> -trace_pci_nvme_err_invalid
On Mon, Oct 19, 2020 at 05:23:11PM +0200, Andrew Jones wrote:
> On Mon, Oct 19, 2020 at 03:58:40PM +0100, Dave Martin wrote:
> > On Mon, Oct 19, 2020 at 03:18:11PM +0100, Peter Maydell wrote:
> > > On Mon, 19 Oct 2020 at 14:40, Andrew Jones wrote:
> > > >
> > > > On Mon, Oct 19, 2020 at 12:43:33PM
Signed-off-by: Maxim Levitsky
---
include/hw/qdev-core.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 868973319e..3761186804 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -163,8 +163,8 @@ struct
By a mistake I added the pending events in a wrong order.
Fix this by using g_list_append.
Signed-off-by: Maxim Levitsky
---
tests/qtest/libqtest.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
index 08929f5ff6..bd96cb6fdd 100
Just few fixes, for some stuff that slipped thorough.
Tested with make check, and qcow2/raw/nbd iotests.
Best regards,
Maxim Levitsky
Maxim Levitsky (4):
qdev: Fix two typos
libqtest: fix the order of buffered events
libqtest: fix memory leak in the qtest_qmp_event_ref
iotests: r
The g_list_remove_link doesn't free the link element,
opposed to what I thought.
Switch to g_list_delete_link that does free it.
Also refactor the code a bit.
Thanks for Max Reitz for helping me with this.
Signed-off-by: Maxim Levitsky
---
tests/qtest/libqtest.c | 11 ---
1 file changed
The recent changes that brought RCU delayed device deletion,
broke few tests and this test breakage went unnoticed.
Fix this test by rewriting it in python
(which allows to wait for DEVICE_DELETED events before continuing).
Signed-off-by: Maxim Levitsky
---
tests/qemu-iotests/240 | 228
On 19 Oct 2020, at 17:50, Philippe Mathieu-Daudé wrote:
Cc'ing Markus/John/Paolo
I never used `git bisect` up to now, so I might be wronb but it seems
the issue would have been introduced with the following commit:
604f3e4e90c011a6b94fdc1d13700f3ec2375f2a is the first bad commit
commit 604f
On Mon 19 Oct 2020 05:56:56 PM CEST, Alberto Garcia wrote:
> And this one in particular:
>
>https://lists.gnu.org/archive/html/qemu-block/2020-02/msg00601.html
I forgot to add, we still don't support changing bs->file with this
command, so I guess that would be one blocker?
There's no other w
On Mon, Oct 19, 2020 at 08:54:16AM +0200, Klaus Jensen wrote:
> @@ -844,6 +838,12 @@ static void nvme_enqueue_event(NvmeCtrl *n, uint8_t
> event_type,
> return;
> }
>
> +/* ignore if masked (cqe posted, but event not cleared) */
> +if (n->aer_mask & (1 << event_type)) {
> +
On Mon, Oct 19, 2020 at 12:46:08PM -0400, Eduardo Habkost wrote:
> On Thu, Oct 15, 2020 at 10:37:13AM -0400, to...@linux.ibm.com wrote:
> [...]
> > diff --git a/target/i386/sev-stub.c b/target/i386/sev-stub.c
> > index 88e3f39a1e..2d2ee54cc6 100644
> > --- a/target/i386/sev-stub.c
> > +++ b/target/
Eduardo Habkost writes:
> On Mon, Oct 19, 2020 at 09:55:20AM +0200, Markus Armbruster wrote:
>> Eduardo Habkost writes:
>>
>> > On Mon, Oct 12, 2020 at 02:15:31PM +0200, Philippe Mathieu-Daudé wrote:
>> >> Reduce the machine code pulled into qemu-storage-daemon.
>> >>
>> >> The series is fully
On Thu, Oct 15, 2020 at 10:37:13AM -0400, to...@linux.ibm.com wrote:
[...]
> diff --git a/target/i386/sev-stub.c b/target/i386/sev-stub.c
> index 88e3f39a1e..2d2ee54cc6 100644
> --- a/target/i386/sev-stub.c
> +++ b/target/i386/sev-stub.c
> @@ -49,3 +49,8 @@ SevCapability *sev_get_capabilities(Error
- On Oct 17, 2020, at 2:10 PM, Andy Lutomirski l...@kernel.org wrote:
> On Fri, Oct 16, 2020 at 6:40 PM Jann Horn wrote:
>>
>> [adding some more people who are interested in RNG stuff: Andy, Jason,
>> Theodore, Willy Tarreau, Eric Biggers. also linux-api@, because this
>> concerns some pretty
On 19/10/20 18:40, Emmanuel Blot wrote:
> On 19 Oct 2020, at 17:50, Philippe Mathieu-Daudé wrote:
>
>> Cc'ing Markus/John/Paolo
>
> I never used `git bisect` up to now, so I might be wronb but it seems
> the issue would have been introduced with the following commit:
Hi,
I think this could be t
On 19 Oct 2020, at 18:40, Emmanuel Blot wrote:
On 19 Oct 2020, at 17:50, Philippe Mathieu-Daudé wrote:
Cc'ing Markus/John/Paolo
604f3e4e90c011a6b94fdc1d13700f3ec2375f2a is the first bad commit
commit 604f3e4e90c011a6b94fdc1d13700f3ec2375f2a
Applying the reverse diff to the current master d
Ping
On Mon, Oct 12, 2020 at 1:52 PM Owen Anderson wrote:
>
> Ping.
>
> I'd like to get feedback on how/whether this could be developed into a
> landable version.
>
> Thanks,
>
> --Owen
>
> On Tue, Sep 29, 2020 at 2:32 PM Owen Anderson wrote:
> >
> > Hello,
> >
> > I would like to request feedba
On 19/10/20 19:16, Emmanuel Blot wrote:
> --- undef_sh.log 2020-10-19 19:15:08.0 +0200
> +++ undef_py.log 2020-10-19 19:15:20.0 +0200
> @@ -1,3 +1,4 @@
> +-Wl,-u,
> -Wl,-u,_PreallocMode_lookup
> -Wl,-u,__TRACE_CURL_CLOSE_DSTATE
> -Wl,-u,__TRACE_CURL_OPEN_DSTATE
>
>
> I th
On Mon, 19 Oct 2020 11:31:03 +0530
Kirti Wankhede wrote:
> On 9/26/2020 3:53 AM, Alex Williamson wrote:
> > On Wed, 23 Sep 2020 04:54:15 +0530
> > Kirti Wankhede wrote:
> >
> >> Create mapped iova list when vIOMMU is enabled. For each mapped iova
> >> save translated address. Add node to list
On 19 Oct 2020, at 19:14, Paolo Bonzini wrote:
Sorry, I received your email just after I posted mine.
> I think this could be the fix. The problem would be that
>
> awk '$2=="U"{print "-Wl,-u," $1}'
/
> Great, thanks. Can you check if my patch would also work, as it would
> adhere more
On Oct 19 09:34, Keith Busch wrote:
> On Mon, Oct 19, 2020 at 01:30:39PM +0200, Klaus Jensen wrote:
> > @@ -328,7 +328,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t
> > prp1, uint64_t prp2,
> > trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
> >
> > if (unlikely
From: Gollu Appalanaidu
Address 0 is not an invalid address. Remove those invalikd checks.
Unaligned PRP2 and PRP list entries should result in Invalid PRP Offset
status code and not Invalid Field. Fix that.
See NVMe Express v1.3d, Section 4.3 ("Physical Region Page Entry and
List").
Suggested
Dave magically found this. Fix them with "0x%x".
Reported-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 749eb6ad63..70ac837733 100644
--- a
On Oct 19 09:43, Keith Busch wrote:
> On Mon, Oct 19, 2020 at 08:54:16AM +0200, Klaus Jensen wrote:
> > @@ -844,6 +838,12 @@ static void nvme_enqueue_event(NvmeCtrl *n, uint8_t
> > event_type,
> > return;
> > }
> >
> > +/* ignore if masked (cqe posted, but event not cleared) */
On Sun, 18 Oct 2020 23:13:39 +0530
Kirti Wankhede wrote:
>
>
> +vfio_migration_set_state(char *name, uint32_t state) " (%s) state %d"
> +vfio_vmstate_change(char *name, int running, const char *reason,
> uint32_t dev_state) " (%s) running %d reason %s device state %d"
> dif
On Sun, 18 Oct 2020 02:05:03 +0530
Kirti Wankhede wrote:
> On 9/26/2020 1:50 AM, Alex Williamson wrote:
> > On Wed, 23 Sep 2020 04:54:08 +0530
> > Kirti Wankhede wrote:
> >
> >> Added migration state change notifier to get notification on migration
> >> state
> >> change. These states are tr
On 10/19/20 6:48 PM, Markus Armbruster wrote:
Eduardo Habkost writes:
On Mon, Oct 19, 2020 at 09:55:20AM +0200, Markus Armbruster wrote:
Eduardo Habkost writes:
On Mon, Oct 12, 2020 at 02:15:31PM +0200, Philippe Mathieu-Daudé wrote:
Reduce the machine code pulled into qemu-storage-daemon.
On Mon, Oct 19, 2020 at 07:35:38PM +0200, Klaus Jensen wrote:
> From: Gollu Appalanaidu
>
> Address 0 is not an invalid address. Remove those invalikd checks.
>
> Unaligned PRP2 and PRP list entries should result in Invalid PRP Offset
> status code and not Invalid Field. Fix that.
>
> See NVMe
On 9/29/20 2:32 PM, Owen Anderson wrote:
> Hello,
>
> I would like to request feedback on the following patch, which I do
> not believe should be applied to master as-is. The idea here is to
> avoid gathering the full CPU state in the fast path of an indirect
> branch lookup when running in user
>>> Hi Kevin,
>>>
>>> since commit 9ce44e2ce2 "qmp: Move dispatcher to a coroutine" I see
>>> the following error on Windows whenever I close the QEMU window or
>>> shut down the guest.
>>>
>>> $ ./qemu-system-x86_64.exe -machine pc,accel=tcg -display gtk
>>> **
>>> ERROR:../qemu/util/aio-win32.c:3
On Mon, 19 Oct 2020, P J P wrote:
+-- On Sun, 18 Oct 2020, BALATON Zoltan wrote --+
| The s->regs.[src|dst]_[xy] values should not be over 0x3fff because we mask
| them on register write in ati.c
Yes, those register values are set to zero(0).
| and here [src|dst]_[x|y] local variables are decl
Finally I found what was the issue. in the /etc/ssh/sshd_config after
commenting the below lines I am able to ssh to the vm.
# grep -i LISTEN /etc/ssh/sshd_config
#ListenAddress 127.0.0.1
#ListenAddress ::
#
check your sshd config.
--
You received this bug notification because you are a member
* Peter Xu (pet...@redhat.com) wrote:
> Dave magically found this. Fix them with "0x%x".
>
> Reported-by: Dr. David Alan Gilbert
> Signed-off-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
> ---
> hw/i386/intel_iommu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff
On Mon, 19 Oct 2020 at 18:43, Peter Xu wrote:
>
> Dave magically found this. Fix them with "0x%x".
>
> Reported-by: Dr. David Alan Gilbert
> Signed-off-by: Peter Xu
Hmm, a quick grep finds also some "0x%d" in an arm trace-event file :-)
I'll send a patch...
-- PMM
On 12/10/2020 18:09, Philippe Mathieu-Daudé wrote:
The region is registered as 64KiB in sabre_init():
memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
"sabre-config", 0x1);
Remove the superfluous check.
Signed-off-by: Philippe Mathie
On 12/10/2020 18:09, Philippe Mathieu-Daudé wrote:
The current link redirects to https://www.oracle.com/sun/
announcing "Oracle acquired Sun Microsystems in 2010, ..."
but does not give hint where to find the datasheet.
Use the archived PDF on the Wayback Machine, which works.
Signed-off-by: P
On 12/10/2020 18:09, Philippe Mathieu-Daudé wrote:
We only need to zero-initialize 'val' once.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 0889c
On Fri, 16 Oct 2020 13:42:29 +0200
Paolo Bonzini wrote:
> On 16/10/20 13:29, FelixCuioc wrote:
> > The issue here is that an assinged EHCI device accesses
> > an adjacent mapping between the delete and add phases
> > of the VFIO MemoryListener.
> > We want to skip flatview_simplify() is to preven
The smmuv3_cmdq_cfgi_ste_range trace event prints decimal values with
an 0x prefix, which is confusing. We're printing a range of stream IDs
here, which elsewhere we do in decimal, so use decimal here too and
just drop the '0x' prefix.
Signed-off-by: Peter Maydell
---
hw/arm/trace-events | 2 +-
On 10/13/20 3:25 PM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Add new commands to add and remove SSH public keys from
~/.ssh/authorized_keys.
+++ b/qga/qapi-schema.json
@@ -1306,3 +1306,35 @@
##
{ 'command': 'guest-get-devices',
'returns': ['GuestDeviceInfo'] }
+
+
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Mon, 19 Oct 2020 at 18:43, Peter Xu wrote:
> >
> > Dave magically found this. Fix them with "0x%x".
> >
> > Reported-by: Dr. David Alan Gilbert
> > Signed-off-by: Peter Xu
>
> Hmm, a quick grep finds also some "0x%d" in an arm trace-event
On 10/19/2020 10:54 PM, Alex Williamson wrote:
On Mon, 19 Oct 2020 11:31:03 +0530
Kirti Wankhede wrote:
On 9/26/2020 3:53 AM, Alex Williamson wrote:
On Wed, 23 Sep 2020 04:54:15 +0530
Kirti Wankhede wrote:
Create mapped iova list when vIOMMU is enabled. For each mapped iova
save tran
On Mon, Oct 19, 2020 at 11:17:16AM +0900, Dmitry Fomichev wrote:
> This log page becomes necessary to implement to allow checking for
> Zone Append command support in Zoned Namespace Command Set.
>
> This commit adds the code to report this log page for NVM Command
> Set only. The parts that are s
On Mon, Oct 19, 2020 at 11:17:17AM +0900, Dmitry Fomichev wrote:
> In NVMe 1.4, a namespace must report an ID descriptor of UUID type
> if it doesn't support EUI64 or NGUID. Add a new namespace property,
> "uuid", that provides the user the option to either specify the UUID
> explicitly or have a U
On Wed, 14 Oct 2020 at 20:36, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> Use of 0x%d - make up our mind as 0x%x
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> hw/arm/trace-events | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/t
On 10/8/20 10:49 AM, Daniel P. Berrangé wrote:
The bdrv_all_*_snapshot functions return a BlockDriverState pointer
for the invalid backend, which the callers then use to report an
error message. In some cases multiple callers are reporting the
same error message, but with slightly different text.
On Oct 19 11:17, Dmitry Fomichev wrote:
> In NVMe 1.4, a namespace must report an ID descriptor of UUID type
> if it doesn't support EUI64 or NGUID. Add a new namespace property,
> "uuid", that provides the user the option to either specify the UUID
> explicitly or have a UUID generated automatical
On Mon, 19 Oct 2020 at 16:45, Peter Maydell wrote:
>
> On Sat, 10 Oct 2020 at 14:57, Luc Michel wrote:
> >
> > v2 -> v3:
> > - patch 03: moved clock_new definition to hw/core/clock.c [Phil]
> > - patch 03: commit message typo [Clement]
> > - patch 10: clarifications around the CM_CTL/CM_DIB
On 10/16/20 8:27 AM, 罗勇刚(Yonggang Luo) wrote:
On Fri, Oct 16, 2020 at 7:48 PM Paolo Bonzini wrote:
Meta-comment. Your quoting style leaves a lot to be desired:
-if test "$docs" = "yes" ; then
- if has $sphinx_build && test "$sphinx_ok" != "yes"; then
-echo "Warning: $sph
On 10/19/20 9:07 PM, Peter Maydell wrote:
The smmuv3_cmdq_cfgi_ste_range trace event prints decimal values with
an 0x prefix, which is confusing. We're printing a range of stream IDs
here, which elsewhere we do in decimal, so use decimal here too and
just drop the '0x' prefix.
Signed-off-by: Pet
On 10/19/20 7:39 PM, Peter Xu wrote:
Dave magically found this. Fix them with "0x%x".
Reported-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
On 10/19/20 6:36 PM, Maxim Levitsky wrote:
Signed-off-by: Maxim Levitsky
---
include/hw/qdev-core.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 868973319e..3761186804 100644
--- a/include/hw/qdev-core.h
+++ b/in
On Mon, Oct 19, 2020 at 11:17:18AM +0900, Dmitry Fomichev wrote:
> +QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
...
> QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
You've got duplicate sizeof checks for the NvmeIdNsDescr.
Otherwise, the patch looks fine.
On Mon, Oct 19, 2020 at 5:45 PM Paolo Bonzini wrote:
>
> Redo the curses test to do the same tests that the configure
> check used to do. OpenBSD triggers the warning because
> it does not support NCURSES_WIDECHAR and thus the cc.links
> test fails.
>
> Signed-off-by: Paolo Bonzini
> ---
> meso
On Tue, 20 Oct 2020 00:45:28 +0530
Kirti Wankhede wrote:
> On 10/19/2020 10:54 PM, Alex Williamson wrote:
> > On Mon, 19 Oct 2020 11:31:03 +0530
> > Kirti Wankhede wrote:
> >
> >> On 9/26/2020 3:53 AM, Alex Williamson wrote:
> >>> On Wed, 23 Sep 2020 04:54:15 +0530
> >>> Kirti Wankhede wro
On Mon, Oct 19, 2020 at 11:17:19AM +0900, Dmitry Fomichev wrote:
> Add a new Boolean namespace property, "attached", to provide the most
> basic namespace attachment support. The default value for this new
> property is true. Also, implement the logic in the new CNS values to
> include/exclude name
On 10/19/20 6:07 AM, Philippe Mathieu-Daudé wrote:
From: Alexander von Gluck IV
Signed-off-by: Alexander von Gluck IV
[PMD: Avoid to recreate the image each time]
grammar: s/to recreate/recreating/
Signed-off-by: Philippe Mathieu-Daudé
---
--
Eric Blake, Principal Software Engineer
Red
On 10/18/20 1:34 AM, Zhengui li wrote:
From: Zhengui
Currently, there is no rate limit for qemu-img convert. This may
cause the task of qemu-img convert to consume all the bandwidth
of the storage. This will affect the IO performance of other processes
and virtual machines under shared storage.
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