On 10/19/20 8:13 AM, Peter Maydell wrote: > M-profile CPUs with half-precision floating point support should > be able to write to FPSCR.FZ16, but an M-profile specific masking > of the value at the top of vfp_set_fpscr() currently prevents that. > This is not yet an active bug because we have no M-profile > FP16 CPUs, but needs to be fixed before we can add any. > > The bits that the masking is effectively preventing from being > set are the A-profile only short-vector Len and Stride fields, > plus the Neon QC bit. Rearrange the order of the function so > that those fields are handled earlier and only under a suitable > guard; this allows us to drop the M-profile specific masking, > making FZ16 writeable. > > This change also makes the QC bit correctly RAZ/WI for older > no-Neon A-profile cores. > > This refactoring also paves the way for the low-overhead-branch > LTPSIZE field, which uses some of the bits that are used for > A-profile Stride and Len. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/vfp_helper.c | 47 ++++++++++++++++++++++++----------------- > 1 file changed, 28 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
