If a MemoryRegion has subregion linked (but NOT mapped), these
subregions won't be displayed in the 'info mtree' HMP command.
Add the possibility to display such subregion descriptions.
It will result useful for the Interleaver memory device.
Signed-off-by: Philippe Mathieu-Daudé
---
Any clever
On Mon, Aug 17, 2020 at 7:02 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Move LOG_DIS log to before sleeping handling so that it logs
> for sleep instructions aswell.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> target/microblaze/tran
Some slow devices might be arranged in an interleaved setup to reduce
waiting for memory banks and improve memory throughput. Classical
examples are NOR flashes.
Add an 'interleaver' device to allow making such interleaved memory
accesses. This device support using the 16x8, 32x8, 32x16, 64x8,
64
On Mon, Aug 17, 2020 at 7:04 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Use atomic_cmpxchg to implement the atomic cmpxchg sequence.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> target/microblaze/translate.c | 21 +---
On Mon, Aug 17, 2020 at 7:02 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add support for data-access barriers.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> target/microblaze/translate.c | 5 +
> 1 file changed, 5 insertions(+)
>
>
On 16/08/20 19:30, Philippe Mathieu-Daudé wrote:
> There is an issue when accessing an alias memory region via the
> memory_region_dispatch_read() / memory_region_dispatch_write()
> calls:
>
> The memory_region_init_alias() flow is:
>
> memory_region_init_alias()
> -> memory_region_init()
>
On Mon, 17 Aug 2020 10:17:34 -0400
"Jason J. Herne" wrote:
> The POP states that the IPLB location is only written to 0x14 for
> list-directed IPL. Some operating systems expect 0x14 to not change on
> boot and will fail IPL if it does change.
>
> Fixes: 9bfc04f9ef6802fff0
Should be
Fixes: 9bf
On Thu, Aug 13, 2020 at 06:26:21PM -0400, Eduardo Habkost wrote:
> Separate run of the script using the --force flag, for the cases
> where the typedef wasn't found in the same header.
This scenario feels a little suspicious to me.
A bunch of these are caused because the typedef is put
into qemu/
On 12/08/20 00:51, Dmitry Fomichev wrote:
> When a host-managed zoned device is passed through to the
> guest system using scsi-generic driver, the maximum i/o size for the
> drive at the guest may end up being larger than at the host, causing
> i/o errors while accessing the backing zoned drive at
Hi Gerd
Have another small question. Do you know how force show cursor working
in this case?
Michael
On Mon, Aug 17, 2020 at 9:28 AM Gerd Hoffmann wrote:
>
> Hi,
>
> > > > +static const uint8_t qemu_wacom_hid_report_descriptor[] = {
> > > > + 0x05, 0x01,
> > > > + 0x09, 0x02,
> > >
>
On Thu, Aug 13, 2020 at 04:11:40AM -0700, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200813032537.2888593-1-richard.hender...@linaro.org/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output
On Wed, Aug 12, 2020 at 08:25:21PM -0700, Richard Henderson wrote:
> This allows header files to declare pointers without pulling
> in the entire crypto subsystem.
>
> Signed-off-by: Richard Henderson
> ---
> include/crypto/cipher.h | 2 --
> include/qemu/typedefs.h | 1 +
> 2 files changed, 1 i
On Wed, Aug 12, 2020 at 08:25:25PM -0700, Richard Henderson wrote:
> Both qemu/osdep.h and cipherpriv.h have already been
> included by the parent cipher.c.
>
> Signed-off-by: Richard Henderson
> ---
> crypto/cipher-builtin.inc.c | 2 --
> crypto/cipher-gcrypt.inc.c | 2 --
> crypto/cipher-nett
On Wed, Aug 12, 2020 at 08:25:23PM -0700, Richard Henderson wrote:
> The check in the encode/decode path using full division has a
> noticeable amount of overhead. By asserting the blocksize is
> a power of 2, we can reduce this check to a mask.
>
> Signed-off-by: Richard Henderson
> ---
> cryp
On Thu, Aug 13, 2020 at 10:00:29AM +0200, Philippe Mathieu-Daudé wrote:
> On 8/13/20 5:25 AM, Richard Henderson wrote:
> > QEMU standard procedure for included c files is to use *.inc.c.
> > E.g. there are a different set of checks that are applied.
> >
> > Signed-off-by: Richard Henderson
> > --
On Wed, Aug 12, 2020 at 08:25:26PM -0700, Richard Henderson wrote:
> The fourth argument to xts_encrypt should be the decrypt
> callback; we were accidentally passing encrypt twice.
>
> Signed-off-by: Richard Henderson
> ---
> crypto/cipher-nettle.inc.c | 2 +-
> 1 file changed, 1 insertion(+),
On Wed, Aug 12, 2020 at 08:25:27PM -0700, Richard Henderson wrote:
> This allows the in memory structures to be read-only.
>
> Signed-off-by: Richard Henderson
> ---
> crypto/cipherpriv.h | 2 +-
> include/crypto/cipher.h | 2 +-
> crypto/cipher-afalg.c | 2 +-
> crypto/ciph
On Wed, Aug 12, 2020 at 08:25:28PM -0700, Richard Henderson wrote:
> Merge the allocation of "opaque" into the allocation of "cipher".
> This is step one in reducing the indirection in these classes.
>
> Signed-off-by: Richard Henderson
> ---
> crypto/afalgpriv.h | 3 ++
> crypto/ciphe
On Wed, Aug 12, 2020 at 08:25:29PM -0700, Richard Henderson wrote:
> The class vtable should be set by the class initializer.
> This will also allow additional subclassing, reducing the
> amount of indirection in the hierarchy.
>
> Signed-off-by: Richard Henderson
> ---
> crypto/cipherpriv.h
On Wed, Aug 12, 2020 at 08:25:30PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> crypto/cipher.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Daniel P. Berrangé
Regards,
Daniel
--
|: https://berrange.com -o-https://www.flick
On Wed, Aug 12, 2020 at 08:25:31PM -0700, Richard Henderson wrote:
> We verified that the data block is properly sized modulo
> AES_BLOCK_SIZE within qcrypto_builtin_cipher_{en,de}crypt.
> Therefore we will never have to handle odd sized blocks.
>
> Signed-off-by: Richard Henderson
> ---
> crypt
On Wed, Aug 12, 2020 at 08:25:33PM -0700, Richard Henderson wrote:
> By making the function private, we will be able to make further
> simplifications. Re-indent the migrated code and fix the missing
> braces for CODING_STYLE.
>
> Signed-off-by: Richard Henderson
> ---
> include/crypto/aes.h
On Wed, Aug 12, 2020 at 08:25:32PM -0700, Richard Henderson wrote:
> There's no real reason we need two separate helper functions here.
> Standardize on the function signature required for xts_encrypt.
> Rename to do_aes_{en,de}crypt_ecb, since the helper does not
> itself do anything with respect
On Wed, Aug 12, 2020 at 08:25:34PM -0700, Richard Henderson wrote:
> Split into encrypt/decrypt functions, dropping the "enc" argument.
> Now that the function is private to this file, we know that "len"
> is a multiple of AES_BLOCK_SIZE. So drop the odd block size code.
>
> Name the functions do
On 15/08/20 16:19, Li Qiang wrote:
> Currently in 'megasas_map_sgl' when 'iov_count=0' will just return
> success however the 'cmd' doens't contain any iov. This will cause
> the assert in 'scsi_dma_complete' failed. This is because in
> 'dma_blk_cb' the 'dbs->sg_cur_index == dbs->sg->nsg' will be
On Wed, Aug 12, 2020 at 08:25:20PM -0700, Richard Henderson wrote:
> Mostly this is intended to cleanup the class hierarchy
> used for the ciphers. We currently have multiple levels
> of dispatch, and multiple separate allocations. The final
> patches rearrange this to one level of indirect call,
On Mon, Aug 17, 2020 at 05:29:38PM +0100, Daniel P. Berrangé wrote:
> On Thu, Aug 13, 2020 at 06:26:21PM -0400, Eduardo Habkost wrote:
> > Separate run of the script using the --force flag, for the cases
> > where the typedef wasn't found in the same header.
>
> This scenario feels a little suspi
No, the ext ID wasn't be checked at a real HW.
Just copied it from the U-boot official repository
https://github.com/u-boot/u-boot/blob/789bfb52668ee609b2043de645e2f94bbd24fd1f/drivers/mtd/spi/spi-nor-ids.c#L183
Do i need to take it from a real HW and compare?
On 12.08.2020 10:27, Cédric Le Goate
On Mon, Aug 17, 2020 at 08:42:04AM -0700, Richard Henderson wrote:
> On 8/17/20 7:01 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add support for data-access barriers.
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target/microblaze/translate.c | 5 +
> > 1 file
On Thu, Aug 13, 2020 at 7:36 PM Kevin Wolf wrote:
> Instead of implementing qemu-nbd --offset in the NBD code, just put a
> raw block node with the requested offset on top of the user image and
> rely on that doing the job.
>
> This does not only simplify the nbd_export_new() interface and bring
Nikola reported on Windows when gd_vc_gfx_init() is called, the
window is not yet realized, so we run gd_refresh_rate_millihz(NULL)
which returns 0 milli-Hertz.
When a Widget is realized, it fires a 'realized' event. We already
have the gd_draw_event() handler registered for this even, so simply
mo
From: "Edgar E. Iglesias"
Trap mbar-sleeps from user-space.
Reported-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 530c15e5ad
From: "Edgar E. Iglesias"
As suggested by Richard, trap mbar/sleeps from user-space.
Cheers,
Edgar
Edgar E. Iglesias (1):
target/microblaze: mbar: Trap sleeps from user-space
target/microblaze/translate.c | 5 +
1 file changed, 5 insertions(+)
--
2.25.1
+-- On Mon, 17 Aug 2020, Philippe Mathieu-Daudé wrote --+
| On 8/17/20 7:02 AM, P J P wrote:
| > +-- On Sun, 16 Aug 2020, Philippe Mathieu-Daudé wrote --+
| > | What about read_with_attrs()/write_with_attrs()? It seems they are part
| > | of the same problem.
| >
| > * read/write_with_attrs funct
On 8/17/20 12:30 PM, Cornelia Huck wrote:
On Mon, 17 Aug 2020 10:17:34 -0400
"Jason J. Herne" wrote:
The POP states that the IPLB location is only written to 0x14 for
list-directed IPL. Some operating systems expect 0x14 to not change on
boot and will fail IPL if it does change.
Fixes: 9bfc04
On Fri, Aug 14, 2020 at 9:43 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Currently the reset vector address is hard-coded in a RISC-V CPU's
> instance_init() routine. In a real world we can have 2 exact same
> CPUs except for the reset vector address, which is pretty common in
> the RISC-V core IP
On Fri, Aug 14, 2020 at 9:41 AM Bin Meng wrote:
>
> From: Bin Meng
>
> RISC-V machines do not instantiate RISC-V CPUs directly, instead
> they do that via the hart array. Add a new property for the reset
> vector address to allow the value to be passed to the CPU, before
> CPU is realized.
>
> Si
On Fri, Aug 14, 2020 at 9:45 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Now that we have the newly introduced 'resetvec' property in the
> RISC-V CPU and HART, instead of hard-coding the reset vector addr
> in the CPU's instance_init(), move that to riscv_cpu_realize()
> based on the configured pr
On 8/17/20 1:39 AM, Gerd Hoffmann wrote:
> Hi,
>
>> FWIW I'm still hitting issues with qemu-5.1.0 GA but maybe it's
>> unrelated to that specific fix. Issues reproduce on fedora 33+, not
>> fedora 32.
>
>> +Failed to open module:
>> /builddir/build/BUILD/qemu-5.1.0-rc3/build-dynamic/x86_64-soft
Hi Anup,
On 8/17/20 11:30 AM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Anup,
>
> On Sat, Aug 15, 2020 at 1:44 AM Anup Patel wrote:
>> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng wrote:
>>> From: Bin Meng
>>>
>>> This ad
On Mon 17 Aug 2020 05:53:07 PM CEST, Kevin Wolf wrote:
> Maybe the difference is in allocating 64k at once instead of doing a
> separate allocation for every 4k block? But with the extent size hint
> patches to file-posix, we should allocate 1 MB at once by default now
> (if your test image was new
Patchew URL: https://patchew.org/QEMU/20200817172331.598255-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On 7/30/2020 11:14 AM, Steve Sistare wrote:
> Anonymous memory segments used by the guest are preserved across a re-exec
> of qemu, mapped at the same VA, via a proposed madvise(MADV_DOEXEC) option
> in the Linux kernel. For the madvise patches, see:
>
> https://lore.kernel.org/lkml/1595869887-233
Hi Philippe,
Nice improvement, I didnt know about this API. Makes sense to use it indeed.
The patch works fine. I tested your patches by applying the previous two
sets first, and then this one.
It ran well with the avocado tests and also with the official image
OrangePi_pc_debian_stretch_server_li
Hi Philippe,
Same as the one for the SD device: I tested it with the avocado tests and
the official image OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
and networking is working good (ran some apt-get commands etc).
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
Regards,
Niek
On 8/17/20 8:24 PM, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200817172331.598255-1-phi...@redhat.com/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker installe
Hi,
Interesting suggestion Philippe. I modelled the initial code of the H3 SoC
mostly in-line with the aspeed SoC,
to let it use commonly applied code structures where possible. And it looks
like in this series, aspeed_soc.h is also
getting the same change. I'll see if I can find some time to make
On Mon, Aug 17, 2020 at 11:12 AM via wrote:
>
> Hi Anup,
>
> On 8/17/20 11:30 AM, Bin Meng wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Hi Anup,
> >
> > On Sat, Aug 15, 2020 at 1:44 AM Anup Patel wrote:
> >> On Fri, Aug 14, 202
Patchew URL:
https://patchew.org/QEMU/20200817143723.343284-1-pbonz...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200817143723.343284-1-pbonz...@redhat.com
Subject: [PATCH v3 000/150] Meson integratio
Patchew URL:
https://patchew.org/QEMU/20200817143723.343284-1-pbonz...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN =
On Fri, Aug 14, 2020 at 9:43 AM Bin Meng wrote:
>
> From: Bin Meng
>
> This is an initial support for Microchip PolarFire SoC Icicle Kit.
> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>
> For more details a
On 8/17/20 8:28 PM, Alistair Francis wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Mon, Aug 17, 2020 at 11:12 AM via wrote:
>> Hi Anup,
>>
>> On 8/17/20 11:30 AM, Bin Meng wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachme
Patchew URL: https://patchew.org/QEMU/20200817161853.593247-1-f4...@amsat.org/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
On 8/17/20 9:48 AM, Daniel P. Berrangé wrote:
> On Wed, Aug 12, 2020 at 08:25:21PM -0700, Richard Henderson wrote:
>> This allows header files to declare pointers without pulling
>> in the entire crypto subsystem.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> include/crypto/cipher.h | 2 --
>>
On 8/17/20 1:38 PM, Richard Henderson wrote:
> On 8/17/20 9:48 AM, Daniel P. Berrangé wrote:
>> On Wed, Aug 12, 2020 at 08:25:21PM -0700, Richard Henderson wrote:
>>> This allows header files to declare pointers without pulling
>>> in the entire crypto subsystem.
>>>
>>> Signed-off-by: Richard Hend
On Mon, 17 Aug 2020 14:30:51 -0400
Steven Sistare wrote:
> On 7/30/2020 11:14 AM, Steve Sistare wrote:
> > Anonymous memory segments used by the guest are preserved across a re-exec
> > of qemu, mapped at the same VA, via a proposed madvise(MADV_DOEXEC) option
> > in the Linux kernel. For the mad
On 8/17/20 10:09 AM, Daniel P. Berrangé wrote:
> What were you measuring performance with ? Did you use the
> benchmark-crypto-cipher program or something else ?
Perf of a boot of an aarch64 kernel, which
* debug enabled for regression testing,
* the v8.3-pauth instructions enabled,
* a l
On 8/17/20 1:42 PM, Richard Henderson wrote:
> On 8/17/20 1:38 PM, Richard Henderson wrote:
>> On 8/17/20 9:48 AM, Daniel P. Berrangé wrote:
>>> On Wed, Aug 12, 2020 at 08:25:21PM -0700, Richard Henderson wrote:
This allows header files to declare pointers without pulling
in the entire cr
On Fri, Aug 14, 2020 at 9:45 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Microchip PolarFire SoC MMUART is ns16550 compatible, with some
> additional registers. Create a simple MMUART model built on top
> of the existing ns16550 model.
>
> Signed-off-by: Bin Meng
> ---
>
> MAINTAINERS
On Fri, Aug 14, 2020 at 9:49 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
> wires 4 of them out. Let's connect all 5 MMUARTs.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/Kconfig
On 8/17/2020 4:48 PM, Alex Williamson wrote:
> On Mon, 17 Aug 2020 14:30:51 -0400
> Steven Sistare wrote:
>
>> On 7/30/2020 11:14 AM, Steve Sistare wrote:
>>> Anonymous memory segments used by the guest are preserved across a re-exec
>>> of qemu, mapped at the same VA, via a proposed madvise(MADV
Host CPU : Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz
Host Memory : 15.49 GB
Start Time (UTC) : 2020-08-17 21:00:02
End Time (UTC) : 2020-08-17 21:32:56
Execution Time : 0:32:54.21
Status : SUCCESS
On Mon, 17 Aug 2020 17:20:57 -0400
Steven Sistare wrote:
> On 8/17/2020 4:48 PM, Alex Williamson wrote:
> > On Mon, 17 Aug 2020 14:30:51 -0400
> > Steven Sistare wrote:
> >
> >> On 7/30/2020 11:14 AM, Steve Sistare wrote:
> >>> Anonymous memory segments used by the guest are preserved acros
User opens /proc/self/exe symlink, than kernel should create
/proc/self/fd/ symlink. We should be able to detect both exe and
fd/ symlinks to provide common behaviour. The easiest solution is to
make execfd global and keep it open. This solution looks acceptable because
exec_path is already glo
Signed-off-by: Andrew Aladjev
---
linux-user/Makefile.objs | 5 +++--
linux-user/syscall.c | 33 +
linux-user/syscall_proc.c | 32
linux-user/syscall_proc.h | 7 +++
4 files changed, 43 insertions(+), 34 deletions(-)
cr
Signed-off-by: Andrew Aladjev
---
linux-user/syscall.c | 12 ++--
linux-user/syscall_proc.c | 113 +++---
linux-user/syscall_proc.h | 5 +-
3 files changed, 101 insertions(+), 29 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 0
On 8/17/20 10:30 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Trap mbar-sleeps from user-space.
>
> Reported-by: Richard Henderson
> Signed-off-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Hender
On 8/17/20 6:04 AM, Chenqun (kuhn) wrote:
> Other branches(eg:' CASE_OP_32_64(brcond)') have changed the opc value too.
> Do we need to assign a value to nb_iargs for it?
In those cases nb_iargs does not change.
r~
Paolo Bonzini 于2020年8月18日周二 上午1:05写道：
> On 15/08/20 16:19, Li Qiang wrote:
> > Currently in 'megasas_map_sgl' when 'iov_count=0' will just return
> > success however the 'cmd' doens't contain any iov. This will cause
> > the assert in 'scsi_dma_complete' failed. This is because in
> > 'dma_blk_cb
If I connect a serial mouse to the built-in serial port on an old
(kernel 2.4) box and go
stty -F /dev/ttyS0 1200 cs7
dd if=/dev/ttyS0 bs=1|hexdump -C
The bytes received/printed when the mouse is moved all have bit7=0.
--
You received this bug notification because you are a member of qemu-
deve
David Gibson writes:
> On Mon, Aug 17, 2020 at 07:24:43AM +0200, Philippe Mathieu-Daudé wrote:
>> On 8/17/20 6:47 AM, David Gibson wrote:
>> > On Wed, Jul 22, 2020 at 11:56:49PM -0300, Thiago Jung Bauermann wrote:
>> >> The ARM code has a start-powered-off property in ARMCPU, which is a
>> >> s
On Mon, 17 Aug 2020 15:44:03 -0600
Alex Williamson wrote:
> On Mon, 17 Aug 2020 17:20:57 -0400
> Steven Sistare wrote:
>
> > On 8/17/2020 4:48 PM, Alex Williamson wrote:
> > > On Mon, 17 Aug 2020 14:30:51 -0400
> > > Steven Sistare wrote:
> > >
> > >> On 7/30/2020 11:14 AM, Steve Sistar
On 2020/8/14 下午1:16, Yan Zhao wrote:
On Thu, Aug 13, 2020 at 12:24:50PM +0800, Jason Wang wrote:
On 2020/8/10 下午3:46, Yan Zhao wrote:
driver is it handled by?
It looks that the devlink is for network device specific, and in
devlink.h, it says
include/uapi/linux/devlink.h - Network physical d
This version tries to fix an issue found by David Gibson when running
the Travis CI:
Unexpected error in qdev_prop_set_after_realize() at
/home/travis/build/dgibson/qemu/hw/core/qdev-properties.c:30:
qemu-system-mips64el: Attempt to set property 'start-powered-off' on anonymous
device (type 'I64
This change is in a separate patch because it's not so obvious that it
won't cause a regression.
Suggested-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
Reviewed-by: Greg Kurz
Signed-off-by: Thiago Jung Bauermann
---
hw/core/cpu.c| 2 +-
target/arm/cpu
PowerPC sPAPR CPUs start in the halted state, and spapr_reset_vcpu()
attempts to implement this by setting CPUState::halted to 1. But that's too
late for the case of hotplugged CPUs in a machine configure with 2 or more
threads per core.
By then, other parts of QEMU have already caused the vCPU to
There are other platforms which also have CPUs that start powered off, so
generalize the start-powered-off property so that it can be used by them.
Note that ARMv7MState also has a property of the same name but this patch
doesn't change it because that class isn't a subclass of CPUState so it
woul
Instead of setting CPUState::halted to 1 in ppce500_cpu_reset_sec(), use
the start-powered-off property which makes cpu_common_reset() initialize it
to 1 in common code.
Also change creation of CPU object from cpu_create() to object_new() and
qdev_realize() because cpu_create() realizes the CPU an
Instead of setting CPUState::halted to 1 in main_cpu_reset(), use the
start-powered-off property which makes cpu_common_reset() initialize it
to 1 in common code.
Also change creation of CPU object from cpu_create() to object_new() and
qdev_realize() because cpu_create() realizes the CPU and it's
We rely on cpu_common_reset() to set cs->halted to 0, so main_cpu_reset()
is pointless.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
Signed-off-by: Thiago Jung Bauermann
---
hw/sparc/sun4m.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/hw/
Instead of setting CPUState::halted to 1 in secondary_cpu_reset(), use the
start-powered-off property which makes cpu_common_reset() initialize it
to 1 in common code.
This makes secondary_cpu_reset() unnecessary, so remove it.
Also remove setting of cs->halted from cpu_devinit(), which seems out
Instead of setting CPUState::halted to 1 in s390_cpu_initfn(), use the
start-powered-off property which makes cpu_common_reset() initialize it
to 1 in common code.
Note that this changes behavior by setting cs->halted to 1 on reset, which
didn't happen before.
Acked-by: Cornelia Huck
Signed-off-
From: Matthieu Bucchianeri
Fix double-call to tcg_temp_new_i64(), where a temp is allocated both at
declaration time and further down the implementation of gen_evmwsmiaa().
Note that gen_evmwsmia() and gen_evmwsmiaa() are still not implemented
correctly, as they invoke gen_evmwsmi() which may re
From: Lijun Pan
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
Message-Id: <20200701234344.91843-2-...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e7d
From: Gustavo Romero
Fix some typos in comments about code modeling coalescing points in the
XIVE routing engine (IVRE).
Signed-off-by: Gustavo Romero
Message-Id: <1595461434-27725-1-git-send-email-grom...@linux.ibm.com>
Signed-off-by: David Gibson
---
hw/intc/xive.c | 6 +++---
1 file change
The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:
Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-5.2-20200818
for you to fetch changes up to 3110f0ee19ccdb50adff3
From: Lijun Pan
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
Message-Id: <20200701234344.91843-4-...@linux.ibm.com>
Signed-off-by: David Gibson
---
tar
From: Lijun Pan
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
Message-Id: <20200701234344.91843-6-...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4
2 files changed, 5 insertions(+)
di
From: Lijun Pan
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
Message-Id: <20200724045845.89976-5-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/helper.h
From: Greg Kurz
Nested KVM HV only works if the kernel is using the radix MMU mode, ie.
the CPU is POWER9 and it is not running in some pre-power9 compat mode.
Otherwise, the KVM HV module fails to load in the guest with -ENODEV.
It might be painful for a user to discover this late that nested ca
From: Lijun Pan
This patch enables the Power ISA 3.1 in QEMU.
Signed-off-by: Lijun Pan
Message-Id: <20200701234344.91843-3-...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/cpu.h| 2 +-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 2 insertions(+), 2 del
From: Lijun Pan
Convert the original implementation of vmuluwm to the more generic
tcg_gen_gvec_mul.
Signed-off-by: Lijun Pan
Message-Id: <20200701234344.91843-5-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 -
targ
From: Lijun Pan
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
Message-Id: <20200724045845.89976-4-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/helper.h | 2 ++
ta
From: Greg Kurz
We have a dedicated error API for hints. Use it instead of embedding
the hint in the error message, as recommanded in the "qapi/error.h"
header file.
While here, have cap_fwnmi_apply(), which already uses
error_append_hint(), to call ERRP_GUARD() as well.
Signed-off-by: Greg Kur
From: Daniel Henrique Barboza
This patch adds a new documentation file, ppc-spapr-numa.rst,
informing what developers and user can expect of the NUMA distance
support for the pseries machine, up to QEMU 5.1.
In the (hopefully soon) future, when we rework the NUMA mechanics
of the pseries machine
From: Lijun Pan
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan
Message-Id: <20200724045845.89976-3-...@linux.ibm.com>
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
tcg/ppc/tcg-target.h | 2 ++
tcg/ppc/tcg
From: Cédric Le Goater
It is not yet supported.
Signed-off-by: Cédric Le Goater
Message-Id: <20200804131639.407049-1-...@kaod.org>
Signed-off-by: David Gibson
---
docs/specs/ppc-spapr-xive.rst | 5 +
1 file changed, 5 insertions(+)
diff --git a/docs/specs/ppc-spapr-xive.rst b/docs/specs/
From: Lijun Pan
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan
Message-Id: <20200724045845.89976-2-...@linux.ibm.com>
Signed-off-by: David Gibson
Reviewed-by: Richard Henderson
---
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/i
From: Gustavo Romero
Currently if option '-icount auto' is passed to the QEMU TCG to enable
counting instructions the VM crashes with the following error report when
Linux runs on it:
qemu-system-ppc64: Bad icount read
This happens because read/write access to the SPRs PURR, VTB, and TBU40
is n
From: Greg Kurz
When starting an L2 KVM guest with `ic-mode=dual,kernel-irqchip=on`,
QEMU fails with:
KVM is too old to support ic-mode=dual,kernel-irqchip=on
This error message was introduced to detect older KVM versions that
didn't allow destruction and re-creation of the XICS KVM device that
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