On Fri, Aug 14, 2020 at 9:49 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
> wires 4 of them out. Let's connect all 5 MMUARTs.
>
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++
> include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
> 3 files changed, 51 insertions(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 3292fae..ceb7c16 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -54,3 +54,4 @@ config MICROCHIP_PFSOC
> select HART
> select SIFIVE
> select UNIMP
> + select MCHP_PFSOC_MMUART
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 20a642c..f6b375c 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -11,6 +11,7 @@
> * 0) CLINT (Core Level Interruptor)
> * 1) PLIC (Platform Level Interrupt Controller)
> * 2) eNVM (Embedded Non-Volatile Memory)
> + * 3) MMUARTs (Multi-Mode UART)
> *
> * This board currently generates devicetree dynamically that indicates at
> least
> * two harts and up to five harts.
> @@ -38,6 +39,7 @@
> #include "hw/irq.h"
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> +#include "chardev/char.h"
> #include "hw/cpu/cluster.h"
> #include "target/riscv/cpu.h"
> #include "hw/misc/unimp.h"
> @@ -46,6 +48,7 @@
> #include "hw/riscv/sifive_clint.h"
> #include "hw/riscv/sifive_plic.h"
> #include "hw/riscv/microchip_pfsoc.h"
> +#include "sysemu/sysemu.h"
>
> /*
> * The BIOS image used by this machine is called Hart Software Services
> (HSS).
> @@ -69,8 +72,13 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
> [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
> [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
> + [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
> [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
> + [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
> + [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
> + [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> + [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> @@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> memmap[MICROCHIP_PFSOC_MPUCFG].base,
> memmap[MICROCHIP_PFSOC_MPUCFG].size);
>
> + /* MMUARTs */
> + s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
> + memmap[MICROCHIP_PFSOC_MMUART0].base,
> + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
> + serial_hd(0));
> + s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
> + memmap[MICROCHIP_PFSOC_MMUART1].base,
> + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
> + serial_hd(1));
> + s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
> + memmap[MICROCHIP_PFSOC_MMUART2].base,
> + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
> + serial_hd(2));
> + s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
> + memmap[MICROCHIP_PFSOC_MMUART3].base,
> + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
> + serial_hd(3));
> + s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
> + memmap[MICROCHIP_PFSOC_MMUART4].base,
> + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
> + serial_hd(4));
> +
> /* eNVM */
> memory_region_init_rom(envm_data, OBJECT(dev),
> "microchip.pfsoc.envm.data",
> memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 1953ef1..a5efa1d 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -22,6 +22,8 @@
> #ifndef HW_MICROCHIP_PFSOC_H
> #define HW_MICROCHIP_PFSOC_H
>
> +#include "hw/char/mchp_pfsoc_mmuart.h"
> +
> typedef struct MicrochipPFSoCState {
> /*< private >*/
> DeviceState parent_obj;
> @@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState {
> RISCVHartArrayState e_cpus;
> RISCVHartArrayState u_cpus;
> DeviceState *plic;
> + MchpPfSoCMMUartState *serial0;
> + MchpPfSoCMMUartState *serial1;
> + MchpPfSoCMMUartState *serial2;
> + MchpPfSoCMMUartState *serial3;
> + MchpPfSoCMMUartState *serial4;
> } MicrochipPFSoCState;
>
> #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
> @@ -64,14 +71,27 @@ enum {
> MICROCHIP_PFSOC_L2CC,
> MICROCHIP_PFSOC_L2LIM,
> MICROCHIP_PFSOC_PLIC,
> + MICROCHIP_PFSOC_MMUART0,
> MICROCHIP_PFSOC_SYSREG,
> MICROCHIP_PFSOC_MPUCFG,
> + MICROCHIP_PFSOC_MMUART1,
> + MICROCHIP_PFSOC_MMUART2,
> + MICROCHIP_PFSOC_MMUART3,
> + MICROCHIP_PFSOC_MMUART4,
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> MICROCHIP_PFSOC_DRAM,
> };
>
> +enum {
> + MICROCHIP_PFSOC_MMUART0_IRQ = 90,
> + MICROCHIP_PFSOC_MMUART1_IRQ = 91,
> + MICROCHIP_PFSOC_MMUART2_IRQ = 92,
> + MICROCHIP_PFSOC_MMUART3_IRQ = 93,
> + MICROCHIP_PFSOC_MMUART4_IRQ = 94,
> +};
> +
> #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
> #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
>
> --
> 2.7.4
>
>
