On Fri, Jul 03, 2020 at 08:49:52PM +0200, Philippe Mathieu-Daudé wrote:
> By using the TYPE_* definitions for devices, we can:
> - quickly find where devices are used with 'git-grep'
> - easily rename a non-user-creatable device (one-line change).
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-
On 23/06/20 12:50, Philippe Mathieu-Daudé wrote:
> The sigmask_len is a property of the accelerator, not the VM.
> Simplify by directly using the global kvm_state, remove the
> unnecessary KVMState* argument.
This is not entirely true, if there were multiple KVMStates how would
you know which one
On Tue, Jun 30, 2020 at 11:45:42PM +0200, BALATON Zoltan wrote:
> On Tue, 30 Jun 2020, Mark Cave-Ayland wrote:
> > On 29/06/2020 19:55, BALATON Zoltan wrote:
> > > The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
> > > the rom region and fall back to loading a binary image with
On Fri, Jun 26, 2020 at 11:33:03AM +0100, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > We haven't yet implemented the fairly involved handshaking that will be
> > needed to migrate PEF protected guests. For now, just use a migration
> > blocker so we get
Public bug reported:
Reported by on IRC:
QEMU almost freezes when running with `GDK_BACKEND=x11` set and the
parameter `gl=on` added to the `-display` option.
GDK_BACKEND=x11 qemu-system-x86_64 -nodefaults -no-user-config -enable-
kvm -machine q35 -cpu host -m 4G -display gtk,gl=on -vga std -us
On 7/4/20 7:15 PM, BALATON Zoltan wrote:
> On Sat, 4 Jul 2020, Philippe Mathieu-Daudé wrote:
>> Various machine/board/soc models create EHCI device instances
>> with the generic QDEV API, and don't need to access USB internals.
>>
>> Simplify header inclusions by moving the QOM type names into a
>>
On Wed, Jul 01, 2020 at 06:43:37PM -0500, Lijun Pan wrote:
> This patch enables the Power ISA 3.1 in QEMU.
>
> Signed-off-by: Lijun Pan
Applied to ppc-for-5.2.
> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
>
> target/ppc/cpu.h| 2 +-
> target/ppc/translate_
On Wed, Jul 01, 2020 at 06:43:35PM -0500, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
> this version. In v4 version, coding style issues are fixed, community
> reviews/suggestions are taken i
On Wed, Jul 01, 2020 at 06:43:36PM -0500, Lijun Pan wrote:
> This flag will be used for Power10 instructions.
>
> Signed-off-by: Lijun Pan
Applied to ppc-for-5.2.
> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
>
> target/ppc/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
On Wed, 24 Jun 2020 21:47:46 +0200
Lukas Straub wrote:
> On Tue, 23 Jun 2020 16:42:30 +0200
> Lukas Straub wrote:
>
> > Hello Everyone,
> > In many cases, if qemu has a network connection (qmp, migration, chardev,
> > etc.)
> > to some other server and that server dies or hangs, qemu hangs too
On Sat, 6 Jun 2020 21:17:32 +0200
Lukas Straub wrote:
> Hello Everyone,
> So here is v2. Patch 1 can already be merged independently of the others.
>
> Regards,
> Lukas Straub
>
> Changes:
> v2:
> -use new yank api
> -drop disk_size parameter
> -introduce pick_qemu_util function and use it
>
On 7/5/20 9:12 AM, Paolo Bonzini wrote:
> On 23/06/20 12:50, Philippe Mathieu-Daudé wrote:
>> The sigmask_len is a property of the accelerator, not the VM.
>> Simplify by directly using the global kvm_state, remove the
>> unnecessary KVMState* argument.
>
> This is not entirely true, if there were
On 7/5/20 7:46 AM, Paolo Bonzini wrote:
> On 20/06/20 17:38, Philippe Mathieu-Daudé wrote:
>> -} else {
>> -assert(!DEVICE_GET_CLASS(dev)->bus_type);
>> +} else if (DEVICE_GET_CLASS(dev)->bus_type) {
>> +error_report("%s: Unexpected bus '%s' for device '%s'",
>> +
Are we sure that qdev_realize is never called with user-provided input? If
it's a programming error, the call chain will end up passing &error_abort
anyway, won't it?
Paolo
Il dom 5 lug 2020, 12:05 Philippe Mathieu-Daudé ha
scritto:
> On 7/5/20 7:46 AM, Paolo Bonzini wrote:
> > On 20/06/20 17:3
Public bug reported:
The Debian Sid 5.0-6 qemu-kvm package can no longer get further than the
Clover bootloader whereas 5.0-6 and earlier worked fine.
So I built qemu master from github and it has the same problem, whereas
git tag v5.0.0 (or 4.2.1) does not, so something between v5.0.0 release
an
On Fri, Jul 03, 2020 at 09:25:10PM +0200, Gerd Hoffmann wrote:
> On Fri, Jul 03, 2020 at 09:09:43AM -0400, Michael S. Tsirkin wrote:
> > On Thu, Jul 02, 2020 at 10:48:46PM +0200, Gerd Hoffmann wrote:
> > > +/* copy AML table into ACPI tables blob and patch header there */
> > > +g_array_app
On 7/5/20 1:14 PM, Paolo Bonzini wrote:
> Are we sure that qdev_realize is never called with user-provided input?
I am not sure, but ...
> If it's a programming error, the call chain will end up passing
> &error_abort anyway, won't it?
... this is a good point :)
>
> Paolo
>
> Il dom 5 lug 20
Correct the format
> -Original Message-
> From: Richard Henderson
> Sent: Friday, July 3, 2020 2:54 AM
> To: Wu, Wentong ; qemu-devel@nongnu.org
> Cc: qemu-triv...@nongnu.org; ma...@denx.de; crwu...@gmail.com;
> peter.mayd...@linaro.org
> Subject: Re: [PATCH 3/3] target/nios2: Use gen_i
Correct the format
> -Original Message-
> From: Richard Henderson
> Sent: Friday, July 3, 2020 2:54 AM
> To: Wu, Wentong ; qemu-devel@nongnu.org
> Cc: qemu-triv...@nongnu.org; ma...@denx.de; crwu...@gmail.com;
> peter.mayd...@linaro.org
> Subject: Re: [PATCH 3/3] target/nios2: Use gen_i
From: Michael Rolnik
This includes definitions of various basic parameters needed
for integration of a new platform into QEMU.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-
From: Michael Rolnik
This patch introduces three memory-management-related functions
that will become part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Si
This is the AVR port from Michael, release (merge) candidate 6.
I've rebased rc5 to the current master branch, fixed the conflicts,
and updated the APIs where necessary (e.g. qdev_create() had to be
replaced).
These patches have been on the list for a long time. Let's try to
get them finally merg
From: Michael Rolnik
AVR core types are:
- avr1
- avr2
- avr25
- avr3
- avr31
- avr35
- avr4
- avr5
- avr51
- avr6
- avrtiny
- xmega2
- xmega3
- xmega4
- xmega5
- xmega6
- xmega7
Each core type covers multiple AVR MCUs, mentioned in the comments
before definiti
From: Michael Rolnik
This patch introduces functions avr_cpu_do_interrupt() and
avr_cpu_exec_interrupt() that are part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sara
From: Michael Rolnik
Initialize TCG register variables.
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
S
From: Michael Rolnik
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Signed-
From: Michael Rolnik
Add migration-related functions of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harr
From: Michael Rolnik
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Signed-off-by: Thomas Huth
---
target/avr/insn.decode | 8 +
target/avr/tr
From: Michael Rolnik
This patch introduces AVR CPU class object and its basic elements
and functions.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
S
From: Philippe Mathieu-Daudé
Arduino boards are build with AVR chipsets. Add some of these
boards:
- Arduino Duemilanove
- Arduino Uno
- Arduino Mega
For more information:
https://www.arduino.cc/en/Main/Products
https://store.arduino.cc/arduino-genuino/most-popular
[AM: Remove word '
From: Michael Rolnik
Provide function disassembles executed instruction when `-d in_asm` is
provided
Example:
`./avr-softmmu/qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
-d in_asm` will produce something like the following
```
...
IN:
0x014a: CALL 0x38
From: Michael Rolnik
Make AVR support buildable.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-b
From: Michael Rolnik
Add the core of translation mechanism.
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovi
From: Michael Rolnik
This patch introduces enumeration "AVRFeature" that will be
used for defining various AVR core types.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM: Re
From: Michael Rolnik
This is a simple device of just one register, and whenever this
register is written to it calls qemu_set_irq function for each
of 8 bits/IRQs. It is used to implement AVR Power Reduction.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksan
From: Michael Rolnik
This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Philippe Mathieu-Daudé
Add some AVR microcontrollers from the ATmega family:
- middle range: ATmega168 and ATmega328
- high range: ATmega1280 and ATmega2560
For product comparison:
https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P
https://www.microchip.com
From: Michael Rolnik
Add AVR related definitions into QEMU.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
From: Michael Rolnik
Add helpers for instructions that need to interact with QEMU. Also,
add stubs for unimplemented instructions. Instructions SPM and WDR
are left unimplemented because they require emulation of complex
peripherals. The implementation of instruction SLEEP is very limited
due to
From: Michael Rolnik
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
As the path name demonstrates, the FreeRTOS tests target a
b
From: Philippe Mathieu-Daudé
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type of the variable containing e_flags]
[AM: Moved definition of e_flags conversion function to boot.c]
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathi
From: Michael Rolnik
Start implementation of instructions by adding register definitions.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Michael Rolnik
Print out 'T' through serial port.
The Arduino Duemilanove is based on a AVR5 CPU, while the
Arduino MEGA2560 on a AVR6 CPU.
Signed-off-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
[rth: Squash Arduino adjustments from f4bug]
Tested-by: Richard Henderson
Sign
The new section explains basic ways of using AVR target in QEMU.
Signed-off-by: Michael Rolnik
[thuth: Converted doc from texi to Sphinx syntax]
Signed-off-by: Thomas Huth
---
docs/system/target-avr.rst | 37 +
docs/system/targets.rst| 1 +
2 files chang
From: Michael Rolnik
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philip
From: Michael Rolnik
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by:
From: Michael Rolnik
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
Signed-off-by: Richa
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM: Re
From: Michael Rolnik
Add a single code line that will automatically provide 'machine none'
test.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Reviewed-by: Thomas Huth
Sig
在 2020/7/5 4:04, Philippe Mathieu-Daudé 写道:
Hi Stefan,
On 7/3/20 12:44 PM, Stefan Brankovic wrote:
Add disassembler for Loongson 2F instruction set.
Testing is done by comparing qemu disassembly output, obtained by
using -d in_asm command line option, with appropriate objdump output.
This
Patchew URL:
https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH rc6 00/30] target/avr merger
Type: series
Message-id: 20200705140315.260514-1-h...@tuxfamily.org
On Saturday, July 4, 2020, Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> wrote:
>
>
> On Friday, July 3, 2020, Stefan Brankovic
> wrote:
>
>> Add disassembler for Loongson 2F instruction set.
>>
>> Testing is done by comparing qemu disassembly output, obtained by
>> using -d in_asm comma
On Sunday, July 5, 2020, Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> wrote:
>
>
> On Saturday, July 4, 2020, Aleksandar Markovic <
> aleksandar.qemu.de...@gmail.com> wrote:
>
>>
>>
>> On Friday, July 3, 2020, Stefan Brankovic
>> wrote:
>>
>>> Add disassembler for Loongson 2F instructio
On Thu, 2 Jul 2020 at 19:53, Richard Henderson
wrote:
> This isn't right. Not so much the gen_io_start portion, but the entire
> existence of helper_check_interrupt.
I agree that it looks bogus (xtensa has a similar helper as well, incidentally),
but fixing all that stuff up is more effort than
On Mon, 29 Jun 2020 at 09:17, Wentong Wu wrote:
>
> wrctl instruction on nios2 target will cause checking cpu
> interrupt but tcg_handle_interrupt() will call cpu_abort()
> if the CPU gets an interrupt while it's not in 'can do IO'
> state, so add gen_io_start around wrctl instruction. Also
> at t
On 7/5/20 12:26 AM, Philippe Mathieu-Daudé wrote:
> On 7/5/20 12:18 AM, Philippe Mathieu-Daudé wrote:
>> On 7/5/20 12:10 AM, Philippe Mathieu-Daudé wrote:
>>> On 7/4/20 1:42 AM, Philippe Mathieu-Daudé wrote:
On 7/3/20 5:16 PM, Philippe Mathieu-Daudé wrote:
> On 7/3/20 3:23 PM, Peter Maydel
Since added in commit 2bea128c3d, each SDHCI is wired with a SD
card, using empty card when no block drive provided. This is not
the desired behavior. The SDHCI exposes a SD bus to plug cards
on, if no card available, it is fine to have an unplugged bus.
Avoid creating unnecessary SD card device w
Several callers of load_elf() pass pointers for lowaddr and highaddr
parameters which are then not used for anything. This may stem from a
misunderstanding that load_elf need a value here but in fact it can
take NULL to ignore these values. Remove such unused variables and
pass NULL instead from ca
On Sun, 5 Jul 2020, David Gibson wrote:
On Tue, Jun 30, 2020 at 11:45:42PM +0200, BALATON Zoltan wrote:
On Tue, 30 Jun 2020, Mark Cave-Ayland wrote:
On 29/06/2020 19:55, BALATON Zoltan wrote:
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to l
On 07.02.20 07:43, Jan Kiszka wrote:
From: Jan Kiszka
This is helpful when debugging stuck guest timers.
As we need apic_get_current_count for that, and it is really not
emulation specific, move it to apic_common.c and export it. Fix its
style at this chance as well.
Signed-off-by: Jan Kiszka
On Sun, Jul 5, 2020 at 10:09 AM Peter Maydell wrote:
> On Thu, 2 Jul 2020 at 19:53, Richard Henderson
> wrote:
> > This isn't right. Not so much the gen_io_start portion, but the entire
> > existence of helper_check_interrupt.
>
> I agree that it looks bogus (xtensa has a similar helper as well,
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
>
> From: LIU Zhiwei
>
> Vector AMOs operate as if aq and rl bits were zero on each element
> with regard to ordering relative to other instructions in the same hart.
> Vector AMOs provide no ordering guarantee between element operations
> in t
On Fri, 3 Jul 2020 at 17:54, Peter Maydell wrote:
>
> From: Eric Auger
>
> This patch implements the PROBE request. At the moment,
> only THE RESV_MEM property is handled. The first goal is
> to report iommu wide reserved regions such as the MSI regions
> set by the machine code. On x86 this will
Am Sun, 5 Jul 2020 07:29:06 -0700 (PDT)
schrieb no-re...@patchew.org:
> Patchew URL:
> https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
[...]
> === OUTPUT BEGIN ===
> 1/30 Checking commit b5e3116a3591 (target/avr: Add basic parameters
> of the new platform) WARNING: added, move
On Sun, 5 Jul 2020 at 19:31, Thomas Huth wrote:
>
> Am Sun, 5 Jul 2020 07:29:06 -0700 (PDT)
> schrieb no-re...@patchew.org:
>
> > Patchew URL:
> > https://patchew.org/QEMU/20200705140315.260514-1-h...@tuxfamily.org/
> [...]
> > === OUTPUT BEGIN ===
> > 1/30 Checking commit b5e3116a3591 (target/avr
Public bug reported:
which gives an error when run on a system that uses dash for /bin/sh.
The problem is at line 6464 which has
if test "$have_keyring" == "yes"
the double equal sign is non-posix bash syntax that isn't accepted by posix
shells like dash. This was added 2020-05-25 according
On Sat, Jul 4, 2020, 16:50 Philippe Mathieu-Daudé wrote:
> Various machine/board/soc models create OHCI device instances
> with the generic QDEV API, and don't need to access USB internals.
>
> Simplify header inclusions by moving the QOM type names into a
> simple header, with no need to include
Hi,
Since v3:
- rebased (was from Feb 2018)
- use named GPIOs
- addressed Peter review comment (adding TYPE_PL181_BUS object)
- convert DPRINF to trace events
Since v2:
- pl181: remove legacy sd_set_cb() (Peter)
Since v1:
- rebased on /master (Peter sdcard reset() patches)
- fix milkymist-mmc fr
Convert the controller to the SDBus API:
- add the a TYPE_PL181_BUS object of type TYPE_SD_BUS,
- adapt the SDBusClass set_inserted/set_readonly handlers
- create the bus in the PL181 controller
- switch legacy sd_*() API to the sdbus_*() API.
Signed-off-by: Philippe Mathieu-Daudé
---
Since v3:
A
pl181_send_command() do a bus transaction (send or receive),
rename it as pl181_do_command().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 649386ec3d..3fc2cdd71a 100644
--- a/hw
Add TODO to use Fifo32 API from "qemu/fifo32.h".
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 3fc2cdd71a..86219c851d 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -57,7 +57,7 @@
From: Alistair Francis
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr,
"\(.*\)\\n"\(.*\))
The 'card is readonly' and 'card inserted' IRQs are not wired.
Add a comment in case someone know where to wire them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/versatilepb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index e596b8170f.
Convert disabled DPRINTF() to trace events and remove ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pl181.c | 26 +-
hw/sd/trace-events | 10 ++
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index f
To make the code easier to manage/review/use, rename the
cardstatus[0] variable as 'card_readonly' and name the GPIO
"card-read-only".
Similarly with cardstatus[1], renamed as 'card_inserted' and
name its GPIO "card-inserted".
Adapt the users accordingly by using the qdev_init_gpio_out_named()
fun
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/integratorcp.c | 13 +
hw/arm/realview.c | 12
hw/
omap_mmc.c is the last device left using the legacy sdcard API.
Move the prototype declarations into a separate header, to
make it clear this is a legacy API.
Reviewed-by: Alistair Francis
Message-Id: <20180216022933.10945-8-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/
sd_data_ready() belongs to the legacy API. As its last user has
been converted to the SDBus API, make it static.
Reviewed-by: Alistair Francis
Message-Id: <20180216022933.10945-7-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sd.h | 1 -
hw/sd/sd.c | 2 +-
2 fi
On Sun, Jul 5, 2020 at 11:16 AM Max Filippov wrote:
> On Sun, Jul 5, 2020 at 10:09 AM Peter Maydell
> wrote:
> > On Thu, 2 Jul 2020 at 19:53, Richard Henderson
> > wrote:
> > > This isn't right. Not so much the gen_io_start portion, but the entire
> > > existence of helper_check_interrupt.
> >
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :)
This series move the SD card creation to the machine/board code.
Regards,
Phil.
Philippe Mathieu-Daudé (4):
hw/lm32/milkymist: Un-inline milkymist_memcard_create()
hw/lm32/milkymist: Comment to re
The 'card is readonly' and 'card inserted' IRQs are not wired.
Add a comment in case someone know where to wire them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index 469e3c4322..1179
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist.c | 13 +
hw/sd/milkymist-memcard.c | 55 +
We don't need to wait until realize() to create the SDBus,
create it in init() directly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/milkymist-memcard.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
index afdb8
As we will modify milkymist_memcard_create(), move it first
to the source file where it is used.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist-hw.h | 11 ---
hw/lm32/milkymist.c| 11 +++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/lm32/mi
On 7/5/20 4:03 PM, Thomas Huth wrote:
> From: Michael Rolnik
>
> Make AVR support buildable.
>
> [AM: Remove word 'Atmel' from filenames and all elements of code]
> Suggested-by: Aleksandar Markovic
> Signed-off-by: Michael Rolnik
> Signed-off-by: Richard Henderson
> Signed-off-by: Aleksandar
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in
This series move the SD card creation to the machine/board code.
Regards,
Phil.
Philippe Mathieu-Daudé (2):
hw/sd/pxa2xx_mmci: Do not create SD card within the SDHCI controller
hw/sd/pxa2xx_mmci: Tri
SDHCI controllers provide a SD Bus to plug SD cards, but don't
come with SD card plugged in :) Let the machine/board object
create and plug the SD cards when required.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/pxa.h | 3 +--
hw/arm/pxa2xx.c | 39 +
Avoid declaring PXA2xxMMCIState local variable, return it directly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/pxa2xx_mmci.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
index 9482b9212d..2996a2ef17 100644
--- a/hw/sd/pxa2x
I tried to maintain the SPI mode because it is useful in
tiny embedded devices, and thought it would be helpful for
the AVR MCUs.
As AVR was blocked, I thought it was wise to deprecate the
SPI mode as users are interested in the faster MMC mode.
Today Thomas surprised me by posting an update of it!
SD cards be used with SPI, SD or MMC protocol.
Unfortunately, maintaining the SPI protocol make improving the
MMC mode very difficult. As of 2020 users are more interested
in using cards with the MMC protocol.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/system/deprecated.rst | 5 +
1 fil
This device duplicate the SPI mode of the sd-card device. The
SPI protocol is better handler in the sd-card, however as the
TYPE_SSI_SLAVE is not an interface, the sd-card can not implement
it easily to be pluggable on a SPI bus. Meanwhile the ssi-sd
device acts as a bridge, but is bitroting. Depre
Since commit 510ef98dca5, qdev_realize() aborts if bus-less
device is realized on a bus. Be kind with the developer by
displaying a hint about what is wrong.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Use errp (bonzini suggestion)
Paolo, I was tempted to check errp is really &error_abort else
In commit d88c42ff2c we added 2 methods: i2c_try_create_slave()
and i2c_realize_and_unref().
Markus noted their name could be improved for consistency [1],
and Peter reported the lack of documentation [2]. Fix that now.
Since v1:
- Addressed Markus review comments
- Added Markus/Corey R-b tags
[1
All the callers of aspeed_i2c_get_bus() have a AspeedI2CState and
cast it to a DeviceState with DEVICE(), then aspeed_i2c_get_bus()
cast the DeviceState to an AspeedI2CState with ASPEED_I2C()...
Simplify aspeed_i2c_get_bus() callers by using AspeedI2CState
argument.
Reviewed-by: Markus Armbruster
The other i2c functions are called i2c_slave_FOO(). Rename as
i2c_slave_realize_and_unref() to be consistent.
Suggested-by: Markus Armbruster
Reviewed-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h | 2 +-
hw/arm/aspeed.c | 10 ++
hw/i2c/core.c
We use "new" names for functions that allocate and initialize
device objects: pci_new(), isa_new(), usb_new().
Let's call this one i2c_slave_new(). Since we have to update
all the callers, also let it return a I2CSlave object.
Suggested-by: Markus Armbruster
Reviewed-by: Markus Armbruster
Signed
In commit d88c42ff2c we added new prototype but neglected to
add their documentation. Fix that.
Reported-by: Peter Maydell
Reviewed-by: Corey Minyard
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h | 48
1 file changed, 48 insertions(
We use "create_simple" names for functions that allocate, initialize,
configure and realize device objects: pci_create_simple(),
isa_create_simple(), usb_create_simple(). For consistency, rename
i2c_create_slave() as i2c_slave_create_simple(). Since we have
to update all the callers, also let it re
The availability of the SERIALIZATION instruction is indicated
by the presence of the CPUID feature flag SERIALIZE, which is
defined as CPUID.(EAX=7,ECX=0):ECX[bit 14].
The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruc
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