On Fri, 21 Feb 2020 11:51:15 -0600
Babu Moger wrote:
> On 2/21/20 11:05 AM, Igor Mammedov wrote:
> > On Thu, 13 Feb 2020 12:16:51 -0600
> > Babu Moger wrote:
> >
> >> Initialize all the parameters in one function init_topo_info.
> >
> > is it possible to squash it in 2/16
> >
> Sure. We
On Thu, 13 Feb 2020 12:17:04 -0600
Babu Moger wrote:
> Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg.
> This is required to build EPYC mode topology.
>
> Signed-off-by: Babu Moger
> ---
> hw/i386/pc.c |1 +
> hw/i386/x86.c |2 ++
>
On 2020/2/21 22:09, Peter Maydell wrote:
> On Mon, 17 Feb 2020 at 13:10, Dongjiu Geng wrote:
>>
>> In the ARMv8 platform, the CPU error types includes synchronous external
>> abort(SEA) and SError Interrupt (SEI). If exception happens in guest, host
>> does not know the detailed information of g
On Thu, 13 Feb 2020 12:16:58 -0600
Babu Moger wrote:
> Store the smp sockets in CpuTopology. The socket information required to
> build the apic id in EPYC mode. Right now socket information is not passed
> to down when decoding the apic id. Add the socket information here.
>
> Signed-off-by: B
It works with virsh device-attach. Thank you very much.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1846451
Title:
K800 keyboard no longer works when attached to a VM
Status in QEMU:
Fix Relea
On 2/24/20 5:16 AM, Gavin Shan wrote:
This uses TYPE_PL011 when creating the serial port, to make the code
a bit more atomatic.
Do you mean aUtomatic? I'm not sure this automate the code, but using
the TYPE definition is definitively cleaner.
With description fixed:
Reviewed-by: Philippe Mat
Hi Igor,
On 2/19/20 5:08 PM, Igor Mammedov wrote:
[...]
Series removes ad hoc RAM allocation API (memory_region_allocate_system_memory)
and consolidates it around hostmem backend. It allows to
* resolve conflicts between global -mem-prealloc and hostmem's "policy" option
fixing premature a
On Thu, 13 Feb 2020 12:17:18 -0600
Babu Moger wrote:
> These functions add support for building EPYC mode topology given the smp
> details like numa nodes, cores, threads and sockets.
>
> The new apic id decoding is mostly similar to current apic id decoding
> except that it adds a new field llc
On 2/23/20 2:27 PM, Yoshinori Sato wrote:
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
index 6cf7936201..4ee6647728 100644
--- a/hw/rx/rx-virt.c
+++ b/hw/rx/rx-virt.c
@@ -90,8 +90,
On Thu, 13 Feb 2020 12:17:25 -0600
Babu Moger wrote:
> Use the new functions from topology.h and delete the unused code. Given the
> sockets, nodes, cores and threads, the new functions generate apic id for EPYC
> mode. Removes all the hardcoded values.
>
> Signed-off-by: Babu Moger
modulo MAX
On 2/22/20 11:19 PM, Niek Linnenbank wrote:
Hey Philippe,
Very nice to see that the Raspberry 1 will be supported again, thanks
for contributing this!
I tried to bring up the machine using raspbian 2019-09-26. It ran
throught the early kernel initialisation
but for me it gets stuck at this
On 21.02.20 19:04, Peter Xu wrote:
> On Fri, Feb 21, 2020 at 05:41:51PM +0100, David Hildenbrand wrote:
>> I was now able to actually test resizing while migrating. I am using the
>> prototype of virtio-mem to test (which also makes use of resizable
>> allocations). Things I was able to reproduce:
On Thu, Feb 20, 2020 at 02:52:45PM -0500, Cleber Rosa wrote:
> On Thu, Feb 20, 2020 at 01:49:40PM -0300, Wainer dos Santos Moschetta wrote:
> > On 2/19/20 11:06 PM, Cleber Rosa wrote:
> > > +
> > > +def test_virt_tcg(self):
> > > +"""
> > > +:avocado: tags=accel:tcg
> > > +
Hi Peter,
Will send V3 for below comments.
In v2 I may have confused with functionality of group priority interrupt bits.
Now things look clear. Thanks.
Regards,
Sai Pavan
> -Original Message-
> From: Peter Maydell
> Sent: Friday, February 21, 2020 9:00 PM
> To: Sai Pavan Boddu
> Cc:
This patch series implements the mask for unimplemented priority bits in
arm-gic. Which will return the expected number of priority bits on read.
Changes for V2:
Followed gicv3 code for defining mask for unimplemented bits
Hardcoded num priority bits for A9 and ARM11MPCore boards
Changes f
All A9 CPUs have a GIC with 5 bits of priority.
Signed-off-by: Sai Pavan Boddu
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
---
hw/cpu/a9mpcore.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 1f8bc8a..b4f6a7e 100644
--- a/hw/cpu/a
ARM11MPCore GIC is implemented with 4 priority bits.
Signed-off-by: Sai Pavan Boddu
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
---
hw/cpu/arm11mpcore.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 2e3e87c..ab9fadb 100644
Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits
are read as zeros(RAZ).
Signed-off-by: Sai Pavan Boddu
Suggested-by: Peter Maydell
---
hw/intc/arm_gic.c| 33 +++--
hw/intc/arm_gic_common.c | 1 +
include/hw/intc/arm_gi
An HTTP object store of my acquaintance returns "accept-ranges: bytes"
(all lower case) as a header, causing the QEMU curl backend to refuse
to talk to it. RFC 7230 says that HTTP headers are case insensitive,
so update the curl backend accordingly.
At the same time, allow for arbitrary white spac
RFC 7230 section 3.2 indicates that whitespace is permitted between
the field name and field value and after the field value.
Signed-off-by: David Edmondson
---
block/curl.c | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/block/curl.c b/block/
Nice catch. You are right. I was a bit confused after looking at current
xvisor and KVM port. They are delegating S mode interrupts to VS mode, as
per my understanding after looking at
https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c
line no. 34. I will see if there is
RFC 7230 section 3.2 indicates that HTTP header field names are case
insensitive.
Signed-off-by: David Edmondson
---
block/curl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/block/curl.c b/block/curl.c
index f9ffb7f4e2bf..6e325901dc68 100644
--- a/block/curl.c
+++ b/
Do not leave stale linked list pointers around after removal. It's
safer to set them to NULL so that use-after-removal results in an
immediate segfault.
The RCU queue removal macros are unchanged since nodes may still be
traversed after removal.
Suggested-by: Paolo Bonzini
Signed-off-by: Stefan
QLIST_REMOVE() and friends leave dangling linked list pointers in the node that
was removed. This makes it impossible to decide whether a node is currently in
a list or not. It also makes debugging harder.
Based-on: 20200222085030.1760640-1-stefa...@redhat.com
("[PULL 00/31] Block patc
QLIST_SAFE_REMOVE() is confusing here because the node must be on the
list. We actually just wanted to clear the linked list pointers when
removing it from the list. QLIST_REMOVE() now does this, so switch to
it.
Suggested-by: Paolo Bonzini
Signed-off-by: Stefan Hajnoczi
---
util/aio-posix.c
On 19.02.20 23:46, Peter Xu wrote:
> On Wed, Feb 12, 2020 at 02:42:46PM +0100, David Hildenbrand wrote:
>> Factor it out and add a comment.
>>
>> Reviewed-by: Igor Kotrasinski
>> Acked-by: Murilo Opsfelder Araujo
>> Reviewed-by: Richard Henderson
>> Cc: "Michael S. Tsirkin"
>> Cc: Murilo Opsfel
On 19.02.20 23:49, Peter Xu wrote:
> On Wed, Feb 12, 2020 at 02:42:48PM +0100, David Hildenbrand wrote:
>> We want to populate memory within a reserved memory region. Let's factor
>> that out.
>>
>> Reviewed-by: Richard Henderson
>> Acked-by: Murilo Opsfelder Araujo
>> Cc: Igor Kotrasinski
>> Cc
Patchew URL:
https://patchew.org/QEMU/20200224103406.1894923-1-stefa...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/2] qemu/queue.h: clear linked list pointers on remove
Message-id: 20200224103406.1894923-1-ste
On 24.02.20 11:50, David Hildenbrand wrote:
> On 19.02.20 23:46, Peter Xu wrote:
>> On Wed, Feb 12, 2020 at 02:42:46PM +0100, David Hildenbrand wrote:
>>> Factor it out and add a comment.
>>>
>>> Reviewed-by: Igor Kotrasinski
>>> Acked-by: Murilo Opsfelder Araujo
>>> Reviewed-by: Richard Henderso
On 19.02.20 23:50, Peter Xu wrote:
> On Wed, Feb 12, 2020 at 02:42:49PM +0100, David Hildenbrand wrote:
>> @@ -178,13 +183,15 @@ void *qemu_ram_mmap(int fd,
>> size_t offset, total;
>> void *ptr, *guardptr;
>>
>> +g_assert(QEMU_IS_ALIGNED(size, pagesize));
>
> (NOTE: assertion is f
On Sat, Feb 22, 2020 at 05:23:38 -0600, Eric Blake wrote:
> In the past, we have had CVEs caused by qemu probing one image type
> when an image started out as another but the guest was able to modify
> content. The solution to those CVEs was to encode backing format
> information into qcow2, to en
Hi,
Yes, indeed this has to be fixed in QEMU, Xvisor and KVM.
Before fixing Xvisor and KVM, we have to first fix this in QEMU.
For Xvisor RISC-V, feel free to send patch to xvisor-de...@googlegroups.com
For KVM RISC-V, I will update it in v11 patch series and KVM RISC-V git repo as
well.
Regar
On 12.10.19 01:39, John Snow wrote:
> Just caught up with the discussion.
>
> It looks like Thomas took my 1/5; so I'll respin on top of his "[PATCH
> 0/5] Enable more iotests during "make check-block" series to catch those
> improvements as they stand.
Any updates on this? :)
Max
signature.a
On Wed, 19 Feb 2020 10:21:05 +1100
David Gibson wrote:
> On Fri, Feb 14, 2020 at 07:19:00PM +0100, Greg Kurz wrote:
> > On Fri, 14 Feb 2020 09:28:35 +1100
> > David Gibson wrote:
> >
> > > On Thu, Feb 13, 2020 at 04:38:38PM +0100, Greg Kurz wrote:
> > > > Until the CAS negotiation is over, an H
On Fri, Feb 21, 2020 at 12:14:18PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/21/20 11:56 AM, Stefan Hajnoczi wrote:
> > On Tue, Feb 11, 2020 at 10:51:19AM +, Stefan Hajnoczi wrote:
> > > On Mon, Feb 10, 2020 at 08:58:28PM +0100, Philippe Mathieu-Daudé wrote:
> >
> > Ping?
> >
> > QEMU has b
On Sat, Feb 22, 2020 at 01:13:32AM -0800, no-re...@patchew.org wrote:
> This series seems to have some coding style problems. See output below for
> more information:
The checkpatch warnings are benign:
* The include/qemu/queue.h coding style warnings are because this is
code imported to QEMU
On Mon, 24 Feb 2020 09:45:11 +0100
Philippe Mathieu-Daudé wrote:
> Hi Igor,
>
> On 2/19/20 5:08 PM, Igor Mammedov wrote:
> [...]
> > Series removes ad hoc RAM allocation API
> > (memory_region_allocate_system_memory)
> > and consolidates it around hostmem backend. It allows to
> > * resolve c
On Sat, Feb 22, 2020 at 05:34:29AM -0600, Eric Blake wrote:
> On 2/22/20 2:50 AM, Stefan Hajnoczi wrote:
> > From: Alexander Bulekov
> >
> > fork() is a simple way to ensure that state does not leak in between
> > fuzzing runs. Unfortunately, the fuzzer mutation engine relies on
> > bitmaps which
On Mon, Feb 24, 2020 at 12:13:34PM +0800, pannengy...@huawei.com wrote:
> From: Pan Nengyuan
>
> This series patch fix memleaks when detaching vhost-user-blk device.
> 1. use old virtio_del_queue to fix memleaks, it's easier for stable branches
> to merge.
>As the discussion in
> https://li
On Sat, Feb 22, 2020 at 05:23:41 -0600, Eric Blake wrote:
> Creating an image that requires format probing of the backing image is
> inherently unsafe (we've had several CVEs over the years based on
> probes leaking information to the guest on a subsequent boot). If our
> probing algorithm ever ch
On 2/24/20 12:33 PM, Igor Mammedov wrote:
On Mon, 24 Feb 2020 09:45:11 +0100
Philippe Mathieu-Daudé wrote:
Hi Igor,
On 2/19/20 5:08 PM, Igor Mammedov wrote:
[...]
Series removes ad hoc RAM allocation API (memory_region_allocate_system_memory)
and consolidates it around hostmem backend. It al
On Mon, Feb 24, 2020 at 02:55:33AM -0800, no-re...@patchew.org wrote:
> === OUTPUT BEGIN ===
> 1/2 Checking commit f913b2430ad3 (qemu/queue.h: clear linked list pointers on
> remove)
> ERROR: do not use assignment in if condition
> #65: FILE: include/qemu/queue.h:314:
> +if (((head)->sqh_first
On Mon, Feb 24, 2020 at 12:01:45 +0100, Peter Krempa wrote:
> On Sat, Feb 22, 2020 at 05:23:38 -0600, Eric Blake wrote:
[...]
> > libvirt HAS to use blockdev-open on the backing chain and supply a
> > backing format there, and thus has to probe images. If libvirt ever
> > probes differently than
On 2/24/20 11:34 AM, Stefan Hajnoczi wrote:
Do not leave stale linked list pointers around after removal. It's
safer to set them to NULL so that use-after-removal results in an
immediate segfault.
The RCU queue removal macros are unchanged since nodes may still be
traversed after removal.
Sugg
From: Aleksandar Markovic
This patch is just a follow up to James' wish to be releived
of QEMU KVM/MIPS mainatainer duties. Many thanks to James for
his substantial contributions to QEMU for MIPS made over many
years, and not only in KVM area.
CC: James Hogan
CC: Christian Borntraeger
CC: Paol
From: Aleksandar Markovic
Reactivate MIPS KVM maintainership with a modest goal of keeping
the support alive, checking common KVM code changes against MIPS
functionality, etc. (hence the status "Odd Fixes"), with hope that
this component will be fully maintained at some further, but not
distant p
On 2/24/20 12:39 PM, Stefan Hajnoczi wrote:
On Mon, Feb 24, 2020 at 02:55:33AM -0800, no-re...@patchew.org wrote:
=== OUTPUT BEGIN ===
1/2 Checking commit f913b2430ad3 (qemu/queue.h: clear linked list pointers on
remove)
ERROR: do not use assignment in if condition
#65: FILE: include/qemu/queue
On 24.02.20 12:50, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Reactivate MIPS KVM maintainership with a modest goal of keeping
> the support alive, checking common KVM code changes against MIPS
> functionality, etc. (hence the status "Odd Fixes"), with hope that
> this componen
Hello Qemu development community members,
I have created a virtual device in Qemu.
Now I want to run Qemu with the virtual device,so how to do it ?
Thanks,
Priyamvad Acharya
On 2/24/20 12:55 PM, Christian Borntraeger wrote:
On 24.02.20 12:50, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Reactivate MIPS KVM maintainership with a modest goal of keeping
the support alive, checking common KVM code changes against MIPS
functionality, etc. (hence the status "Odd
On Mon, Feb 24, 2020 at 1:09 PM Philippe Mathieu-Daudé
wrote:
> On 2/24/20 12:55 PM, Christian Borntraeger wrote:
> > On 24.02.20 12:50, Aleksandar Markovic wrote:
> >> From: Aleksandar Markovic
> >>
> >> Reactivate MIPS KVM maintainership with a modest goal of keeping
> >> the support alive, che
On 2/12/20 9:27 PM, Philippe Mathieu-Daudé wrote:
We link with VirGL in our debian-amd64 (cross-host) docker image.
This series includes few fixes to keep testing it.
ping?
Philippe Mathieu-Daudé (3):
tests/docker: Update VirGL git repository URL
tests/docker: Remove obsolete VirGL --
> Philippe Mathieu-Daudé wrote:
> > Aleksandar Markovic wrote:
> >> From: Aleksandar Markovic
> >>
> >> Reactivate MIPS KVM maintainership with a modest goal of keeping
> >> the support alive, checking common KVM code changes against MIPS
> >> functionality, etc. (hence the status "Odd Fixes"), w
On 2/12/20 9:27 PM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
We often run Linux kernels to test QEMU. We sometimes need
to build them manually to use non-default features. We only
miss the tiny 'bc' tool.
The ncurses library is helpful to run 'make menuconfig'.
Finally, gdb-
On 12/3/19 2:41 PM, Alex Bennée wrote:
Cleber Rosa writes:
On Mon, Aug 19, 2019 at 01:18:26AM +0200, Philippe Mathieu-Daudé wrote:
Add a runner script to be able to run acceptance tests within
Docker images. We can now reproduce Travis CI builds locally (and
debug them!).
Signed-off-by: Phil
On 2/24/20 1:20 PM, Aleksandar Markovic wrote:
> Philippe Mathieu-Daudé wrote:
> > Aleksandar Markovic wrote:
> >> From: Aleksandar Markovic
> >>
> >> Reactivate MIPS KVM maintainership with a modest goal of keeping
> >> the support alive, checking common KVM code changes against MIPS
>
On Sat, Feb 15, 2020 at 08:59:28AM +, miaoyubo wrote:
>
> > -Original Message-
> > From: Daniel P. Berrangé [mailto:berra...@redhat.com]
> > Sent: Friday, February 14, 2020 6:25 PM
> > To: miaoyubo
> > Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com;
> > imamm...@redhat.com; qe
On 24/02/20 12:50, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> This patch is just a follow up to James' wish to be releived
> of QEMU KVM/MIPS mainatainer duties. Many thanks to James for
> his substantial contributions to QEMU for MIPS made over many
> years, and not only in KVM a
On 22/02/20 13:25, Chen Gang wrote:
> On 2020/2/22 下午3:37, Paolo Bonzini wrote:
>> On 22/02/20 03:10, Chen Gang wrote:
>>> Set C1 to 1 if stack overflow occurred; set to 0 otherwise".
>>>
>>> In helper_fxam_ST0, I guess, we need "env->fpus |= 0x200" (but I don't
>>> know wheter it will be conflict
> Philippe Mathieu-Daudé wrote:
> > >> diff --git a/MAINTAINERS b/MAINTAINERS
> > >> index b0728c8..9cc55d5 100644
> > >> --- a/MAINTAINERS
> > >> +++ b/MAINTAINERS
> > >> @@ -365,8 +365,8 @@ S: Maintained
> > >> F: target/arm/kvm.c
> > >>
> > >> MIPS KVM CPUs
> > >> -R: Aleksandar Rikalo
>
On Sat, 22 Feb 2020 at 08:50, Stefan Hajnoczi wrote:
>
> The following changes since commit 9ac5df20f51fabcba0d902025df4bd7ea987c158:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200221-1' into staging (2020-02-21
> 16:18:38 +)
>
> are available in the Git re
Am 24.02.2020 um 13:35 hat Stefan Ring geschrieben:
> On Thu, Feb 20, 2020 at 10:19 AM Stefan Ring wrote:
> >
> > Hi,
> >
> > I have a very curious problem on an oVirt-like virtualization host
> > whose storage lives on gluster (as qcow2).
> >
> > The problem is that of the writes done by ZFS, who
On Wed, Feb 19, 2020 at 13:12:53 -0600, Eric Blake wrote:
> [adding qemu]
Adding Daniel as he objected to qemu-img.
>
> On 2/19/20 12:57 PM, Peter Krempa wrote:
[...]
> > Additionally I think that we could just get rid of the copy of the image
> > detection copy in libvirt and replace it by in
On Fri, Feb 07, 2020 at 10:46:19AM +, Stefan Hajnoczi wrote:
> The virtqueue code sets up MemoryRegionCaches to access the virtqueue
> guest RAM data structures. The code currently assumes that
> VRingMemoryRegionCaches is initialized before device emulation code
> accesses the virtqueue. An
On Mon, Feb 24, 2020 at 01:35:54PM +, Stefan Hajnoczi wrote:
> On Fri, Feb 07, 2020 at 10:46:19AM +, Stefan Hajnoczi wrote:
> > The virtqueue code sets up MemoryRegionCaches to access the virtqueue
> > guest RAM data structures. The code currently assumes that
> > VRingMemoryRegionCaches i
The Intel PT packets which contain IP payloads will have LIP values, and it
will include the CS base component if the CPUID.(EAX=14H,ECX=0H).ECX.[bit31]
is set. But it will disabled the Intel PT in kvm guest because of the need
of live migration safe(c078ca9 i386: Disable Intel PT if packets IP pay
After expose all the capabilities of Intel PT to KVM guest, the guest Intel
PT CPUID information may difference with same guest cpu model on differnt
hardware. It will block the live migration. This patch will mark the Intel
PT feature as unmigratable.
Signed-off-by: Luwei Kang
---
target/i386/c
The Intel PT feature includes some sub-features(CPUID.(EAX=14H,ECX=0H)) and
these sub-features are different on different HW platforms. To make the live
migration safety(get the same CPUID info with same cpu model on different HW
platform), the current Intel PT CPUID information is set to a constan
Add two GitLab jobs to build the OpenSBI firmware binaries.
The first job builds a Docker image with the packages requisite
to build OpenSBI, and stores this image in the GitLab registry.
The second job pulls the image from the registry and builds the
OpenSBI firmware binaries.
The docker image i
This series advances the roms/opensbi submodule to the v0.6 release,
and builds and captures platform firmware binaries from that release.
A 32-bit sifive_u bios image has also been added, so that we can have
32-bit test coverage for SiFive specific drivers that cannot be done
with the 'virt' ma
To make Intel PT live migration safe and get same CPUID information
with same CPU model on diffrent host. CPUID[14] is set to constant
value in "e37a5c7 i386: Add Intel Processor Trace feature support".
But it will block the new features of Intel PT. This patch will
remove this limitation and expos
Upgrade OpenSBI from v0.5 to v0.6 and the pre-built bios images.
The v0.6 release includes the following commits:
dd8ef28 firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils
98f4a20 firmware: Introduce relocation lottery
f728a0b include: Sync-up encoding with priv v1.12-draft and
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 6 ++
Although the real world SiFive HiFive Unleashed board is a 64-bit
hardware configuration, with QEMU it is possible to test 32-bit
configuration with the same hardware features.
This updates the roms Makefile to add the build rules for creating
the 32-bit OpenSBI firmware image for sifive_u machine
On Mon, 24 Feb 2020 17:51:30 +0900,
Philippe Mathieu-Daudé wrote:
>
> On 2/23/20 2:27 PM, Yoshinori Sato wrote:
> > Signed-off-by: Yoshinori Sato
> > ---
> > hw/rx/rx-virt.c | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
On Mon, Feb 24, 2020 at 2:56 PM Yoshinori Sato
wrote:
> On Mon, 24 Feb 2020 17:51:30 +0900,
> Philippe Mathieu-Daudé wrote:
> >
> > On 2/23/20 2:27 PM, Yoshinori Sato wrote:
> > > Signed-off-by: Yoshinori Sato
> > > ---
> > > hw/rx/rx-virt.c | 6 --
> > > 1 file changed, 4 insertions(+), 2
** Changed in: qemu
Status: New => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1829242
Title:
qemu on windows host exits after savevm command
Status in QEMU:
Fix Committed
On 20.02.20 13:56, Janosch Frank wrote:
> When a guest has saved a ipib of type 5 and calls diagnose308 with
> subcode 10, we have to setup the protected processing environment via
> Ultravisor calls. The calls are done by KVM and are exposed via an
> API.
>
> The following steps are necessary:
On Monday, February 24, 2020 7:57:03 AM -03 David Hildenbrand wrote:
> On 24.02.20 11:50, David Hildenbrand wrote:
> > On 19.02.20 23:46, Peter Xu wrote:
> >> On Wed, Feb 12, 2020 at 02:42:46PM +0100, David Hildenbrand wrote:
> >>> Factor it out and add a comment.
> >>>
> >>> Reviewed-by: Igor Kotr
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-10-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/bitops.h | 38 +
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-22-ys...@users.sourceforge.jp>
Tested-by
.
Squashed v19 changes.
Changes for v19.
Follow tcg changes.
Cleanup cpu.c.
simplify rx_cpu_class_by_name and rx_load_image move to rx-virt.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20200224
Testing binaries bellow.
u-boot
Download - https://osdn.net/users
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-18-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINER
From: Philippe Mathieu-Daudé
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-11-ys...@users.sourceforge.jp>
Tested-by: Philippe Math
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <201906070
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-1
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by: Philip
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t arch:rx
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-4-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use newer QOM style, split cpu-qom.h, restrict access to
extable a
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-23-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-3-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-t
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signe
From: Philippe Mathieu-Daudé
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/rx/
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-17-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-9-ys...@users.sourceforge.jp>
Signed-off-b
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-5-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
include/disas/dis-asm.h |5 +
target/rx/disas.c | 1480 +
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-8-ys...@users.sourcef
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-6-ys...@users.sourcefo
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philip
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