On Tue, Oct 15, 2019 at 01:19:33PM -0600, Alex Williamson wrote:
On Fri, 11 Oct 2019 13:20:06 +0200
Jens Freimann wrote:
This adds support for hiding a device to the qbus and qdev APIs. The
first user of this will be the virtio-net failover feature but the API
introduced with this patch could
On Tue, Oct 15, 2019 at 11:50:08AM +0100, Dr. David Alan Gilbert wrote:
* Jens Freimann (jfreim...@redhat.com) wrote:
On Fri, Oct 11, 2019 at 06:11:33PM +0100, Dr. David Alan Gilbert wrote:
> * Jens Freimann (jfreim...@redhat.com) wrote:
> > This patch adds a new migration state called wait-unpl
On Tue 15 Oct 2019 06:05:23 PM CEST, Eric Blake wrote:
>> 6356 5548 4740 3932 3124 2316 15 8 7 0
>>
>> <-> <->
>> subcluste
On 16.10.19 02:19, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20191015142729.18123-1-mre...@redhat.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Subject: [PATCH v2 00/21] iotests: Allow ./chec
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index c5c9d4900e..d399dcba52 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -92,6 +92,10 @@ config Q35
> select SMBIOS
> select FW_CFG_DMA
>
> +config MICROVM
> +bool
Missing:
select ISA_BUS
select APIC
On Wed, Oct 09, 2019 at 03:01:15PM +0100, Beata Michalska wrote:
> On Tue, 1 Oct 2019 at 14:04, Andrew Jones wrote:
> >
> > Introduce cpu properties to give fine control over SVE vector lengths.
> > We introduce a property for each valid length up to the current
> > maximum supported, which is 204
On 16.10.2019 08:11, Thomas Huth wrote:
On 16/10/2019 05.00, Eduardo Habkost wrote:
On Tue, Sep 17, 2019 at 08:31:40PM -0300, Eduardo Habkost wrote:
On Mon, Jul 01, 2019 at 07:25:27PM -0300, Eduardo Habkost wrote:
On Mon, Jun 10, 2019 at 01:58:50PM +0100, Peter Maydell wrote:
[...]
The confi
This patch adds support for blkreplay driver to the blockdev options.
Now blkreplay can be used with -blockdev command line option
in the following format:
-blockdev driver=blkreplay,image=file-node-name,node-name=replay-node-name
This option makes possible implementation of the better command
lin
Peter Xu wrote:
> Define the new macro VMSTATE_INSTANCE_ID_ANY for callers who wants to
> auto-generate the vmstate instance ID. Previously it was hard coded
> as -1 instead of this macro. It helps to change this default value in
> the follow up patches. No functional change.
>
> Signed-off-by:
Peter Xu wrote:
> It was always used as 32bit, so define it as used to be clear.
> Instead of using -1 as the auto-gen magic value, we switch to
> UINT32_MAX. We also make sure that we don't auto-gen this value to
> avoid overflowed instance IDs without being noticed.
>
> Suggested-by: Juan Quint
Peter Xu wrote:
> Migration is silently broken now with x2apic config like this:
>
> -smp 200,maxcpus=288,sockets=2,cores=72,threads=2 \
> -device intel-iommu,intremap=on,eim=on
>
> After migration, the guest kernel could hang at anything, due to
> x2apic bit not migrated correctly in IA
The Aspeed I2C controller can operate in different transfer modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer multiple
bytes in the same command sequence.
Each SoC h
Hello,
The Aspeed I2C controller can operate in three different transfer
modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer multiple
bytes in the same command sequenc
The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.
Signed-off-by: Cédric Le Goater
---
include/hw/i2c/aspeed_i2c.h | 3 +++
hw/i2c/aspeed_i2c.c | 37 +
2 files changed, 40 insertions(+)
dif
Signed-off-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 93 ++---
hw/i2c/trace-events | 9 +
2 files changed, 89 insertions(+), 13 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 030d9c56be65..2da04a4bff30 100644
--- a/hw/i
Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_
Now that Arm CPUs have advertised features lets add tests to ensure
we maintain their expected availability with and without KVM.
Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
---
tests/Makefile.include | 5 +-
tests/arm-cpu-features.c | 242 +++
2
Since Linux kernel v5.2-rc1 KVM has support for enabling SVE in guests.
This series provides the QEMU bits for that enablement. First, we
select existing CPU properties representing features we want to
advertise in addition to the SVE vector lengths and prepare
them for a qmp query. Then we introdu
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA tr
Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
a CPU property") we can disable the 'max' cpu model's VFP and neon
features, but there's no way to disable SVE. Add the 'sve=on|off'
property to give it that flexibility. We also rename
cpu_max_get/set_sve_vq to cpu_max_get/set
kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
parameter. Rather than just using it as an output parameter to
pass back the preferred target, use it also as an input parameter,
allowing a caller to pass a selected target if they wish and to
also pass cpu features. If the caller doe
Add support for the query-cpu-model-expansion QMP command to Arm. We
do this selectively, only exposing CPU properties which represent
optional CPU features which the user may want to enable/disable.
Additionally we restrict the list of queryable cpu models to 'max',
'host', or the current type whe
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates t
These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
swabbing is different than it is for fpsmid because the vector format
is a little-endian stream of words.
Signed-off-by: Andrew Jones
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
---
target/arm/kvm64.c | 183
Enable SVE in the KVM guest when the 'max' cpu type is configured
and KVM supports it. KVM SVE requires use of the new finalize
vcpu ioctl, so we add that now too. For starters SVE can only be
turned on or off, getting all vector lengths the host CPU supports
when on. We'll add the other SVE CPU pr
Am 16.10.2019 um 10:40 hat Pavel Dovgalyuk geschrieben:
> This patch adds support for blkreplay driver to the blockdev options.
> Now blkreplay can be used with -blockdev command line option
> in the following format:
> -blockdev driver=blkreplay,image=file-node-name,node-name=replay-node-name
>
>
Extend the SVE vq map initialization and validation with KVM's
supported vector lengths when KVM is enabled. In order to determine
and select supported lengths we add two new KVM functions for getting
and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.
This patch has been co-authored with Richa
Allow cpu 'host' to enable SVE when it's available, unless the
user chooses to disable it with the added 'sve=off' cpu property.
Also give the user the ability to select vector lengths with the
sve properties. We don't adopt 'max' cpu's other sve property,
sve-max-vq, because that property is diffi
Define the board with 1 GiB of RAM but some boards can have up to 2
GiB.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
Changes since AST2600 patchset:
- lowered the RAM size to 1 GiB as it was breaking the tests on some
hosts.
include/hw/arm/aspeed.h | 1 +
hw/arm/aspee
On Thu, Oct 10, 2019 at 01:33:02PM -0400, Richard Henderson wrote:
> On 10/10/19 2:16 AM, Andrew Jones wrote:
> >> It might be best to avoid the ifdef altogether:
> >>
> >> for (i = 0; i < 32; ++i) {
> >> uint64_t *d = (uint64_t *)&buf[sve_zreg_offset(vq, i)];
> >> for (j = 0; j
* Peter Xu (pet...@redhat.com) wrote:
> Before finally register one SaveStateEntry, we detect for duplicated
> entries. This could be helpful to notify us asap instead of get
> silent migration failures which could be hard to diagnose.
>
> For example, this patch will generate a message like this
On 10/16/19 9:46 AM, Paolo Bonzini wrote:
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..d399dcba52 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -92,6 +92,10 @@ config Q35
select SMBIOS
select FW_CFG_DMA
+config MICROVM
+bool
Missing:
selec
On 16/10/19 11:26, Philippe Mathieu-Daudé wrote:
> On 10/16/19 9:46 AM, Paolo Bonzini wrote:
>>
>>> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
>>> index c5c9d4900e..d399dcba52 100644
>>> --- a/hw/i386/Kconfig
>>> +++ b/hw/i386/Kconfig
>>> @@ -92,6 +92,10 @@ config Q35
>>> select SMBIOS
>>
On Dienstag, 15. Oktober 2019 11:20:39 CEST Greg Kurz wrote:
> On Tue, 08 Oct 2019 14:05:28 +0200
>
> Christian Schoenebeck wrote:
> > I wonder though whether virtio-fs suffers from the same file ID collisions
> > problem when sharing multiple file systems.
>
> I gave a try and it seems that vir
On 9/26/19 7:34 PM, Philippe Mathieu-Daudé wrote:
> Hi,
>
> I previously posted a RFC for the Raspberry Pi 4:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg642241.html
> and got it almost working (boots Linux kernel to userland, sadly
> I'm still having timeout issues with the eMMC block
Peter Xu wrote:
> Before finally register one SaveStateEntry, we detect for duplicated
> entries. This could be helpful to notify us asap instead of get
> silent migration failures which could be hard to diagnose.
>
> For example, this patch will generate a message like this (if without
> previou
Put QOM and main struct definition in a separate header file, so it
can be accessed from other components.
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
---
include/hw/virtio/virtio-mmio.h | 73 +++
microvm is a machine type inspired by Firecracker and constructed
after its machine model.
It's a minimalist machine type without PCI nor ACPI support, designed
for short-lived guests. microvm also establishes a baseline for
benchmarking and optimizing both QEMU and guest operating systems,
since
Fix code style issues detected by checkpatch.pl on functions that will
be moved out to x86.c.
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 53
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git
Add a new "microvm" section under "X86 Machines" with the new files
related to this machine type.
Signed-off-by: Sergio Lopez
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINE
The following functions are named *pc* but are not PC-machine specific
but generic to the X86 architecture, rename them:
load_linux -> x86_load_linux
pc_new_cpu -> x86_new_cpu
pc_cpus_init -> x86_cpus_init
pc_cpu_index_to_props -> x86_cpu_
Follow checkpatch.pl recommendation and replace the use of strtol with
qemu_strtoui in x86_load_linux().
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index
qboot is a minimalist x86 firmware for booting Linux kernels. It does
the mininum amount of work required for the task, and it's able to
boot both PVH images and bzImages without relying on option roms.
This characteristics make it an ideal companion for the microvm
machine type.
Signed-off-by: S
Follow checkpatch.pl recommendation and avoid an assignment in if
condition in x86_load_linux().
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c8608b8
Document the new microvm machine type.
Signed-off-by: Sergio Lopez
Reviewed-by: Michael S. Tsirkin
---
docs/microvm.rst | 98
1 file changed, 98 insertions(+)
create mode 100644 docs/microvm.rst
diff --git a/docs/microvm.rst b/docs/microvm.rst
Follow checkpatch.pl recommendation and remove commented out code from
x86_load_linux().
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 90c2263a33..612bfe9c95 10
This allows to alter the contents of an already added item.
Signed-off-by: Sergio Lopez
Reviewed-by: Michael S. Tsirkin
---
include/hw/nvram/fw_cfg.h | 42 +++
hw/nvram/fw_cfg.c | 29 +++
2 files changed, 71 insertions(+)
diff
Move x86 functions that will be shared between PC and non-PC machine
types to x86.c, along with their helpers.
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Stefano Garzarella
Reviewed-by: Michael S. Tsirkin
---
include/hw/i386
Split up PCMachineState and PCMachineClass and derive X86MachineState
and X86MachineClass from them. This allows sharing code with non-PC
x86 machine types.
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
---
in
microvm is a machine type inspired by Firecracker and constructed
after its machine model.
It's a minimalist machine type without PCI nor ACPI support, designed
for short-lived guests. microvm also establishes a baseline for
benchmarking and optimizing both QEMU and guest operating systems,
since
As a last step into splitting PCMachineState and deriving
X86MachineState from it, make the functions previously extracted from
pc.c to x86.c independent from PCMachineState, using X86MachineState
instead.
Signed-off-by: Sergio Lopez
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathie
In apic_accept_pic_intr(), reject PIC interruptions if a i8259 PIC has
not been instantiated (isa_pic == NULL).
Suggested-by: Paolo Bonzini
Signed-off-by: Sergio Lopez
Reviewed-by: Michael S. Tsirkin
---
hw/intc/apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc
setxattr to directry fails because lo_setxattr (and lo_remove_xattr)
tries to open any file with O_RDWR even if it is a directory.
Since O_RDONLY is enough for the operation, change O_RDWR flag to
O_RDONLY to fix the problem.
Signed-off-by: Misono Tomohiro
---
contrib/virtiofsd/passthrough_ll.c
Patchew URL:
https://patchew.org/QEMU/20191016012432.22731-1-richardw.y...@linux.intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH] checkpatch: sugguest to use qemu_real_host_page_size instead
of getpagesize() or sysco
Hello,
I test xattr operation on virtiofs using xfstest generic/062
(with -o xattr option and XFS backend) and see some problems.
These patches fixes the two of the problems.
The remaining problems are:
1. we cannot xattr to block device created by mknod
which does not have actual device (s
I see xfstest generic/062 causes process hang because of xattr operation to
FIFO created by mknod. The problem is that virtiofsd opens any files
with only O_RDWR or O_RDONLY flags for xattr operation, and therefore
if a file is FIFO, open may not return.
Since O_NONBLOCK flag has no effect to regu
Hello people,
On 15/10/2019 18:57, Philippe Mathieu-Daudé wrote:
> Hi Joshua,
>
> On 10/15/19 3:17 PM, Joshua Shaffer wrote:
>> Hello,
>>
>> I've been using the LEON3 port of qemu, and am wondering if anyone has
>> touched the networking setup for such since the thread here:
>> https://lists.rt
Hi,
Almost a year since 1.12.0 was tagged (Nov 17th to be exact),
time to plan the 1.13 release I think ...
How about freeze in a week or two, release by mid-november?
Pending stuff I'm aware of is the disk geometry patch series.
The corresponding qemu series is still waiting to be merged.
The
Kamil Rytarowski writes:
> On 16.10.2019 08:11, Thomas Huth wrote:
>> On 16/10/2019 05.00, Eduardo Habkost wrote:
>>> On Tue, Sep 17, 2019 at 08:31:40PM -0300, Eduardo Habkost wrote:
On Mon, Jul 01, 2019 at 07:25:27PM -0300, Eduardo Habkost wrote:
> On Mon, Jun 10, 2019 at 01:58:50PM +
Patchew URL:
https://patchew.org/QEMU/1571163625-642312-1-git-send-email-andrey.shinkev...@virtuozzo.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Gentle Ping,
Philippe, John?
Just wondering if the series is okay, as Gerd pointed out this series
is a blocker for the corresponding changes in SeaBIOS for v 1.13
Sam
On Tue, Oct 8, 2019 at 2:51 PM Sam Eiderman wrote:
>
>
>
> On Tue, Oct 8, 2019, 13:34 Philippe Mathieu-Daudé wrote:
>>
>> Hi
On 16/10/2019 12.59, Alex Bennée wrote:
>
> Kamil Rytarowski writes:
>
>> On 16.10.2019 08:11, Thomas Huth wrote:
>>> On 16/10/2019 05.00, Eduardo Habkost wrote:
On Tue, Sep 17, 2019 at 08:31:40PM -0300, Eduardo Habkost wrote:
> On Mon, Jul 01, 2019 at 07:25:27PM -0300, Eduardo Habkost
Patchew URL:
https://patchew.org/QEMU/1571163625-642312-1-git-send-email-andrey.shinkev...@virtuozzo.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=
14.10.2019 18:39, Max Reitz wrote:
> Sometimes it is useful to be able to add a node to the block graph that
> takes or unshare a certain set of permissions for debugging purposes.
> This patch adds this capability to blkdebug.
>
> (Note that you cannot make blkdebug release or share permissions t
On Tue, 15 Oct 2019 at 17:34, Philippe Mathieu-Daudé wrote:
>
> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé
Xen change...
Acked-
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote:
>
> The SRAM must be enabled before using the Buffer Pool mode or the DMA
> mode. This is not required on other SoCs.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote:
>
> The Aspeed I2C controller can operate in different transfer modes :
>
> - Byte Buffer mode, using a dedicated register to transfer a
> byte. This is what the model supports today.
>
> - Pool Buffer mode, using an internal SRAM to tr
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote:
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
From: Zhang Chen
Because Advanced Watch Dog module needs chardev socket
to initialize properly before.
Signed-off-by: Zhang Chen
---
vl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/vl.c b/vl.c
index 4489cfb2bb..4094f61d28 100644
--- a/vl.c
+++ b/vl.c
@@ -2683,6 +2683,13 @@ stat
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote:
>
> Currently, we link the DRAM memory region to the FMC model (for DMAs)
> through a property alias at the SoC level. The I2C model will need a
> similar region for DMA support, add a DRAM region property at the SoC
> level for both model to u
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote:
>
> The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
> transfers to and from DRAM.
>
> A pair of registers defines the buffer address and the length of the
> DMA transfer. The address should be aligned on 4 bytes and the m
On Tue, 15 Oct 2019 at 17:55, Peter Maydell wrote:
>
> On Tue, 15 Oct 2019 at 18:43, Cédric Le Goater wrote:
> > On 15/10/2019 19:03, Peter Maydell wrote:
> > > On Mon, 14 Oct 2019 at 17:05, Peter Maydell
> > > wrote:
> > > (armhf)pmaydell@mustang-maydell:~/qemu$
> > > ./build/all-a32/arm-softm
From: Zhang Chen
Advanced Watch Dog is an universal monitoring module on VMM side, it can be
used to detect network down(VMM to guest, VMM to VMM, VMM to another remote
server) and do previously set operation.
for example: send message to admin, notify another VMM, send qmp command to
qemu do
From: Zhang Chen
This patch load pulse_timer and timeout_timer in the new iothread.
The pulse timer will send pulse info to awd_node, and the timeout timer
will check the reply pulse from awd_node. If timeout occur, it will send
opt_script's data to the notification_node.
Signed-off-by: Zhang Ch
From: Zhang Chen
This patch introduce a new module named Advanced Watch Dog,
and defined the input and output parameter. AWD use standard chardev
as the way of communicationg with the outside world.
Demo command:
-object
advanced-watchdog,id=heart1,server=on,awd_node=h1,notification_node=heartbe
From: Zhang Chen
Find and check the chardev awd_node and notification_node,
The awd_node used for keep connect with outside(like VM client/other
host/Remote server), and the notification_node used for do some
operation when disconnect event occur.
Signed-off-by: Zhang Chen
---
net/awd.c | 37 +
> I'm seeing massive corruption of qcow2 images with qemu 4.1.0 and git master
> as of 7f21573c822805a8e6be379d9bcf3ad9effef3dc after a few
> savevm/quit/loadvm cycles.
[...]
> bisected the introduction of the problem to commit
> 69f47505ee66afaa513305de0c1895a224e52c45
> (block: avoid recursive b
On 11/10/2019 10.56, Stefan Hajnoczi wrote:
> The current libqos virtio-pci.c code implements the VIRTIO Legacy
> interface. Extract existing code in preparation for VIRTIO 1.0 support.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> tests/libqos/virtio-pci.h | 2 --
> tests/libqos/virtio-pci.c | 2
Hi Andrew,
On 10/16/19 10:54 AM, Andrew Jones wrote:
Now that Arm CPUs have advertised features lets add tests to ensure
we maintain their expected availability with and without KVM.
Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
---
tests/Makefile.include | 5 +-
tests/arm-cpu-fe
On 11/10/2019 10.56, Stefan Hajnoczi wrote:
> VIRTIO 1.0 PCI devices have multiple PCI_CAP_ID_VNDR capabilities so we
> need a way to iterate over them. Extend qpci_find_capability() to take
> the last address.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> tests/libqos/pci.h | 2 +-
> tests/libqo
Hi Sam,
On 10/16/19 13:02, Sam Eiderman wrote:
> Gentle Ping,
>
> Philippe, John?
>
> Just wondering if the series is okay, as Gerd pointed out this series
> is a blocker for the corresponding changes in SeaBIOS for v 1.13
The QEMU series is still not merged, due to a bug in the last patch
(namel
On 11/10/2019 10.56, Stefan Hajnoczi wrote:
> Instead of just passing the vring page frame number, pass the full
> QVirtQueue. This will allow the VIRTIO 1.0 transport to program the
> fine-grained vring address registers in the future.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> tests/libqos/vi
Hi Peter,
On 10/15/19 7:03 PM, Peter Maydell wrote:
On Mon, 14 Oct 2019 at 17:05, Peter Maydell wrote:
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-id: 20190925143248.1-21-...@kaod.org
Signed-off-by: Peter Maydell
---
include/hw/arm/aspee
On Wed, Oct 16, 2019 at 02:05:24PM +0200, Philippe Mathieu-Daudé wrote:
> > +static void test_query_cpu_model_expansion_kvm(const void *data)
> > +{
> > +QTestState *qts;
> > +
> > +qts = qtest_init(MACHINE "-accel kvm -cpu host");
> > +
> > +assert_has_feature(qts, "host", "pmu");
>
>
On 10/16/19 12:59 PM, Alex Bennée wrote:
Kamil Rytarowski writes:
On 16.10.2019 08:11, Thomas Huth wrote:
On 16/10/2019 05.00, Eduardo Habkost wrote:
On Tue, Sep 17, 2019 at 08:31:40PM -0300, Eduardo Habkost wrote:
On Mon, Jul 01, 2019 at 07:25:27PM -0300, Eduardo Habkost wrote:
On Mon, Jun
On 10/16/19 2:21 PM, Andrew Jones wrote:
On Wed, Oct 16, 2019 at 02:05:24PM +0200, Philippe Mathieu-Daudé wrote:
+static void test_query_cpu_model_expansion_kvm(const void *data)
+{
+QTestState *qts;
+
+qts = qtest_init(MACHINE "-accel kvm -cpu host");
+
+assert_has_feature(qts, "hos
On 10/16/19 2:14 PM, Laszlo Ersek wrote:
Hi Sam,
On 10/16/19 13:02, Sam Eiderman wrote:
Gentle Ping,
Philippe, John?
Just wondering if the series is okay, as Gerd pointed out this series
is a blocker for the corresponding changes in SeaBIOS for v 1.13
The QEMU series is still not merged, du
Hi :
I am looking at a patch where we disable TOPOEXT when -cpu host or -cpu max is
passed to qemu :
if (cpu->max_features) {
for (w = 0; w < FEATURE_WORDS; w++) {
/* Override only features that weren't set explicitly
* by the user.
*/
env->features[w] |=
x86_cpu_
Reintroduce float32_to_float64 that was removed here:
https://lists.gnu.org/archive/html/qemu-devel/2018-04/msg00455.html
- nbench test it not actually calling this function at all
- SPECS 2006 significat number of tests impoved their runtime, just
few of them showed small slowdown
Signed-of
On 16/10/2019 14:20, Philippe Mathieu-Daudé wrote:
> Hi Peter,
>
> On 10/15/19 7:03 PM, Peter Maydell wrote:
>> On Mon, 14 Oct 2019 at 17:05, Peter Maydell wrote:
>>>
>>> From: Cédric Le Goater
>>>
>>> Signed-off-by: Cédric Le Goater
>>> Reviewed-by: Joel Stanley
>>> Message-id: 20190925143248
On 10/16/19 2:41 PM, Cédric Le Goater wrote:
On 16/10/2019 14:20, Philippe Mathieu-Daudé wrote:
Hi Peter,
On 10/15/19 7:03 PM, Peter Maydell wrote:
On Mon, 14 Oct 2019 at 17:05, Peter Maydell wrote:
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message
Hi :
I am looking at a patch where we disable TOPOEXT when -cpu host or -cpu max is
passed to qemu :
if (cpu->max_features) {
for (w = 0; w < FEATURE_WORDS; w++) {
/* Override only features that weren't set explicitly
* by the user.
*/
env->features[w] |=
x86_cpu_
Hi :
I am looking at a patch where we disable TOPOEXT when -cpu host or -cpu max is
passed to qemu :
if (cpu->max_features) {
for (w = 0; w < FEATURE_WORDS; w++) {
/* Override only features that weren't set explicitly
* by the user.
*/
env->features[w] |=
x86_cpu_
Hi David,
a)
> qemu-img check /volumes/disk2-part2/images/vmtest10-1.qcow2
No errors were found on the image.
24794/327680 = 7.57% allocated, 9.28% fragmented, 0.00% compressed clusters
Image end offset: 1625751552
> qemu-img info /volumes/disk2-part2/images/vmtest10-1.qcow2
image: vmtest10-1.qco
Am 01.10.2019 um 21:15 hat Markus Armbruster geschrieben:
> The QAPI code generator clocks in at some 3100 SLOC in 8 source files.
> Almost 60% of the code is in qapi/common.py. Split it into more
> focused modules:
>
> * Move QAPISchemaPragma and QAPISourceInfo to qapi/source.py.
>
> * Move QAP
On Wed, Oct 16, 2019 at 03:25:53AM -0700, no-re...@patchew.org wrote:
>Patchew URL:
>https://patchew.org/QEMU/20191016012432.22731-1-richardw.y...@linux.intel.com/
>
>
>
>Hi,
>
>This series seems to have some coding style problems. See output below for
>more information:
>
>Subject: [PATCH] checkp
From: Tianyu Lan
This patchset is to enable Hyper-V direct tlbflush
feature. The feature is to let L0 hypervisor to handle
tlb flush hypercall for L1 hypervisor.
Tianyu Lan (2):
linux headers: update against Linux 5.4-rc2
target/i386/kvm: Add Hyper-V direct tlb flush support
docs/hyperv.tx
From: Tianyu Lan
commit da0c9ea146cbe92b832f1b0f694840ea8eb33cce
Signed-off-by: Tianyu Lan
---
include/standard-headers/asm-x86/bootparam.h | 2 +
include/standard-headers/asm-x86/kvm_para.h | 1 +
include/standard-headers/linux/ethtool.h | 24 ++
include/standard-headers/linux/
The libvdeplug-dev package is required to compile-test net/vde.c.
Signed-off-by: Thomas Huth
---
.gitlab-ci.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ed8067f5cf..be57c6a454 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -5,
Hi Michael,
How sure are you that it's that commit - have you checked the commit before
it?
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1846427
Title:
4.1.0: qcow2 corruption on savevm/quit/lo
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