Re: [Qemu-devel] [PATCH 1/3] pcie: don't skip multi-mask events

On 6/21/19 9:46 AM, Michael S. Tsirkin wrote: If we are trying to set multiple bits at once, testing that just one of them is already set gives a false positive. As a result we won't interrupt guest if e.g. presence detection change and attention button press are both set. This happens with mu

Re: [Qemu-devel] [PATCH 2/3] pcie: check that slt ctrl changed before deleting

On 6/21/19 9:46 AM, Michael S. Tsirkin wrote: During boot, linux would sometimes overwrites control of a powered off slot before powering it on. Unfortunately QEMU interprets that as a power off request and ejects the device. For example: /x86_64-softmmu/qemu-system-x86_64 -enable-kvm -S -ma

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On 6/21/19 9:46 AM, Michael S. Tsirkin wrote: During boot, linux guests tend to clear all bits in pcie slot status register which is used for hotplug. If they clear bits that weren't set this is racy and will lose events: not a big problem for manual hotplug on bare-metal, but a problem for us

Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model

On 6/28/2019 8:28 AM, Eduardo Habkost wrote: Add new version of Cascadelake-Server CPU model, setting stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR with some flags. The new feature will introduce a new host software requirement, breaking our CPU model runnability promises. This means w

Re: [Qemu-devel] [QEMU] [PATCH v5 0/8] Add Qemu to SeaBIOS LCHS interface

On Wed, Jun 26, 2019 at 03:39:40PM +0300, Sam Eiderman wrote: > v1: > > Non-standard logical geometries break under QEMU. > > A virtual disk which contains an operating system which depends on > logical geometries (consistent values being reported from BIOS INT13 > AH=08) will most likely break u

Re: [Qemu-devel] [SeaBIOS] [PATCH v4 0/5] Add Qemu to SeaBIOS LCHS interface

On Wed, Jun 26, 2019 at 03:38:11PM +0300, Sam Eiderman wrote: > v1: > > Non-standard logical geometries break under QEMU. > > A virtual disk which contains an operating system which depends on > logical geometries (consistent values being reported from BIOS INT13 > AH=08) will most likely break u

[Qemu-devel] [PATCH v2] console: fix cell overflow

Linux terminal behavior (coming from vt100 I think) is somewhat strange when it comes to line wraps: When a character is printed to the last char cell of a line the cursor does NOT jump to the next line but stays where it is. The line feed happens when the next character is printed. So the valid

Re: [Qemu-devel] [PATCH] spapr/xive: H_INT_ESB is used for LSIs only

On Mon, Jul 01, 2019 at 07:55:03AM +0200, Cédric Le Goater wrote: > On 01/07/2019 07:07, David Gibson wrote: > > On Fri, Jun 21, 2019 at 05:05:45PM +0200, Cédric Le Goater wrote: > >> On 21/06/2019 16:52, Greg Kurz wrote: > >>> As indicated in the function header, this "hcall is only supported for

[Qemu-devel] [Bug 1774149] Re: qemu-user x86_64 x86 gdb call function from gdb doesn't work

It seems the issue is related to gdb code: set_gdbarch_call_dummy_location (gdbarch, ON_STACK); What is going on? The breakpoint is stored on stack and for the first time the address has a flag PAGE_WRITE. After a call, the address does not have anymore the flag PAGE_WRITE. It is changed in meth

Re: [Qemu-devel] [RFC PATCH 0/5] FAULT INJECTION FRAMEWORK

On Fri, Jun 28, 2019 at 02:45:29PM +0200, Damien Hedde wrote: > This series adds a python framework aiming to provide some ways to do fault > injection in a running vm. In its current state, it allows to easily interact > with memory, change gpios and qom properties. > > The framework consists in

Re: [Qemu-devel] [PATCH v16 1/5] linux-user: Add support for translation of statx() syscall

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Aleksandar Rikalo > > Implement support for translation of system call statx(). > > The implementation is based on "best effort" approach: if host > is capable of executing statx(), host statx() is used. If not, > the implementation in

Re: [Qemu-devel] [PATCH v16 2/5] linux-user: Add support for strace for statx() syscall

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Jim Wilson > > All of the flags need to be conditional as old systems don't have > statx support. Otherwise it works the same as other stat family > syscalls. This requires the pending patch to add statx support. > > Tested on Ubuntu

Re: [Qemu-devel] [PATCH v16 3/5] linux-user: Fix target_flock structure for MIPS O64 ABI

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Aleksandar Markovic > > Among MIPS ABIs, only MIPS O32 and N32 have special (different > than other architectures) definition of structure flock in kernel. > > Bring target_flock definition in QEMU for MIPS O64 ABI to the > correct sta

Re: [Qemu-devel] [PATCH v16 4/5] linux-user: Introduce TARGET_HAVE_ARCH_STRUCT_FLOCK

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Aleksandar Markovic > > Bring target_flock definitions to be more in sync with the way > flock is defined in kernel. > > Basically, the rules from the kernel are: > > 1. Majority of architectures have a common flock definition. > > 2

Re: [Qemu-devel] [PATCH v16 5/5] linux-user: Handle EXCP_FPE properly for MIPS

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Aleksandar Markovic > > Handle EXCP_FPE properly for MIPS in cpu loop. > > Note that a vast majority of FP instructions are not affected by > the absence of the code in this patch, as they use alternative code > paths for handling floa

Re: [Qemu-devel] [PATCH v16 5/5] linux-user: Handle EXCP_FPE properly for MIPS

Le 28/06/2019 à 12:43, Aleksandar Markovic a écrit : > From: Aleksandar Markovic > > Handle EXCP_FPE properly for MIPS in cpu loop. > > Note that a vast majority of FP instructions are not affected by > the absence of the code in this patch, as they use alternative code > paths for handling floa

Re: [Qemu-devel] [PATCH] linux-user: move QEMU_IFLA_BR_MULTI_BOOLOPT to the good function

Le 26/06/2019 à 17:08, Laurent Vivier a écrit : > QEMU_IFLA_BR_MULTI_BOOLOPT has been added to the wrong function > host_to_target_slave_data_bridge_nlattr(). Move it to > host_to_target_data_bridge_nlattr(). > > This fixes following error: > Unknown QEMU_IFLA_BR type 46 > > Fixes: 61b463fbf6cb

Re: [Qemu-devel] [Qemu-trivial] Fix cacheline size retrieval on FreeBSD/PowerPC(64)

Le 27/06/2019 à 02:15, Justin Hibbits a écrit : > > > On Wed, Jun 26, 2019, 19:08 Laurent Vivier > wrote: > > Le 27/06/2019 à 02:02, Justin Hibbits a écrit : > > > > > > On Wed, Jun 26, 2019, 13:04 Justin Hibbits >

Re: [Qemu-devel] [QEMU-PPC] [PATCH v3] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

On Mon, 1 Jul 2019 16:19:46 +1000 Suraj Jitindar Singh wrote: > The ibm,get_system_parameter rtas call is used by the guest to retrieve > data relating to certain parameters of the system. The SPLPAR > characteristics option (token 20) is used to determin characteristics of > the environment in

Re: [Qemu-devel] patch to swap SIGRTMIN + 1 and SIGRTMAX - 1

On Sat, 29 Jun 2019 at 11:53, Philippe Mathieu-Daudé wrote: > > Hi Marlies, > > On 6/29/19 1:26 AM, Marlies Ruck wrote: > > Hi, > > > > I just wanted to follow up since I sent this patch a week ago to make sure > > it was a received. An ack would be appreciated. > > You did not Cc'ed the maintain

Re: [Qemu-devel] [PATCH v24 1/7] target/avr: Add outward facing interfaces and core CPU logic

On Fri, 28 Jun 2019 18:54:27 +0300 Michael Rolnik wrote: > Igor. > > so avr6 instead of a6-avr-cpu, xmega2 instead of xmega2-avr-cpu and so on, > right? (it would be better if question was rith under context that prompted it) [...] > > > +++ b/target/avr/cpu.h > > > @@ -0,0 +1,283 @@ > > > +/*

[Qemu-devel] [PATCH v2 2/3] qemu-bridge-helper: move repeating code in parse_acl_file

From: Prasad J Pandit Move repeating error handling sequence in parse_acl_file routine to an 'err' label. Signed-off-by: Prasad J Pandit --- qemu-bridge-helper.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/qemu-bridge-helper.c b/qemu-bridge-helper.c

[Qemu-devel] [PATCH v2 0/3] restrict bridge interface name to IFNAMSIZ

From: Prasad J Pandit Hello, Linux net_deivce defines network interface name to be of IFNAMSIZE(=16) bytes, including the terminating null('\0') byte. Qemu tap deivce, while invoking 'qemu-bridge-helper' tool to set up the network bridge interface, supplies bridge name of 16 characters, thus al

Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

On Sat, 29 Jun 2019 at 17:37, Lucien Murray-Pitts wrote: > However for the m68k the do_transaction_failed function pointer field > has not been implemented. Er, I implemented that in commit e1aaf3a88e95ab007. Are you working with an out-of-date version of QEMU ? thanks -- PMM

[Qemu-devel] [PATCH v2 3/3] net: tap: restrict bridge name to IFNAMSIZ

From: Prasad J Pandit The interface name in Linux interface request struct 'ifreq' OR in qemu-bridge-helper is defined to be of size IFNAMSIZ(=16), including the terminating null('\0') byte. QEMU tap device, while invoking qemu-bridge-helper, supplies bridge name of 16 characters, restrict it to

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

CCing qemu-devel On 7/1/19 11:57 AM, Igor Mammedov wrote: On Mon, 1 Jul 2019 10:04:01 +0300 Marcel Apfelbaum wrote: On 6/21/19 9:46 AM, Michael S. Tsirkin wrote: During boot, linux guests tend to clear all bits in pcie slot status register which is used for hotplug. If they clear bits that w

[Qemu-devel] [PATCH v2 1/3] qemu-bridge-helper: restrict interface name to IFNAMSIZ

From: Prasad J Pandit The interface names in qemu-bridge-helper are defined to be of size IFNAMSIZ(=16), including the terminating null('\0') byte. The same is applied to interface names read from 'bridge.conf' file to form ACLs rules. If user supplied '--br=bridge' name is not restricted to the

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

CCing qemu-devel On 7/1/19 11:57 AM, Igor Mammedov wrote: On Mon, 1 Jul 2019 10:04:01 +0300 Marcel Apfelbaum wrote: On 6/21/19 9:46 AM, Michael S. Tsirkin wrote: During boot, linux guests tend to clear all bits in pcie slot status register which is used for hotplug. If they clear bits that w

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On Tue, Jun 25, 2019 at 03:07:30PM +0200, Igor Mammedov wrote: > On Fri, 21 Jun 2019 02:46:50 -0400 > "Michael S. Tsirkin" wrote: > > > During boot, linux guests tend to clear all bits in pcie slot status > > register which is used for hotplug. > > If they clear bits that weren't set this is racy

Re: [Qemu-devel] [PATCH v2 0/3] restrict bridge interface name to IFNAMSIZ

Patchew URL: https://patchew.org/QEMU/20190701090904.31312-1-ppan...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190701090904.31312-1-ppan...@redhat.com Type: series Subject: [Qemu-devel] [PATCH v2 0/3] restrict bri

Re: [Qemu-devel] [PATCH 2/3] pcie: check that slt ctrl changed before deleting

On Tue, Jun 25, 2019 at 02:45:11PM +0200, Igor Mammedov wrote: > On Fri, 21 Jun 2019 02:46:48 -0400 > "Michael S. Tsirkin" wrote: > > > During boot, linux would sometimes overwrites control of a powered off > > slot before powering it on. Unfortunately QEMU interprets that as a > > power off requ

Re: [Qemu-devel] [PATCH 1/4] hw/i386: Factorize CPU routine

On Fri, Jun 28, 2019 at 11:44:07PM +0200, Sergio Lopez wrote: > > Eduardo Habkost writes: > > > On Fri, Jun 28, 2019 at 01:53:46PM +0200, Sergio Lopez wrote: > > [...] > >> /* Enables contiguous-apic-ID mode, for compatibility */ > >> -static bool compat_apic_id_mode; > >> +bool compat_apic_id_

Re: [Qemu-devel] [PATCH for-4.1 00/24] Fix record/replay and add reverse debugging

Ping. Pavel Dovgalyuk > -Original Message- > From: dovgaluk [mailto:dovga...@ispras.ru] > Sent: Thursday, June 27, 2019 8:49 PM > To: pbonz...@redhat.com > Cc: qemu-devel@nongnu.org; kw...@redhat.com; peter.mayd...@linaro.org; > crosthwaite.pe...@gmail.com; boost.li...@gmail.com; > arte

[Qemu-devel] [PATCH v2 0/6] ARM SMMUv3: Fix spurious notification errors and stall with vfio-pci

This series fixes the guest stall observed when attempting to run a guest exposed with a SMMUv3 and a VFIO-PCI device. As a reminder SMMUv3 is not yet integrated with VFIO (the device will not work properly) but this shouldn't prevent the guest from booting. It also silences some spurious translat

[Qemu-devel] [PATCH v2 2/6] memory: Add IOMMU_ATTR_VFIO_NESTED IOMMU memory region attribute

We introduce a new IOMMU Memory Region attribute, IOMMU_ATTR_VFIO_NESTED that tells whether the virtual IOMMU requires physical nested stages for VFIO integration. Current Intel virtual IOMMU device supports "Caching Mode" and does not require 2 stages at physical level to be integrated with VFIO.

[Qemu-devel] [PATCH v2 4/6] hw/arm/smmuv3: Advertise VFIO_NESTED

Virtual SMMUv3 requires physical nested stages for VFIO integration. Advertise this attribute. Signed-off-by: Eric Auger --- --- hw/arm/smmuv3.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e96d5beb9a..384c02cb91 100644 --- a/hw/arm/s

[Qemu-devel] [PATCH v2 1/6] memory: Remove unused memory_region_iommu_replay_all()

memory_region_iommu_replay_all is not used. Remove it. Signed-off-by: Eric Auger Reported-by: Peter Maydell --- include/exec/memory.h | 10 -- memory.c | 9 - 2 files changed, 19 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index e6140e8

[Qemu-devel] [PATCH 4/3] pcie: minor cleanups for slot control/status

Rename function arguments to make intent clearer. Better documentation for slot control logic. Suggested-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pcie.h | 3 ++- hw/pci/pcie.c | 17 +++-- 2 files changed, 13 insertions(+), 7 deletions(-) dif

[Qemu-devel] [PATCH v2 5/6] hw/arm/smmuv3: Log a guest error when decoding an invalid STE

Log a guest error when encountering an invalid STE. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 384c02cb91..2e270a0f07 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -320,6 +320,7 @@ static int d

[Qemu-devel] [PATCH v2 6/6] hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations

An IOVA/ASID invalidation is notified to all IOMMU Memory Regions through smmuv3_inv_notifiers_iova/smmuv3_notify_iova. When the notification occurs it is possible that some of the PCIe devices associated to the notified regions do not have a valid stream table entry. In that case we output a LOG_

Re: [Qemu-devel] [PATCH v2 3/3] net: tap: restrict bridge name to IFNAMSIZ

On Mon, Jul 01, 2019 at 02:39:04PM +0530, P J P wrote: > From: Prasad J Pandit > > The interface name in Linux interface request struct 'ifreq' > OR in qemu-bridge-helper is defined to be of size IFNAMSIZ(=16), > including the terminating null('\0') byte. > > QEMU tap device, while invoking qemu

[Qemu-devel] [PATCH v2 3/6] hw/vfio/common: Do not replay IOMMU mappings in nested case

In nested mode, the stage 1 translation tables are owned by the guest and there is no caching on host side. So there is no need to replay the mappings. As of today, the SMMUv3 nested mode is not yet implemented and there is no functional VFIO integration without. But keeping the replay call would

Re: [Qemu-devel] [PATCH] hw/arm/virt: Add support for Cortex-A7

On 6/30/19 5:13 PM, Jan Kiszka wrote: > From: Jan Kiszka > > No reason to deny this type. Maybe add "As the A15, it supports the EL2/V7VE features."? > > Signed-off-by: Jan Kiszka > --- > hw/arm/virt.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c >

Re: [Qemu-devel] [PATCH v2 1/3] qemu-bridge-helper: restrict interface name to IFNAMSIZ

On Mon, Jul 01, 2019 at 02:39:02PM +0530, P J P wrote: > From: Prasad J Pandit > > The interface names in qemu-bridge-helper are defined to be > of size IFNAMSIZ(=16), including the terminating null('\0') byte. > The same is applied to interface names read from 'bridge.conf' > file to form ACLs r

Re: [Qemu-devel] [PATCH v2 2/3] qemu-bridge-helper: move repeating code in parse_acl_file

On Mon, Jul 01, 2019 at 02:39:03PM +0530, P J P wrote: > From: Prasad J Pandit > > Move repeating error handling sequence in parse_acl_file routine > to an 'err' label. > > Signed-off-by: Prasad J Pandit > --- > qemu-bridge-helper.c | 18 -- > 1 file changed, 8 insertions(+), 1

Re: [Qemu-devel] [PULL 57/60] target/ppc: add HV support for POWER9

On 7/1/19 7:04 AM, David Gibson wrote: > On Fri, Jun 28, 2019 at 03:20:32PM +0200, Philippe Mathieu-Daudé wrote: >> Hi, >> >> On 3/12/19 8:58 PM, Cédric Le Goater wrote: >>> On 3/12/19 8:30 PM, Cleber Rosa wrote: > From: "Cleber Rosa" > Sent: Tuesday, March 12, 2019 3:14:09 PM > Subjec

Re: [Qemu-devel] [PULL 00/19] testing/next (tests/vm, Travis and hyperv build fix)

On Mon, 24 Jun 2019 at 14:43, Alex Bennée wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git repositor

Re: [Qemu-devel] [PATCH 4/3] pcie: minor cleanups for slot control/status

On 7/1/19 11:34 AM, Michael S. Tsirkin wrote: > Rename function arguments to make intent clearer. > Better documentation for slot control logic. > > Suggested-by: Igor Mammedov > Signed-off-by: Michael S. Tsirkin > --- > > > include/hw/pci/pcie.h | 3 ++- > hw/pci/pcie.c | 17 +++

Re: [Qemu-devel] [PATCH 1/3] pcie: don't skip multi-mask events

On 6/21/19 8:46 AM, Michael S. Tsirkin wrote: > If we are trying to set multiple bits at once, testing that just one of > them is already set gives a false positive. As a result we won't > interrupt guest if e.g. presence detection change and attention button > press are both set. This happens with

Re: [Qemu-devel] [PATCH v2 3/3] net: tap: restrict bridge name to IFNAMSIZ

+-- On Mon, 1 Jul 2019, Daniel P. Berrangé wrote --+ | Playing games with multiple "perfectly" sized static buffers & snprintf is | madness. How about re-writing this method so that it just uses | g_strdup_printf() to dynamically format the helper_cmd string. | | Alternatively we could get rid o

Re: [Qemu-devel] [PATCH v2 5/6] hw/arm/smmuv3: Log a guest error when decoding an invalid STE

On 7/1/19 11:30 AM, Eric Auger wrote: > Log a guest error when encountering an invalid STE. > > Signed-off-by: Eric Auger > --- > hw/arm/smmuv3.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 384c02cb91..2e270a0f07 100644 > --- a/hw/arm/smmuv

Re: [Qemu-devel] [PATCH v2 1/6] memory: Remove unused memory_region_iommu_replay_all()

On 7/1/19 11:30 AM, Eric Auger wrote: > memory_region_iommu_replay_all is not used. Remove it. > > Signed-off-by: Eric Auger > Reported-by: Peter Maydell > --- > include/exec/memory.h | 10 -- > memory.c | 9 - > 2 files changed, 19 deletions(-) > > diff --git a/i

Re: [Qemu-devel] [PATCH v2 1/3] qemu-bridge-helper: restrict interface name to IFNAMSIZ

+-- On Mon, 1 Jul 2019, Daniel P. Berrangé wrote --+ | > +if (strcmp(cmd, "include") && strlen(arg) >= IFNAMSIZ) { | > +fprintf(stderr, "name `%s' too long: %lu\n", arg, strlen(arg)); | | strlen returns size_t, which does not match %lu - it needs %zu - we can | ignore the non-p

Re: [Qemu-devel] [PATCH v2 0/3] restrict bridge interface name to IFNAMSIZ

Patchew URL: https://patchew.org/QEMU/20190701090904.31312-1-ppan...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190701090904.31312-1-ppan...@redhat.com Subject: [Qemu-devel] [PATCH v2 0/3] restrict bridge interface

Re: [Qemu-devel] [PATCH v5] memory: do not notify for non inclusive overlap entry

Hi Yan, On 6/29/19 12:19 AM, Yan Zhao wrote: > if an entry has non inclusive overlap with the notifier, print warning > message and do not do notification for it. > > Out of scope mapping/unmapping would cause problem, as in below case: > > 1. initially there are two notifiers with ranges > 0-0x

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

On 6/29/19 7:21 AM, Alistair Francis wrote: > On Fri, Jun 28, 2019 at 3:14 PM Paolo Bonzini wrote: >> >> On 28/06/19 23:57, Alistair Francis wrote: >>> >>> I tried to run my VM with option "-drive >>> ...,rerror=report,werror=report" as he noted, but the eternal loop >>> symptom still happens when

Re: [Qemu-devel] [RFC PATCH 0/5] FAULT INJECTION FRAMEWORK

On 7/1/19 10:37 AM, Stefan Hajnoczi wrote: > On Fri, Jun 28, 2019 at 02:45:29PM +0200, Damien Hedde wrote: >> This series adds a python framework aiming to provide some ways to do fault >> injection in a running vm. In its current state, it allows to easily interact >> with memory, change gpios and

Re: [Qemu-devel] [qemu-s390x] [PATCH] s390x: add cpu feature/model files to KVM section

On Wed, 26 Jun 2019 15:08:20 +0200 Cornelia Huck wrote: > The cpu features/models are not only relevant for TCG, but > also for KVM. Make sure that the KVM maintainers are cc:ed > on patches as well. > > Signed-off-by: Cornelia Huck Acked-by: Halil Pasic > --- > MAINTAINERS | 2 ++ > 1 file

[Qemu-devel] [PATCH v2] target/i386: HAX: Enable ROM/ROM device memory region support

From: Hang Yuan Add ROM and ROM device memory region support in HAX. Their memory region is read only and write access will generate EPT violation. The violation will be handled in the HAX kernel with the following patch. https://github.com/intel/haxm/commit/33ceea09a1655fca12c47f1e112b1d269357f

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On 7/1/19 5:57 AM, Aleksandar Markovic wrote: > > On Jun 30, 2019 5:12 PM, "Richard Henderson" > wrote: >> >> On 6/30/19 3:37 PM, Aleksandar Markovic wrote: >> >>  bool have_isa_2_06; >> >>  bool have_isa_2_06_vsx; >> >> +bool have_isa_2_07_vsx; >> > >> > Does

Re: [Qemu-devel] [PATCH v3 0/7] Kconfig dependencies for MIPS machines (but Malta)

Hi Aleksandar, On 6/30/19 9:12 AM, Aleksandar Markovic wrote: > > On Mar 11, 2019 1:56 AM, "Philippe Mathieu-Daudé" > wrote: >> >> Express the MIPS machine dependencies with Kconfig. >> >> Due to its complexity, the Malta board fill follow in a different >> series. >> >

Re: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes

On 6/30/19 7:58 PM, Mark Cave-Ayland wrote: > I don't have space for a full set of images on the G4, however I've tried > boot tests > on installer CDs for MacOS 9, OS X 10.2, Linux and HelenOS and it looks good > here. > > Tested-by: Mark Cave-Ayland [PPC32] Thanks! r!

Re: [Qemu-devel] [PATCH] s390x: add cpu feature/model files to KVM section

On Wed, 26 Jun 2019 15:08:20 +0200 Cornelia Huck wrote: > The cpu features/models are not only relevant for TCG, but > also for KVM. Make sure that the KVM maintainers are cc:ed > on patches as well. > > Signed-off-by: Cornelia Huck > --- > MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+)

Re: [Qemu-devel] [PATCH v3 0/7] Kconfig dependencies for MIPS machines (but Malta)

> Since I doubt we can fix easily the design flow when (coproc) > instructions access optional device before 4.1, I'll also take out the > Boston patches, and see what's left I can respin. No problem, what can we do. Or you can tell me just what patches I should apply from this series now. I pla

Re: [Qemu-devel] [PATCH v5 5/8] acpi: introduce AcpiDeviceIfClass.build_mem_ranges hook

On Fri, 14 Jun 2019 23:56:23 +0800 Tao Xu wrote: > Add build_mem_ranges callback to AcpiDeviceIfClass and use > it for generating SRAT and HMAT numa memory ranges. > > Suggested-by: Igor Mammedov > Co-developed-by: Liu Jingqi > Signed-off-by: Liu Jingqi > Signed-off-by: Tao Xu > --- > > Cha

[Qemu-devel] [PATCH 7/7] target/mips: Correct helper for MSA FCLASS. instructions

From: Aleksandar Markovic Correct helper for MSA FCLASS. instructions. Signed-off-by: Aleksandar Markovic --- target/mips/msa_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 9db2ce7..2240363 100644 --- a/

[Qemu-devel] [PATCH 3/7] target/mips: Correct comments in msa_helper.c

From: Aleksandar Markovic Fix some errors in comments for MSA helpers. Signed-off-by: Aleksandar Markovic --- target/mips/msa_helper.c | 44 ++-- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_h

[Qemu-devel] [PATCH 0/7] target/mips: Mips improvements for 4.1

From: Aleksandar Markovic A collection of misc MIPS improvements that would be nice to be integrated into 4.1. Aleksandar Markovic (7): tcg/tests: target/mips: Amend MSA fixed point multiply tests tcg/tests: target/mips: Amend MSA integer multiply tests target/mips: Correct comments in msa

[Qemu-devel] [PATCH 4/7] target/mips: Correct comments in translate.c

From: Aleksandar Markovic Fix some checkpatch comment-related warnings. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 347 +++- 1 file changed, 225 insertions(+), 122 deletions(-) diff --git a/target/mips/translate.c b/target/mips

[Qemu-devel] [PATCH 2/7] tcg/tests: target/mips: Amend MSA integer multiply tests

From: Aleksandar Markovic Amend MSA fixed point multiply tests: correct output values for MADDV.B, MADDV.H, MADDV.W, MADDV.D, MSUBV.B, MSUBV.H, MSUBV.W and MSUBD.D. Signed-off-by: Aleksandar Markovic --- .../user/ase/msa/int-multiply/test_msa_maddv_b.c | 224 ++--- .../user/a

[Qemu-devel] [PATCH 6/7] target/mips: Unroll loops for MSA float max/min instructions

From: Aleksandar Markovic Slight preformance improvement for MSA float max/min instructions. Signed-off-by: Aleksandar Markovic --- target/mips/msa_helper.c | 200 +-- 1 file changed, 126 insertions(+), 74 deletions(-) diff --git a/target/mips/msa_h

[Qemu-devel] [PATCH 1/7] tcg/tests: target/mips: Amend MSA fixed point multiply tests

From: Aleksandar Markovic Amend MSA fixed point multiply tests: add tests for MADD_Q.H, MADD_Q.W, MADDR_Q.H, MADDR_Q.W, MSUB_Q.H, MSUB_Q.W, MSUBR_Q.H and MSUBR_Q.W. Signed-off-by: Aleksandar Markovic --- tests/tcg/mips/include/wrappers_msa.h | 16 ++ .../ase/msa/fixed-multiply/te

[Qemu-devel] [PATCH 5/7] tcg/tests: target/mips: Correct MSA test compilation and execution order

From: Aleksandar Markovic Correct MSA test compilation and execution order, for the sake of consistence. Signed-off-by: Aleksandar Markovic --- tests/tcg/mips/user/ase/msa/test_msa_compile_32r6eb.sh | 16 tests/tcg/mips/user/ase/msa/test_msa_compile_32r6el.sh | 16

Re: [Qemu-devel] [PATCH] hw/arm/boot: fix direct kernel boot with initrd

On Tue, 18 Jun 2019 at 13:59, Andrew Jones wrote: > > Fix the condition used to check whether the initrd fits > into RAM; in some cases if an initrd was also passed on > the command line we would get an error stating that it > was too big to fit into RAM after the kernel. Despite the > error the l

Re: [Qemu-devel] [PATCH] hw/arm/msf2-som: Exit when the cpu is not the expected one

On Mon, 17 Jun 2019 at 17:01, Philippe Mathieu-Daudé wrote: > > This machine correctly defines its default_cpu_type to cortex-m3 > and report an error if the user requested another cpu_type, > however it does not exit, and this can confuse users trying > to use another core: > > $ qemu-system-ar

Re: [Qemu-devel] [PATCH] hw/arm/virt: Add support for Cortex-A7

On Sun, 30 Jun 2019 at 16:13, Jan Kiszka wrote: > > From: Jan Kiszka > > No reason to deny this type. > > Signed-off-by: Jan Kiszka > --- > hw/arm/virt.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 431e2900fd..ed009fa447 100644 > --- a/hw/arm/v

[Qemu-devel] [PULL 0/6] final s390x patches for 4.1 softfreeze

The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the Git repository at: https://github.com/cohuck/qemu tags/s390x-201

[Qemu-devel] [PULL 5/6] vfio-ccw: support async command subregion

A vfio-ccw device may provide an async command subregion for issuing halt/clear subchannel requests. If it is present, use it for sending halt/clear request to the device; if not, fall back to emulation (as done today). Reviewed-by: Farhan Ali Message-Id: <20190613092542.2834-1-coh...@redhat.com>

[Qemu-devel] [PULL 3/6] s390x/cpumodel: Prepend KDSA features with "KDSA"

From: David Hildenbrand Let's handle it just like for other crypto features. Reviewed-by: Janosch Frank Acked-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target/s390x/cpu_features_def.inc.h | 30 ++--- target/s390x/gen-features.c | 30 ++

Re: [Qemu-devel] [PATCH 0/7] target/mips: Mips improvements for 4.1

> From: Aleksandar Markovic > Sent: Monday, July 1, 2019 1:04 PM > To: qemu-devel@nongnu.org; Aleksandar Rikalo > Cc: Aleksandar Markovic > Subject: [PATCH 0/7] target/mips: Mips improvements for 4.1 > > From: Aleksandar Markovic > > A collection of misc MIPS improvements that would be nice to be

[Qemu-devel] [PULL 4/6] vfio-ccw: use vfio_set_irq_signaling

Use the new helper. Reviewed-by: Eric Auger Reviewed-by: Eric Farman Message-Id: <20190617101036.4087-1-coh...@redhat.com> Signed-off-by: Cornelia Huck --- hw/vfio/ccw.c | 51 +-- 1 file changed, 13 insertions(+), 38 deletions(-) diff --git a/hw

[Qemu-devel] [PULL 2/6] s390x/cpumodel: Rework CPU feature definition

From: David Hildenbrand Let's define features at a single spot and make it less error prone to define new features. Acked-by: Janosch Frank Acked-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target/s390x/cpu_features.c | 352 +- target/s390x/cpu_feat

Re: [Qemu-devel] [PATCH v5 6/8] hmat acpi: Build Memory Subsystem Address Range Structure(s) in ACPI HMAT

On Fri, 14 Jun 2019 23:56:24 +0800 Tao Xu wrote: > From: Liu Jingqi > > HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table > (HMAT). > The specification references below link: > http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf > > It describes the memory at

[Qemu-devel] [PATCH v4 1/4] hw/mips: Explicit the semi-hosting feature is always required

Disabling the semi-hosting feature leads to build failure: LINKmips-softmmu/qemu-system-mips /usr/bin/ld: target/mips/mips-semi.o: in function `helper_do_semihosting': target/mips/mips-semi.c:335: undefined reference to `qemu_semihosting_log_out' /usr/bin/ld: target/mips/mips-semi.c:

[Qemu-devel] [PATCH v4 0/4] Kconfig dependencies for some MIPS machines

Express the MIPS machine dependencies with Kconfig. Various issues prevent to use Kconfig with the Boston and Malta boards. They will be switched later. v4: - dropped Boston (Aleksandar required the ITU to be selectable) - comment why use 'imply' in Jazz (Thomas) v3: - addressed review comments

[Qemu-devel] [PULL 1/6] tests/tcg/s390x: Fix alignment of csst parameter list

From: Richard Henderson The parameter list given in general register 1 shall be aligned on a quadword boundary. This test currently succeeds or fails depending on the compiler version used and the accidential layout of the function's stack frame. Signed-off-by: Richard Henderson Reviewed-by: D

[Qemu-devel] [PATCH v4 4/4] hw/mips: Express dependencies of the r4k platform with Kconfig

This platform use standard PC devices connected to an ISA bus. Networking is provided by a ne2000 chipset. Signed-off-by: Philippe Mathieu-Daudé --- v4: use 'imply' for VGA_ISA/NE2000_ISA (Thomas) v3: remove CONFIG_NE2000_ISA (Thomas) add PFLASH_CFI01 --- default-configs/mips-softmmu-common

[Qemu-devel] [PATCH v4 2/4] hw/mips: Express dependencies of the MIPSsim machine with Kconfig

The MIPSsim machine only emulates an 8250 UART and a simple network controller, connected via an ISA bus. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé --- default-configs/mips-softmmu-common.mak | 1 - hw/mips/Kconfig | 3 +++ 2 files changed, 3 inserti

[Qemu-devel] [PATCH v4 3/4] hw/mips: Express dependencies of the Jazz machine with Kconfig

The Jazz use the RC4030 Asic to provide an EISA bus and DMA/IRQ. The framebuffer display is managed by a G364, the network card is a Sonic DP83932. A QLogic ESP216 provides a SCSI bus. None, for the both machine variants (PICA-61 and Magnum 4000), the DP83932 chipset is soldered on the board, and

[Qemu-devel] [PULL 6/6] s390x: add cpu feature/model files to KVM section

The cpu features/models are not only relevant for TCG, but also for KVM. Make sure that the KVM maintainers are cc:ed on patches as well. Message-Id: <20190626130820.12290-1-coh...@redhat.com> Acked-by: Christian Borntraeger Acked-by: Halil Pasic Signed-off-by: Cornelia Huck --- MAINTAINERS |

Re: [Qemu-devel] [PATCH 4/7] target/mips: Correct comments in translate.c

On 7/1/19 1:04 PM, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Fix some checkpatch comment-related warnings. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 347 > +++- > 1 file changed, 225 insertions(+), 122

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On Mon, Jul 1, 2019 at 12:29 PM Richard Henderson wrote: > > On 7/1/19 5:57 AM, Aleksandar Markovic wrote: > > > > On Jun 30, 2019 5:12 PM, "Richard Henderson" > > wrote: > >> > >> On 6/30/19 3:37 PM, Aleksandar Markovic wrote: > >> >> bool have_isa_2_06; > >

Re: [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > Expression to calculate update_msi_mapping in code handling writes to > DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should > be: > > !!root->msi.intr[0].enable ^ !!val; > > so that MSI mapping is updated when enabled tra

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

On 01/07/19 12:14, Shinichiro Kawasaki wrote: > I observe four of them listed below in sense data, > when I ran basic operations to the zoned storage from the guest via > scsi-block. > > 21h 04h: UNALIGNED WRITE COMMAND > 21h 05h: WRITE BOUNDARY VIOLATION > 21h 06h: ATTEMPT TO REA

Re: [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > MSI mapping needs to be update when MSI address changes, so add the > code to do so. > > Signed-off-by: Andrey Smirnov > Cc: Peter Maydell > Cc: Michael S. Tsirkin > Cc: qemu-devel@nongnu.org > Cc: qemu-...@nongnu.org > --- Reviewed-by: P

Re: [Qemu-devel] [PATCH v2 0/2] intel_iommu: Fix unexpected unmaps during global unmap

On Mon, Jun 24, 2019 at 05:18:09PM +0800, Peter Xu wrote: > v2: > - rename helper to get_naturally_aligned_size(), simplify the > codes as suggested [Paolo] > - check against vtd page size when looping over for unmaps [Yan] > - add r-b for Eric > > Please review, thanks. Series: Reviewed-by: Mi

Re: [Qemu-devel] [PULL v2 0/8] Block patches

On Mon, 24 Jun 2019 at 15:47, Max Reitz wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git repository

Re: [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches > that of i.MX6: > > * INTD/MSI122 > * INTC123 > * INTB124 > * INTA125 > > Fix all of the relevant code to reflect that fact. Nee

Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

>On Monday, July 1, 2019, 06:10:55 PM GMT+9, Peter Maydell wrote: > > On Sat, 29 Jun 2019 at 17:37, Lucien Murray-Pitts> > wrote: > > However for the m68k the do_transaction_failed function pointer field > > has not been implemented.>Er, I implemented that in commit > > e1aaf3a88e95ab007

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On Mon, 1 Jul 2019 05:20:41 -0400 "Michael S. Tsirkin" wrote: > On Tue, Jun 25, 2019 at 03:07:30PM +0200, Igor Mammedov wrote: > > On Fri, 21 Jun 2019 02:46:50 -0400 > > "Michael S. Tsirkin" wrote: > > > > > During boot, linux guests tend to clear all bits in pcie slot status > > > register w

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