On 11/06/2019 04:43, David Gibson wrote:
> On Fri, Jun 07, 2019 at 09:28:49AM -0500, Richard Henderson wrote:
>> On 6/7/19 9:09 AM, Laurent Vivier wrote:
>>> On 07/06/2019 11:29, Laurent Vivier wrote:
On 29/05/2019 08:49, David Gibson wrote:
> From: Richard Henderson
>
> The gvec
On Thu, Jun 06, 2019 at 02:20:18PM -0400, Michael S. Tsirkin wrote:
> On Thu, Jun 06, 2019 at 06:19:43PM +0200, Kashyap Chamarthy wrote:
> > Hi folks,
> >
> > Today I learnt about some obscure PCIe-related properties, in context of
> > the adding PCIe root ports to a guest, namely:
> >
> > io
On 2019/6/11 下午2:51, Tiwei Bie wrote:
The VIRTIO_NET_F_CTRL_VLAN feature requires the support of
vhost-user backend. But it will be advertised to guest driver
as long as it's enabled by users in QEMU, while it's not
supported by vhost-user backend. This patch fixes this issue.
Fixes: 72018d1e1
Peter Maydell writes:
> On Tue, 21 May 2019 at 19:56, Peter Maydell wrote:
>>
>> Currently we have a vague plan that we should migrate our
>> documentation away from Texinfo to using Sphinx, plus some isolated
>> bits of documentation already in .rst format. This email is an attempt
>> to sketch
On 11/06/2019 09:05, Laurent Vivier wrote:
> On 11/06/2019 04:43, David Gibson wrote:
>> On Fri, Jun 07, 2019 at 09:28:49AM -0500, Richard Henderson wrote:
>>> On 6/7/19 9:09 AM, Laurent Vivier wrote:
On 07/06/2019 11:29, Laurent Vivier wrote:
> On 29/05/2019 08:49, David Gibson wrote:
>>>
On 2019/6/10 下午11:55, Michael S. Tsirkin wrote:
On Tue, Jun 04, 2019 at 03:10:43PM +0800, Like Xu wrote:
Hi Michael，
At https://www.linux-kvm.org/page/NetworkingTodo, there is an entry for
network latency saying:
---
reduce networking latency:
allow handling short packets from softirq or V
On Mon, 06/10 19:18, Aarushi Mehta wrote:
> Option only enumerates for hosts that support it.
>
> Signed-off-by: Aarushi Mehta
> Reviewed-by: Stefan Hajnoczi
> ---
> qapi/block-core.json | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/qapi/block-core.json b/qapi/blo
On 07/06/2019 20:30, Richard Henderson wrote:
> The loop is written with scalars, not vectors.
> Use the correct type when incrementing.
>
> Fixes: 5ee5c14cacd
> Reported-by: Laurent Vivier
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/tcg-runtime-gvec.c | 6 +++---
> 1 file changed, 3 i
On 6/7/19 10:34 AM, Gerd Hoffmann wrote:
This patch changes the handling of the mmconfig area. Thanks to the
pci(e) expander devices we already have the logic to exclude address
ranges from PCI0._CRS. We can simply add the mmconfig address range
to the list get it excluded as well.
With tha
On Tue, Apr 02, 2019 at 08:31:06AM +0800, Wei Yang wrote:
>MigrationState->bytes_xfer is only set to 0 in migrate_init().
>
>Remove this unnecessary field.
>
>Signed-off-by: Wei Yang
Hi, David
Are you willing to pick up this one?
>---
> migration/migration.c | 1 -
> migration/migration.h | 1 -
On Mon, Apr 01, 2019 at 02:14:57PM +0800, Wei Yang wrote:
>During migration, there are several places to iterate on
>savevm.handlers. And on each iteration, we need to check its ops and
>related callbacks before invoke it.
>
>Generally, ops is the first element to check, and it is only necessary
>t
Wei Yang wrote:
> On Tue, Apr 02, 2019 at 08:31:06AM +0800, Wei Yang wrote:
>>MigrationState->bytes_xfer is only set to 0 in migrate_init().
>>
>>Remove this unnecessary field.
>>
>>Signed-off-by: Wei Yang
>
> Hi, David
Hi
I am on duty this week, will get it.
>
> Are you willing to pick up thi
Wei Yang wrote:
> On Mon, Apr 01, 2019 at 02:14:57PM +0800, Wei Yang wrote:
>>During migration, there are several places to iterate on
>>savevm.handlers. And on each iteration, we need to check its ops and
>>related callbacks before invoke it.
>>
>>Generally, ops is the first element to check, and
Michael,
Could you pick this series in the next virtio pull request?
If you disagree with some of my patches, could you take at least the
first one (from Kashyap)?
Thanks,
Laurent
On 29/05/2019 16:31, Laurent Vivier wrote:
> Add a new RNG backend using QEMU builtin getrandom function.
>
> v7:
Cc'ing Paolo & Richard.
On 6/10/19 4:27 AM, Colin Xu wrote:
> cc more.
>
> On 2019-06-10 10:19, Colin Xu wrote:
>> QEMU tracks whether a vcpu is halted using CPUState::halted. E.g.,
>> after initialization or reset, halted is 0 for the BSP (vcpu 0)
>> and 1 for the APs (vcpu 1, 2, ...). A halted
Hi Ramon,
On 6/9/19 12:08 PM, Ramon Fried wrote:
> defining CADENCE_GEM_ERR_DEBUG causes compilation
> errors, fix that.
>
> Signed-off-by: Ramon Fried
> ---
> hw/net/cadence_gem.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cade
Igor Mammedov writes:
> Legacy '-numa node,mem' option has a number of issues and mgmt often
> defaults to it. Unfortunately it's no possible to replace it with
> an alternative '-numa memdev' without breaking migration compatibility.
> What's possible though is to deprecate it, keeping option wo
Eduardo Habkost writes:
> On Fri, Jun 07, 2019 at 07:39:17PM +0200, Markus Armbruster wrote:
>> This is correct when the TYPE_VIRT_MACHINE, TYPE_PC_MACHINE and
>> TYPE_SPAPR_MACHINE are exactly the machines supporting NUMA. How could
>> I check that?
>
> parse_numa_node() rejects the -numa optio
On Fri, 2019-06-07 at 15:28 -0400, John Snow wrote:
>
> On 6/7/19 7:08 AM, Paolo Bonzini wrote:
> > On 06/06/19 23:23, John Snow wrote:
> > > So: This looks right; does this fix a bug that can be observed? Do we
> > > have any regression tests for block/NVMe?
> >
> > I don't think it fixes a bug;
Am 11.06.2019 um 04:53 hat l00284672 geschrieben:
> -- Would the "open" hang as well in that case?
>The "open" doesn't hang in that case.
>
> Do you have any better solutions to solve this problem in the case?
Yes, but unfortunately it's a lot harder.
This is roughly what you'd have to do:
On Tue, Jun 11, 2019 at 10:33:29AM +0200, Juan Quintela wrote:
>Wei Yang wrote:
>> On Tue, Apr 02, 2019 at 08:31:06AM +0800, Wei Yang wrote:
>>>MigrationState->bytes_xfer is only set to 0 in migrate_init().
>>>
>>>Remove this unnecessary field.
>>>
>>>Signed-off-by: Wei Yang
>>
>> Hi, David
>
>Hi
Am 07.06.2019 um 19:10 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 07.06.2019 18:52, Vladimir Sementsov-Ogievskiy wrote:
> > 07.06.2019 16:02, Kevin Wolf wrote:
> >> Am 07.06.2019 um 13:18 hat Vladimir Sementsov-Ogievskiy geschrieben:
> >>> 07.06.2019 10:57, Kevin Wolf wrote:
> Am 11.04.20
Paolo Bonzini writes:
> On 10/06/19 18:12, Andreas Färber wrote:
>> Am 10.06.19 um 15:52 schrieb Paolo Bonzini:
>>> On 10/06/19 15:28, Andreas Färber wrote:
Am 10.06.19 um 14:03 schrieb Paolo Bonzini:
> Well, that was explained upthread---finding out what device can be
> plugged wher
Am 07.06.2019 um 19:29 hat Dr. David Alan Gilbert geschrieben:
> * Kevin Wolf (kw...@redhat.com) wrote:
> > Move the monitor core infrastructure from monitor/misc.c to
> > monitor/core.c. This is code that can be shared for all targets, so
> > compile it only once.
> >
> > What remains in monitor/
* Kevin Wolf (kw...@redhat.com) wrote:
> Am 07.06.2019 um 19:29 hat Dr. David Alan Gilbert geschrieben:
> > * Kevin Wolf (kw...@redhat.com) wrote:
> > > Move the monitor core infrastructure from monitor/misc.c to
> > > monitor/core.c. This is code that can be shared for all targets, so
> > > compil
Ping
On Jun 7, 2019 2:21 PM, "Aleksandar Markovic"
wrote:
> From: Aleksandar Markovic
>
> This is a collection of misc patches for Linux user that I recently
> accumulated from variuous sources. All of them originate from problems
> observed on mips target. However, these changes actually affect
On Tue, Jun 11, 2019 at 03:36:53PM +0800, Fam Zheng wrote:
> On Mon, 06/10 19:18, Aarushi Mehta wrote:
> > Option only enumerates for hosts that support it.
> >
> > Signed-off-by: Aarushi Mehta
> > Reviewed-by: Stefan Hajnoczi
> > ---
> > qapi/block-core.json | 4 +++-
> > 1 file changed, 3 ins
On Mon, Jun 10, 2019 at 07:19:02PM +0530, Aarushi Mehta wrote:
> @@ -294,6 +302,7 @@ LuringState *luring_init(Error **errp)
> int rc;
> LuringState *s;
> s = g_malloc0(sizeof(*s));
> +trace_luring_init_state((void *)s, sizeof(*s));
In C conversion to void * is automatic and does
On Mon, 10 Jun 2019 at 22:41, Aleksandar Markovic
wrote:
>
>
> On Jun 10, 2019 5:25 PM, "Peter Maydell" wrote:
> >
> > The docs/specs/index.rst has a couple of minor issues which
> > we didn't notice because we weren't building the manual:
> > * the ToC entry for the new PPC XIVE docs points to
On Mon, Jun 10, 2019 at 07:19:03PM +0530, Aarushi Mehta wrote:
> +static bool qemu_luring_poll_cb(void *opaque)
> +{
> +LuringState *s = opaque;
> +struct io_uring_cqe *cqes;
> +
> +if (io_uring_peek_cqe(&s->ring, &cqes) == 0) {
> +if (!cqes) {
> +qemu_luring_process
On Mon, Jun 10, 2019 at 07:19:04PM +0530, Aarushi Mehta wrote:
> Signed-off-by: Aarushi Mehta
> ---
> qemu-io.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/qemu-io.c b/qemu-io.c
> index 8d5d5911cb..54b82151c4 100644
> --- a/qemu-io.c
> +++ b/qemu-io.c
> @@ -129,6 +129
Please can you try with a more recent version of QEMU? 2.8 is pretty
old, and there are definitely some bugs involving Alpine Linux glibc and
also go that we've fixed in later versions.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
On Mon, Jun 10, 2019 at 07:18:53PM +0530, Aarushi Mehta wrote:
> This patch series adds support for the newly developed io_uring Linux AIO
> interface. Linux io_uring is faster than Linux's AIO asynchronous I/O code,
> offers efficient buffered asynchronous I/O support, the ability to do I/O
> with
On Mon, Jun 10, 2019 at 07:19:05PM +0530, Aarushi Mehta wrote:
> Signed-off-by: Aarushi Mehta
> ---
> tests/qemu-iotests/087 | 26 ++
> tests/qemu-iotests/087.out | 10 ++
> 2 files changed, 36 insertions(+)
>
> diff --git a/tests/qemu-iotests/087 b/tests/qemu
On 6/7/19 2:43 PM, Andrea Bolognani wrote:
On Thu, 2019-06-06 at 14:20 -0400, Michael S. Tsirkin wrote:
On Thu, Jun 06, 2019 at 06:19:43PM +0200, Kashyap Chamarthy wrote:
Hi folks,
Today I learnt about some obscure PCIe-related properties, in context of
the adding PCIe root ports to a guest
On 6/11/19 10:21 AM, Kashyap Chamarthy wrote:
On Thu, Jun 06, 2019 at 02:20:18PM -0400, Michael S. Tsirkin wrote:
On Thu, Jun 06, 2019 at 06:19:43PM +0200, Kashyap Chamarthy wrote:
Hi folks,
Today I learnt about some obscure PCIe-related properties, in context of
the adding PCIe root ports
No reason to keep it separate, it differs from others block driver
behavior and therefor confuses. Instead of generic
'state = (State*)bs->opaque' we have to use special helper.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd.c | 197 +-
Drop one on failure path (we have errp) and turn two others into trace
points.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.h | 9 -
block/nbd-client.c | 6 +++---
block/trace-events | 2 ++
3 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/block/nbd-cli
Hi all!
I need some fields of BDRVNBDState to be available in nbd-client.c
code for my nbd-reconnect series. This leads to the following idea:
It seems that there is no actual benefits in splitting
NBDClientSession out of BDRVNBDState and nbd-client.c out of nbd.c
It only increases confusion aroun
No reason of keeping driver handlers realization in separate of driver
structure. We can get rid of extra header file.
While being here, fix comments style, restore forgotten comments for
NBD_FOREACH_REPLY_CHUNK and nbd_reply_chunk_iter_receive, remove extra
includes.
Signed-off-by: Vladimir Seme
11.06.2019 11:53, Kevin Wolf wrote:
> Am 07.06.2019 um 19:10 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 07.06.2019 18:52, Vladimir Sementsov-Ogievskiy wrote:
>>> 07.06.2019 16:02, Kevin Wolf wrote:
Am 07.06.2019 um 13:18 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 07.06.2019 10:5
On 11/06/19 10:38, Philippe Mathieu-Daudé wrote:
> Cc'ing Paolo & Richard.
>
> On 6/10/19 4:27 AM, Colin Xu wrote:
>> cc more.
>>
>> On 2019-06-10 10:19, Colin Xu wrote:
>>> QEMU tracks whether a vcpu is halted using CPUState::halted. E.g.,
>>> after initialization or reset, halted is 0 for the BS
On 11/06/19 10:56, Markus Armbruster wrote:
> Yes, this is how introspection (both QMP and QOM) is commonly used.
> Just keep in mind one difference: QMP is static, QOM is dynamic.
>
> QMP being static means it's defined at compile time. So is the value of
> query-qmp-schema. Same QEMU build, sa
* Eric Blake (ebl...@redhat.com) wrote:
> On 6/10/19 1:43 PM, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > Allow the caller to restrict the set of interfaces that announces are
> > sent on. The default is still to send on all interfaces.
> >
> > e.g.
> >
> >
From: Richard Henderson
Typo comparing the sign of the field, twice, instead of also comparing
the mask of the field (which itself encodes both position and length).
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190604154225.26992-1-richard.hender...@linaro.org
Revi
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 2 ++
1 file changed, 2
This patchset converts the Arm VFP instructions to use decodetree
instead of the current hand-written decode.
v2 has only very minor changes since v1:
* patch 33 (VFP comparisons): added missing TCG frees
* patch 39 (VJCVT): add back missing jscvt feature check
Patch 39 is the only one still in
Factor out the VFP access checking code so that we can use it in the
leaf functions of the decodetree decoder.
We call the function full_vfp_access_check() so we can keep
the more natural vfp_access_check() for a version which doesn't
have the 'ignore_vfp_enabled' flag -- that way almost all VFP
i
At the moment our -cpu max for AArch32 supports VFP short-vectors
because we always implement them, even for CPUs which should
not have them. The following commits are going to switch to
using the correct ID-register-check to enable or disable short
vector support, so we need to turn it on explicit
Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 VFP encodings. At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.
We need to have one decoder for the unconditional insns and one for
the conditional insns,
Convert the VSEL instructions to decodetree.
We leave trans_VSEL() in translate.c for now as this allows
the patch to show just the changes from the old handle_vsel().
In the old code the check for "do D16-D31 exist" was hidden in
the VFP_DREG macro, and assumed that VFPv3 always implied that
D16-
Convert the VFP VMLS instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 38 ++
target/arm/translate.c | 8 +--
target/arm/vfp.decode | 5 +
3 files changed, 44 ins
Convert the VMINNM and VMAXNM instructions to decodetree.
As with VSEL, we leave the trans_VMINMAXNM() function
in translate.c for the moment.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate.c | 41
target/arm/vfp-u
Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree.
Again, trans_VRINT() is temporarily left in translate.c.
Signed-off-by: Peter Maydell Reviewed-by: Richard
Henderson
---
target/arm/translate.c | 60 +++-
target/arm/vfp-uncond.decode | 5
Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree.
trans_VCVT() is temporarily left in translate.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate.c | 72 +---
target/arm/vfp-uncond.decode | 6 +++
2 files
Convert the VFP VNMLA instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 34 ++
target/arm/translate.c | 19 +--
target/arm/vfp.decode | 5 +
3 files ch
Convert the VFP single load/store insns VLDR and VSTR to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 73 ++
target/arm/translate.c | 22 +-
target/arm/vfp.decode | 7
Move the trans_*() functions we've just created from translate.c
to translate-vfp.inc.c. This is pure code motion with no textual
changes (this can be checked with 'git show --color-moved').
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 337 +++
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase
Convert the VADD instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
d
Convert the VFP two-register transfer instructions to decodetree
(in the v8 Arm ARM these are the "Advanced SIMD and floating-point
64-bit move" encoding group).
Again, we expand out the sequences involving gen_vfp_msr() and
gen_msr_vfp().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hender
Convert the "single-precision" register moves to decodetree:
* VMSR
* VMRS
* VMOV between general purpose register and single precision
Note that the VMSR/VMRS conversions make our handling of
the "should this UNDEF?" checks consistent between the two
instructions:
* VMSR to MVFR0, MVFR1, MVFR
Convert the VFP VNMLS instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 42 ++
target/arm/translate.c | 24 +--
target/arm/vfp.decode | 5
3 files cha
Convert the "double-precision" register moves to decodetree:
this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP.
Note that the conversion process has tightened up a few of the
UNDEF encoding checks: we now correctly forbid:
* VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10
* VMOV-fro
Convert the VSUB instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
d
Convert the VFP load/store multiple insns to decodetree.
This includes tightening up the UNDEF checking for pre-VFPv3
CPUs which only have D0-D15 : they now UNDEF for any access
to D16-D31, not merely when the smallest register in the
transfer list is in D16-D31.
This conversion does not try to sh
Convert the float-to-integer VCVT instructions to decodetree.
Since these are the last unconverted instructions, we can
delete the old decoder structure entirely now.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 72 ++
target/arm/tran
Convert the VDIV instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 21 +
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 20
Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans
functions which perform the memory accesses by going via the TCG
globals cpu_F0s and cpu_F0d, to use local TCG temps instead.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 46
Convert the VCVT double/single precision conversion insns to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 48 ++
target/arm/translate.c | 13 +
target/arm/vfp.decode | 6 +++
On Mon, 06/10 19:18, Aarushi Mehta wrote:
> Aborts when sqe fails to be set as sqes cannot be returned to the ring.
>
> Signed-off-by: Aarushi Mehta
> ---
> MAINTAINERS | 7 +
> block/Makefile.objs | 3 +
> block/io_uring.c| 314 +++
Convert the VCVTT and VCVTB instructions which convert from
f32 and f64 to f16 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
store of the right half of the input single-precision register
rather than doing a loa
Convert the VMUL instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 5 +
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 4 deletions(-)
di
Convert the VFP VMOV (immediate) instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 129 +
target/arm/translate.c | 27 +--
target/arm/vfp.decode | 5 ++
3 files chan
Convert the VNMUL instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 24
target/arm/translate.c | 7 +--
target/arm/vfp.decode | 5 +
3 files changed, 30 insertions(+), 6
Convert the VCVTT, VCVTB instructions that deal with conversion
from half-precision floats to f32 or 64 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
load of the right half of the input single-precision register
Convert the VJCVT instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 28
target/arm/translate.c | 12 +---
target/arm/vfp.decode | 4
3 files changed, 33 insertions(+), 11 deletions(-)
diff --g
Convert the VFP round-to-integer instructions VRINTR, VRINTZ and
VRINTX to decodetree.
These instructions were only introduced as part of the "VFP misc"
additions in v8A, so we check this. The old decoder's implementation
was incorrectly providing them even for v7A CPUs.
Signed-off-by: Peter Mayd
Convert the VFP VMLA instruction to decodetree.
This is the first of the VFP 3-operand data processing instructions,
so we include in this patch the code which loops over the elements
for an old-style VFP vector operation. The existing code to do this
looping uses the deprecated cpu_F0s/F0d/F1s/F1
Convert the VFP fused multiply-add instructions (VFNMA, VFNMS,
VFMA, VFMS) to decodetree.
Note that in the old decode structure we were implementing
these to honour the VFP vector stride/length. These instructions
were introduced in VFPv4, and in the v7A architecture they
are UNPREDICTABLE if the
From: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: A
Convert the VNEG instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
d
Convert the VSQRT instruction to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 20
target/arm/translate.c | 14 +-
target/arm/vfp.decode | 5 +
3 files changed, 26 insertions(+)
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t arch:rx tests/acceptance/boot_linux_co
From: Yoshinori Sato
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.4904
For VFP short vectors, the VFP registers are divided into a
series of banks: for single-precision these are s0-s7, s8-s15,
s16-s23 and s24-s31; for double-precision they are d0-d3,
d4-d7, ... d28-d31. Some banks are "scalar" meaning that
use of a register within them triggers a pure-scalar or
mixed
Convert the VFP VABS instruction to decodetree.
Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or
VFPGen2OpDPFn because none of the operations which use this format
and support short vectors will need it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target
On 6/4/19 5:42 PM, Richard Henderson wrote:
> Typo comparing the sign of the field, twice, instead of also comparing
> the mask of the field (which itself encodes both position and length).
>
> Reported-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 2 +-
>
From: Yoshinori Sato
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 8 +---
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signe
Convert the VCVT (between floating-point and fixed-point) instructions
to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 124 +
target/arm/translate.c | 57 +--
target/arm/vfp.deco
Convert the VFP comparison instructions to decodetree.
Note that comparison instructions should not honour the VFP
short-vector length and stride information: they are scalar-only
operations. This applies to all the 2-operand instructions except
for VMOV, VABS, VNEG and VSQRT. (In the old decode
From: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato
'Convert to CPUC
From: Yoshinori Sato
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
Signed-off-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-9-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use TYPE_RX62N_
Hi Yoshinori, Richard, Igor.
This series an iteration of the previous v16 from Yoshinori with
the fixups requested by Igor here:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg07260.html
and
https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg01547.html
plus trivial cleanups.
It is
Convert the VCVT integer-to-float instructions to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 58 ++
target/arm/translate.c | 12 +--
target/arm/vfp.decode | 6
3 files ch
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by: Philip
From: Yoshinori Sato
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Benn
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-1
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