Fill the new QemuDmaBuf->modifier field properly from plane info.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Marc-André Lureau
Acked-by: Alex Williamson
Message-id: 20190529072144.26737-3-kra...@redhat.com
---
hw/vfio/display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/vfio/display
Check and use QemuDmaBuf->modifier in egl_dmabuf_import_texture()
for dmabuf imports.
Signed-off-by: Gerd Hoffmann
Message-id: 20190529072144.26737-5-kra...@redhat.com
---
ui/egl-helpers.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/ui/
dmabufs can have a format modifier (DRM_FORMAT_MOD_*) which is used for
tiled layouts for example. Add a field to QemuDmaBuf so we can carry
around that information.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Marc-André Lureau
Message-id: 20190529072144.26737-2-kra...@redhat.com
---
include/ui/
To build the C parts of risu for ppc64le with recent glibc/kernel
headers, we need to include sys/user.h to avoid a compile error,
because sys/ucontext.h defines a struct which includes a pointer
to 'struct pt_regs' but does not provide a definition of that struct.
Signed-off-by: Peter Maydell
--
Peter Maydell writes:
> On Fri, 7 Jun 2019 at 10:05, Alex Bennée wrote:
>>
>> The following changes since commit 0d74f3b4277a7ecb0ccb80c865797d11f8e466f5:
>>
>> Merge remote-tracking branch
>> 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-06-06
>> 14:09:14 +0100)
>>
Am 07.06.2019 um 14:02 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 07.06.2019 11:06, Kevin Wolf wrote:
> > Am 07.06.2019 um 05:17 hat Eric Blake geschrieben:
> >> On 4/11/19 12:27 PM, Vladimir Sementsov-Ogievskiy wrote:
> >>> +static coroutine_fn void nbd_reconnect_loop(NBDConnection *con)
> >>
Patchew URL:
https://patchew.org/QEMU/20190607091116.49044-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v17 00/24] Add RX archtecture support
Message-id: 20190607091116.49044-1-ys...
Andreas Färber writes:
> Am 07.06.19 um 13:37 schrieb Paolo Bonzini:
>> QOM is not a particularly active subsystem now: 51 commits in two years.
>> But, we need active maintainers to review and merge patches, and Git
>> shows the following top committers taking on QOM:
>>
>> Markus Armbruste
On 5/17/19 7:40 PM, Peter Maydell wrote:
> Allow the DSP extension to be disabled via a CPU property for
> M-profile CPUs. (A and R-profile CPUs don't have this extension
> as a defined separate optional architecture extension, so
> they don't need the property.)
>
> Signed-off-by: Peter Maydell
Hi David,
I have digged further into our issue and we have seen issues only when
migrating from servers that have a different tsc frequency.
Example:
Source (kernel 4.14.63)
[2.068227] tsc: Refined TSC clocksource calibration: 2593.906 MHz
[2.068373] clocksource: tsc: mask: 0x
On 5/17/19 7:40 PM, Peter Maydell wrote:
> Allow VFP and neon to be disabled via a CPU property. As with
> the "pmu" property, we only allow these features to be removed
> from CPUs which have it by default, not added to CPUs which
> don't have it.
>
> The primary motivation here is to be able to
On 5/17/19 7:40 PM, Peter Maydell wrote:
> Create "vfp" and "dsp" properties on the armv7m container object
> which will be forwarded to its CPU object, so that SoCs can
> configure whether the CPU has these features.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/arm/armv7m.h | 4
>
On Fri, 7 Jun 2019 at 12:58, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Fri, 24 May 2019 at 10:42, Alex Bennée wrote:
> >>
> >>
> >> Jan Bobek writes:
> >>
> >> > This patch series adds support for i386 and x86_64 architectures to
> >> > RISU. Notably, vector registers (SSE, AVX, A
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Fixes check-qtest-rx: tests/qmp-cmd-test
>
> Signed-off-by: Richard Henderson
> Signed-off-by: Yoshinori Sato
Again:
Reviewed-by: Philippe Mathieu-Daudé
> ---
> qapi/common.json | 3 ++-
> 1 file changed, 2 insertions(
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Issue an error if no kernel, no bios, and not qtest'ing.
> Fixes make check-qtest-rx: test/qom-test.
>
> Signed-off-by: Richard Henderson
> Signed-off-by: Yoshinori Sato
Again:
Reviewed-by: Philippe Mathieu-Daudé
> ---
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Many of the multi-part prints have been eliminated by previous
> patches. Eliminate the rest of them.
>
> Reviewed-by: Yoshinori Sato
> Signed-off-by: Richard Henderson
Again:
Reviewed-by: Philippe Mathieu-Daudé
> Sign
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> There are so many different forms of each RX instruction
> that it will be very useful to be able to look at the bytes
> to see on which path a bug may lie.
>
> Reviewed-by: Yoshinori Sato
> Signed-off-by: Richard Henderson
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Note that the ld == 3 case handled by prt_ldmi is decoded as
> XCHG_rr and cannot appear here.
>
> Reviewed-by: Yoshinori Sato
> Signed-off-by: Richard Henderson
Again:
Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-b
On 6/7/19 8:06 AM, Peter Maydell wrote:
> The NSACR register allows secure code to configure the FPU
> to be inaccessible to non-secure code. If the NSACR.CP10
> bit is set then:
> * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2)
> * CPACR.{CP10,CP11} behave as if RAZ/WI
> * HCPTR.{T
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Collected, to be used in the next patch.
>
> Reviewed-by: Yoshinori Sato
> Signed-off-by: Richard Henderson
Again:
Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Yoshinori Sato
> ---
> target/rx/disas.c | 62
>
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Yoshinori Sato
> Message-Id: <20190516055244.95559-10-ys...@users.sourceforge.jp>
> Signed-off-by: Richard Henderson
> ---
> configure | 8 +
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> This has consistency with prt_ri(). It loads all data before
> beginning output. It uses exactly one call to prt() to emit
> the full instruction.
>
> Reviewed-by: Yoshinori Sato
> Signed-off-by: Richard Henderson
Again
On Mon, Jun 03, 2019 at 06:08:18PM +0530, Aarushi Mehta wrote:
> +static void qemu_luring_process_completions(LuringState *s)
> +{
> +struct io_uring_cqe *cqes;
> +int ret;
> +
> +/*
> + * Request completion callbacks can run the nested event loop.
> + * Schedule ourselves so th
On Fri, Jun 07, 2019 at 12:59:54PM +0200, Sergio Lopez wrote:
> I gave this version of the patchset a try, and found that IO hangs when
> the device is assigned to an IOThread. Sometimes is able to serve a few
> requests getting through the Guest OS boot process, to hang the moment
> you try genera
monitor.c mixes a lot of different things in a single file: The core
monitor infrastructure, HMP infrastrcture, QMP infrastructure, and the
implementation of several HMP and QMP commands. Almost worse, struct
Monitor mixes state for HMP, for QMP, and state actually shared between
all monitors. moni
Create a new monitor/ subdirectory and move monitor.c there. As the plan
is to move the monitor core into separate files, use the chance to
rename it to misc.c.
Signed-off-by: Kevin Wolf
---
monitor.c => monitor/misc.c | 0
Makefile.target | 3 ++-
monitor/Makefile.objs | 1 +
Instead of mixing HMP and QMP monitors in the same function, separate
the monitor creation function for both.
Signed-off-by: Kevin Wolf
---
monitor.c | 86 +++
1 file changed, 49 insertions(+), 37 deletions(-)
diff --git a/monitor.c b/monitor.
Commit 788cf9f8c removed the code for password prompting from the
monitor. Since then, the Monitor fields password_completion_cb and
password_opaque have been unused. Remove them.
Signed-off-by: Kevin Wolf
---
monitor.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/monitor.c b/monitor.c
i
Monitor.cmd_table contains the handlers for HMP commands, so there is no
reason to keep it in the state shared with QMP. Move it to MonitorHMP.
Signed-off-by: Kevin Wolf
---
monitor.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/monitor.c b/monitor
Move the monitor core infrastructure from monitor/misc.c to
monitor/core.c. This is code that can be shared for all targets, so
compile it only once.
What remains in monitor/misc.c after this patch is mostly monitor
command implementations and code that requires a system emulator or is
even target
Before we can split monitor.c, we need to create a header file that
contains the common definitions that will be used by multiple source
files.
Signed-off-by: Kevin Wolf
---
monitor/monitor_int.h | 147 ++
monitor/misc.c| 110 +-
The ReadLineState in Monitor is only used for HMP monitors. Create
MonitorHMP and move it there.
Signed-off-by: Kevin Wolf
---
include/monitor/monitor.h | 5 +-
hmp.c | 4 +-
monitor.c | 123 +-
3 files changed, 75 inser
Move HMP infrastructure from monitor/misc.c to monitor/hmp.c. This is
code that can be shared for all targets, so compile it only once.
The amount of function and particularly extern variables in
monitor_int.h is probably a bit larger than it needs to be, but this way
no non-trivial code modificat
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> Fixes check-qtest-rx: tests/machine-none-test.
>
> Signed-off-by: Richard Henderson
Again:
Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Yoshinori Sato
> ---
> tests/machine-none-test.c | 1 +
> 1 file changed,
Currently, struct Monitor mixes state that is only relevant for HMP,
state that is only relevant for QMP, and some actually shared state.
In particular, a MonitorQMP field is present in the state of any
monitor, even if it's not a QMP monitor and therefore doesn't use the
state.
As a first step to
viewers because you don't have
to re-review the same code twice.
>
> My git repository is bellow.
> git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190607
>
> Testing binaries bellow.
> u-boot
> Download - https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.g
On Fri, Jun 07, 2019 at 03:54:20PM +0200, Kevin Wolf wrote:
> monitor.c mixes a lot of different things in a single file: The core
> monitor infrastructure, HMP infrastrcture, QMP infrastructure, and the
> implementation of several HMP and QMP commands. Almost worse, struct
> Monitor mixes state fo
On 07/06/2019 11:29, Laurent Vivier wrote:
> On 29/05/2019 08:49, David Gibson wrote:
>> From: Richard Henderson
>>
>> The gvec expanders take care of masking the shift amount
>> against the element width.
>>
>> Signed-off-by: Richard Henderson
>> Message-Id: <20190518191430.21686-2-richard.hende
Move QMP infrastructure from monitor/misc.c to monitor/qmp.c. This is
code that can be shared for all targets, so compile it only once.
The amount of function and particularly extern variables in
monitor_int.h is probably a bit larger than it needs to be, but this way
no non-trivial code modificat
Commit d52c454aad "contrib: add vhost-user-gpu" and "c68082c43a
virtio-gpu: split virtio-gpu-pci & virtio-vga" created headers with
unusual header guard symbols. Clean them up
Signed-off-by: Markus Armbruster
---
contrib/vhost-user-gpu/virgl.h | 5 +++--
contrib/vhost-user-gpu/vugbm.h | 5 +++--
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> New CPUs should not be suffixed like other devices.
>
> Signed-off-by: Yoshinori Sato
> ---
> include/hw/rx/rx62n.h | 2 +-
> target/rx/cpu.h | 3 +--
> target/rx/cpu.c | 8 ++--
> 3 files changed, 4 insertions(+), 9 deletions(-)
>
> d
On Fri, Jun 07, 2019 at 12:59:54PM +0200, Sergio Lopez wrote:
> I gave this version of the patchset a try, and found that IO hangs when
> the device is assigned to an IOThread. Sometimes is able to serve a few
> requests getting through the Guest OS boot process, to hang the moment
> you try genera
Peter Maydell writes:
> To build the C parts of risu for ppc64le with recent glibc/kernel
> headers, we need to include sys/user.h to avoid a compile error,
> because sys/ucontext.h defines a struct which includes a pointer
> to 'struct pt_regs' but does not provide a definition of that struct.
On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson
>
> There was confusion here about abstract classes and naming cpus.
> We had registered a concrete class named "-rxcpu". This was put
> into the default cpu fields, and matched, so basic tests worked.
> However, no value for -c
From: David Hildenbrand
Core logic courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31 +
target/s390x/vec_string_
Cc'ing Drew and Eric
On 6/7/19 3:07 PM, Peter Maydell wrote:
> Ping for code review, please?
>
> thanks
> -- PMM
>
> On Thu, 16 May 2019 at 15:47, Peter Maydell wrote:
>>
>>
>> This patchset attempts to fix https://bugs.launchpad.net/qemu/+bug/1823998
>> which reports that we don't handle kerne
On 6/7/19 8:44 AM, Philippe Mathieu-Daudé wrote:
> Again:
>
> Please squash in:
>
> -- >8 --
> --- a/include/exec/poison.h
> +++ b/include/exec/poison.h
> @@ -26,6 +26,7 @@
> #pragma GCC poison TARGET_PPC
> #pragma GCC poison TARGET_PPC64
> #pragma GCC poison TARGET_ABI32
> +#pragma GCC poison
Hi Peter,
Sorry for the delay in replying to this...
On Thu, May 16, 2019 at 03:47:29PM +0100, Peter Maydell wrote:
>
> This patchset attempts to fix https://bugs.launchpad.net/qemu/+bug/1823998
> which reports that we don't handle kernels larger than 128MB
> correctly, because we allow the init
The generic s390 section looks like the best resting place.
Message-Id: <20190529091243.25562-1-coh...@redhat.com>
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a96829ea83a2..7be122541583 100644
--- a/MAINTAINERS
From: David Hildenbrand
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.h | 2 +-
On 6/7/19 4:03 PM, Richard Henderson wrote:
> On 6/7/19 8:44 AM, Philippe Mathieu-Daudé wrote:
>> Again:
>>
>> Please squash in:
>>
>> -- >8 --
>> --- a/include/exec/poison.h
>> +++ b/include/exec/poison.h
>> @@ -26,6 +26,7 @@
>> #pragma GCC poison TARGET_PPC
>> #pragma GCC poison TARGET_PPC64
>>
On Tue, Jun 04, 2019 at 08:00:19PM +0100, Dr. David Alan Gilbert wrote:
* Michael S. Tsirkin (m...@redhat.com) wrote:
On Tue, Jun 04, 2019 at 03:43:21PM +0200, Jens Freimann wrote:
> On Mon, Jun 03, 2019 at 04:36:48PM -0300, Eduardo Habkost wrote:
> > On Mon, Jun 03, 2019 at 10:24:56AM +0200, Je
From: David Hildenbrand
Complicated stuff. Provide two different helpers for CC an !CC handling.
We might want to add more helpers later.
zero_search() and match_index() are courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/Makefile.objs
From: David Hildenbrand
The PoP (z14, 7-382) says:
Doublewords to the right of the doubleword in which the
highest-numbered facility bit is assigned for a model
may or may not be stored.
However, stack protection in certain binaries can't deal with that.
"gzip" example code:
f1b4:
On Fri, 7 Jun 2019 15:02:33 +0200
David Hildenbrand wrote:
> This pull request is not for master.
>
> Hi Cornelia,
>
> second attempt :)
>
> The following changes since commit 33556237f652d8a712d0b6d29ecb442e6b65fe42:
>
> Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-
From: David Hildenbrand
1. We'll reuse op_vfa() for similar instructions later, prepare for
that.
2. We'll reuse vop64_3() for other instructions later.
3. Take care of modifying the vector register only if no trap happened.
- on traps, flags are not updated and no elements are modified
- tr
Stefan Hajnoczi writes:
> On Fri, Jun 07, 2019 at 12:59:54PM +0200, Sergio Lopez wrote:
>> I gave this version of the patchset a try, and found that IO hangs when
>> the device is assigned to an IOThread. Sometimes is able to serve a few
>> requests getting through the Guest OS boot process, to
From: David Hildenbrand
Take care of reading/indicating the 32-bit elements.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 ++
target/s3
From: David Hildenbrand
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed,
From: David Hildenbrand
1. We'll reuse op_vcdg() for similar instructions later, prepare for
that.
2. We'll reuse vop64_2() later for other instructions.
We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.
Make sure to restor
The following changes since commit 33556237f652d8a712d0b6d29ecb442e6b65fe42:
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-7-2019'
into staging (2019-06-07 11:17:28 +0100)
are available in the Git repository at:
https://github.com/cohuck/qemu tags/s390x-
From: David Hildenbrand
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 4 +++
target/s390x/translate_vx.inc.c | 23
target/s390x/vec_fpu_helper.c | 48 ++
From: David Hildenbrand
The only FP instruction we can implement without an helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +
2 files changed, 54 insertio
From: David Hildenbrand
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed,
From: David Hildenbrand
Logic mostly courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34
target/s390x/v
From: David Hildenbrand
used_stfl_bytes is 0, before initialized via prepare_stfl() on the
first invocation. We have to move the calculation of max_bytes after
prepare_stfl().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/misc_helper.c | 3 ++-
1 file change
From: David Hildenbrand
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at locat
From: David Hildenbrand
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed,
From: David Hildenbrand
We can reuse float64_dcmask().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 21 +++
target/s390x/vec_fpu_helper.c
From: Richard Henderson
This replaces the target-specific implementations for VSEL.
Signed-off-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/translate_vx.inc.c | 38 ++---
1 file changed, 6 insertions(+), 32 deletions(-)
diff --git a/targ
From: David Hildenbrand
As far as I can see, there is only a tiny difference.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 21 +
tar
From: David Hildenbrand
We don't care about the other two missing base features:
- S390_FEAT_DFP_PACKED_CONVERSION
- S390_FEAT_GROUP_GEN13_PTFF
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
hw/s390x/s390-virtio-ccw.c | 2 ++
target/s390x/cpu_models.c | 4 ++--
targe
From: David Hildenbrand
Let's add it to the max model, so we can enable it.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/gen-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index c346b
>
> are available in the Git repository at:
>
> git://git.kraxel.org/qemu tags/ui-20190607-pull-request
>
> for you to fetch changes up to 15ee0d9bc10b3de677ff6cd78b6dc9d5a7d40603:
>
> egl-helpers: add modifier support to egl_d
From: David Hildenbrand
Let's add all HWCAPs that we can support under TCG right now, when the
respective CPU facilities are enabled.
Cc: Riku Voipio
Cc: Laurent Vivier
Cc: Cornelia Huck
Cc: Laurent Vivier
Cc: Richard Henderson
Acked-by: Laurent Vivier
Reviewed-by: Richard Henderson
Signe
From: David Hildenbrand
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
able to make use of it.
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s
From: David Hildenbrand
We can reuse most of the infrastructure added for VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x
Am 07.06.2019 um 16:03 hat Daniel P. Berrangé geschrieben:
> On Fri, Jun 07, 2019 at 03:54:20PM +0200, Kevin Wolf wrote:
> > monitor.c mixes a lot of different things in a single file: The core
> > monitor infrastructure, HMP infrastrcture, QMP infrastructure, and the
> > implementation of several
On Fri, 7 Jun 2019 18:11:05 +0900
Yoshinori Sato wrote:
> From: Richard Henderson
>
> There was confusion here about abstract classes and naming cpus.
> We had registered a concrete class named "-rxcpu". This was put
> into the default cpu fields, and matched, so basic tests worked.
> However
I have verified the second issue: the second call of function gives error
"Cannot access memory at address".
I have tried it for various architectures. It is same for mips. But it works
for aarch64.
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From: David Hildenbrand
We can reuse most of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/tr
07.06.2019 16:26, Kevin Wolf wrote:
> Am 07.06.2019 um 14:02 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 07.06.2019 11:06, Kevin Wolf wrote:
>>> Am 07.06.2019 um 05:17 hat Eric Blake geschrieben:
On 4/11/19 12:27 PM, Vladimir Sementsov-Ogievskiy wrote:
> +static coroutine_fn void nbd_
On Fri, Jun 07, 2019 at 04:14:07PM +0200, Jens Freimann wrote:
> On Tue, Jun 04, 2019 at 08:00:19PM +0100, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Jun 04, 2019 at 03:43:21PM +0200, Jens Freimann wrote:
> > > > On Mon, Jun 03, 2019 at 04:36:48PM
From: David Hildenbrand
We can reuse some of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/tr
06.06.2019 21:41, John Snow wrote:
> Instead of bdrv_can_store_new_bitmap, rework this as
> bdrv_add_persistent_dirty_bitmap. This makes a more obvious symmetry
> with bdrv_remove_persistent_dirty_bitmap. Most importantly, we are free
> to modify the driver state because we know we ARE adding a bit
From: David Hildenbrand
Very similar to VECTOR FP DIVIDE.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 ++
On Fri, Jun 07, 2019 at 04:25:14PM +0200, Kevin Wolf wrote:
> Am 07.06.2019 um 16:03 hat Daniel P. Berrangé geschrieben:
> > On Fri, Jun 07, 2019 at 03:54:20PM +0200, Kevin Wolf wrote:
> > > monitor.c mixes a lot of different things in a single file: The core
> > > monitor infrastructure, HMP infra
From: David Hildenbrand
CPU_DoubleU is primarily used to reinterpret between integer and floats.
We don't really need this functionality. So let's just keep it simple
and use an uint64_t.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
linux-user/s390x/signal.c | 4 +-
From: David Hildenbrand
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing
helper function.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c |
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Add the infrastructure for building and invoking a decodetree decoder
> for the AArch32 VFP encodings. At the moment the new decoder covers
> nothing, so we always fall back to the existing hand-written decode.
>
> We need to have one decoder for the unc
A vfio-ccw device may provide an async command subregion for
issuing halt/clear subchannel requests. If it is present, use
it for sending halt/clear request to the device; if not, fall
back to emulation (as done today).
Signed-off-by: Cornelia Huck
---
v4->v5:
- It seems we need to take the indi
From: David Hildenbrand
Similar to VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 ++
On Tue, 4 Jun 2019 at 00:22, Richard Henderson
wrote:
>
> These instructions shift left or right depending on the sign
> of the input, and 7 bits are significant to the shift. This
> requires several masks and selects in addition to the actual
> shifts to form the complete answer.
>
> That said,
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VSEL instructions to decodetree.
> We leave trans_VSEL() in translate.c for now as this allows
> the patch to show just the changes from the old handle_vsel().
>
> In the old code the check for "do D16-D31 exist" was hidden in
> the VFP_DREG m
On 6/6/19 12:45 PM, Peter Maydell wrote:
> The Cortex-R5F initfn was not correctly setting up the MVFR
> ID register values. Fill these in, since some subsequent patches
> will use ID register checks rather than CPU feature bit checks.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/cpu.c |
On 6/7/19 9:09 AM, Laurent Vivier wrote:
> On 07/06/2019 11:29, Laurent Vivier wrote:
>> On 29/05/2019 08:49, David Gibson wrote:
>>> From: Richard Henderson
>>>
>>> The gvec expanders take care of masking the shift amount
>>> against the element width.
>>>
>>> Signed-off-by: Richard Henderson
>>
06.06.2019 21:41, John Snow wrote:
> When we check to see if we can store a bitmap, we don't check how many
> we've queued up. This can cause a problem saving bitmaps on close
> instead of when we request them to be added. With the stricter add
> interface, prohibit these bitmaps specifically.
>
>
Am 07.06.2019 um 16:27 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 07.06.2019 16:26, Kevin Wolf wrote:
> > Am 07.06.2019 um 14:02 hat Vladimir Sementsov-Ogievskiy geschrieben:
> >> 07.06.2019 11:06, Kevin Wolf wrote:
> >>> Am 07.06.2019 um 05:17 hat Eric Blake geschrieben:
> On 4/11/19 12:
On 06/07/2019 10:53 AM, Cornelia Huck wrote:
A vfio-ccw device may provide an async command subregion for
issuing halt/clear subchannel requests. If it is present, use
it for sending halt/clear request to the device; if not, fall
back to emulation (as done today).
Signed-off-by: Cornelia Huck
Hi Bastian,
> Hi,
>
> On 6/5/19 8:11 AM, David Brenken wrote:
> > +/*
> > + * Target TriCore QSEED.F significand Lookup Table
> > + *
> > + * The QSEED.F output significand depends on the least-significant
> > + * exponent bit and the 6 most-significant significand bits.
> > + *
> > + * IEEE 754
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