Hi Yoshinori, On 6/7/19 11:10 AM, Yoshinori Sato wrote: > Hello. > This patch series is added Renesas RX target emulation. > > Changes v17. > Remove cpu class name suffix.
I was a bit annoyed you did not collect my review effort from the previous series. It is time-saving for reviewers because you don't have to re-review the same code twice. > > My git repository is bellow. > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190607 > > Testing binaries bellow. > u-boot > Download - https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz > > starting > $ gzip -d u-boot.bin.gz > $ qemu-system-rx -bios u-boot.bin > > linux and pico-root (only sash) > Download - https://osdn.net/users/ysato/pf/qemu/dl/zImage (kernel) > https://osdn.net/users/ysato/pf/qemu/dl/rx-qemu.dtb (DeviceTree) > > starting > $ qemu-system-rx -kernel zImage -dtb rx-qemu.dtb -append "earlycon" > > > Richard Henderson (11): > target/rx: Convert to CPUClass::tlb_fill > target/rx: Add RX to SysEmuTarget > target/rx: Fix cpu types and names > tests: Add rx to machine-none-test.c > hw/rx: Honor -accel qtest > target/rx: Disassemble rx_index_addr into a string > target/rx: Replace operand with prt_ldmi in disassembler > target/rx: Use prt_ldmi for XCHG_mr disassembly > target/rx: Emit all disassembly in one prt() > target/rx: Collect all bytes during disassembly > target/rx: Dump bytes for each insn during disassembly > > Yoshinori Sato (13): > target/rx: TCG translation > target/rx: TCG helper > target/rx: CPU definition > target/rx: RX disassembler > hw/intc: RX62N interrupt controller (ICUa) > hw/timer: RX62N internal timer modules > hw/char: RX62N serial communication interface (SCI) > hw/rx: RX Target hardware definition > qemu/bitops.h: Add extract8 and extract16 > hw/registerfields.h: Add 8bit and 16bit register macros > Add rx-softmmu > MAINTAINERS: Add RX > target/rx: Remove suffix in cpu class. I'd move the last patch directly after "target/rx: Fix cpu types and names". Actually I rebased it this way: [PATCH 01/24] target/rx: TCG translation [PATCH 02/24] target/rx: TCG helper [PATCH 03/24] target/rx: CPU definition [PATCH 04/24] target/rx: RX disassembler [PATCH 18/24] target/rx: Disassemble rx_index_addr into a string [PATCH 19/24] target/rx: Replace operand with prt_ldmi in disassembler [PATCH 20/24] target/rx: Use prt_ldmi for XCHG_mr disassembly [PATCH 21/24] target/rx: Emit all disassembly in one prt() [PATCH 22/24] target/rx: Collect all bytes during disassembly [PATCH 23/24] target/rx: Dump bytes for each insn during disassembly [PATCH 05/24] hw/intc: RX62N interrupt controller (ICUa) [PATCH 06/24] hw/timer: RX62N internal timer modules [PATCH 07/24] hw/char: RX62N serial communication interface (SCI) [PATCH 08/24] hw/rx: RX Target hardware definition [PATCH 09/24] qemu/bitops.h: Add extract8 and extract16 [PATCH 10/24] hw/registerfields.h: Add 8bit and 16bit register macros [PATCH 11/24] target/rx: Convert to CPUClass::tlb_fill [PATCH 13/24] target/rx: Fix cpu types and names [PATCH 24/24] target/rx: Remove suffix in cpu class. [PATCH 12/24] target/rx: Add RX to SysEmuTarget [PATCH 14/24] tests: Add rx to machine-none-test.c [PATCH 15/24] hw/rx: Honor -accel qtest [PATCH 16/24] Add rx-softmmu [PATCH 17/24] MAINTAINERS: Add RX On Linux + win32 running u-boot + Linux as suggested: Tested-by: Philippe Mathieu-Daudé <phi...@redhat.com>
