Philippe Mathieu-Daudé writes:
> Le lun. 11 mars 2019 17:02, Markus Armbruster a écrit :
>
>> Paolo Bonzini writes:
[...]
>> > Does it work if you add the device yourself as a child of /machine,
>> > instead of relying on /machine/unattached?
>>
>> I figure you're suggesting something like this
On 11/03/2019 18.55, Paolo Bonzini wrote:
> On 11/03/19 17:55, Alex Bennée wrote:
>> I'm the sole author (aside from a one line by Greg fixing encoding)
>> and I was asked nicely on IRC to bring it into line with the rest of
>> the files.
>>
>> Cc: Greg Kurz
>> Signed-off-by: Alex Bennée
>> ---
>
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
28c2bf374c447c20937a192695c7b9f5367dea7e.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_legacy.c | 16
audio/wavaudio.c | 58 +++-
2 file
From: Kővágó, Zoltán
Audio drivers now get an Audiodev * as config paramters, instead of the
global audio_option structs. There is some code in audio/audio_legacy.c
that converts the old environment variables to audiodev options (this
way backends do not have to worry about legacy options). It
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
ba58f7e2501b1454b5e0f91c03aad416a404fc6a.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_legacy.c | 28 +
audio/coreaudio.c| 49 ++-
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
040d1241f29104ecfeecb26b0a14f0d042484fc5.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/spiceaudio.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/audio/spiceaudio.c b/audio/spiceaudio.c
ind
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
f25562cb88246b41c3e6380685a108fd341d5b50.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/dsound_template.h | 6 ++---
audio/audio_legacy.c| 43 ++
audio/dsoundaudio.c
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
663d2c918a11ef44d4042e56c796d6dbf40be70c.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/alsaaudio.c| 329 +--
audio/audio_legacy.c | 84 ++-
2 file
On Tue, Mar 12, 2019 at 03:42:21PM +1100, Alexey Kardashevskiy wrote:
> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
> space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
> implements special regions for such GPUs and emulates an NVLink bridge.
> NVL
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
c74dc9c282075fba6928c40b2deae057fa0d4049.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_legacy.c | 38 +
audio/paaudio.c | 81 ---
Hi,
> +if (cursorVisible && cursorImage && NSIntersectsRect(rect,
> cursorRect)) {
> +CGContextDrawImage (viewContextRef, cursorRect, cursorImage);
So you are rendering the cursor to the window.
Better approach would be to just set the cursor of the host window,
like the g
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
1dc596cba39378df862582a0b952e497a16c6c31.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_legacy.c | 12
audio/sdlaudio.c | 22 --
2 files changed, 16 insertio
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
31c899f2f78e40fbc01f563ee4829c98debb68db.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_legacy.c | 32 +
audio/ossaudio.c | 161 ++-
2 files
From: Kővágó, Zoltán
This patch adds structures into qapi to replace the existing
configuration structures used by audio backends currently. This qapi
will be the base of the -audiodev command line parameter (that replaces
the old environment variables based config).
This is not a 1:1 translatio
The following changes since commit e2a18635a400b0e68679614132e9ef6316105590:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-03-08' into
staging (2019-03-09 20:55:44 +)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/audio-20190312-pu
From: Kővágó, Zoltán
Signed-off-by: Kővágó, Zoltán
Message-id:
0c35b1956ed1105244309a774c038816c040108c.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/noaudio.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/audio/noaudio.c b/audio/noaudio.c
index 79690af1eab
From: Kővágó, Zoltán
Remove no longer needed code.
Signed-off-by: Kővágó, Zoltán
Message-id:
82c176a5222a56e4fde45d2b423ada797caddd5d.1552083282.git.dirty.ice...@gmail.com
Signed-off-by: Gerd Hoffmann
---
audio/audio_int.h | 17 -
audio/audio.c | 186 +---
Hi,
> >> +# @buffer-length: the buffer length in microseconds
> >
> > The name buffer-length suggests bytes rather than microseconds. That's
> > why I suggested @buffer-capacity. Matter of taste, up to you and Gerd.
>
> @period-length has the same issue. For me @buffer-capacity and
> @perio
From: Kővágó, Zoltán
I had to include an enum for audio sampling formats into qapi, but that
meant duplicating the audfmt_e enum. This patch replaces audfmt_e and
associated values with the qapi generated AudioFormat enum.
This patch is mostly a search-and-replace, except for switches where the
From: Kővágó, Zoltán
This patch adds documentation of an -audiodev command line option, that
deprecates the old QEMU_* environment variables for audio backend
configuration. It's syntax is similar to existing options (-netdev,
-device, etc):
-audiodev driver_name,property=value,...
Although
This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number.
Signed-off-by: Wei Yang
---
hw/arm/virt-acpi-build.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index d7e2e4885b..57679a89bf 100644
--- a/hw/arm/
When we stop a VM for more than 30 seconds and then resume it, by qemu
monitor command "stop" and "cont", Linux on VM will complain of "soft
lockup - CPU#x stuck for xxs!" as below:
[ 2783.809517] watchdog: BUG: soft lockup - CPU#3 stuck for 2395s!
[ 2783.809559] watchdog: BUG: soft lockup - CPU#2
Hi all,
I'm sorry this patch failed the docker-mingw@fedora build test. I'm going to
move the code to target/arm/kvm.c.
Please ignore this one.
Thanks,
Heyi
On 2019/3/12 14:09, Heyi Guo wrote:
When we stop a VM for more than 30 seconds and then resume it, by qemu
monitor command "stop" and
HWADDR_PRIx can't be used in tracing, use PRIx64 instead.
Signed-off-by: Gerd Hoffmann
---
hw/display/trace-events | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/display/trace-events b/hw/display/trace-events
index 80993cc4d913..c09854314b03 100644
--- a/hw/display/tr
On Mon, 11 Mar 2019 16:55:38 +
Alex Bennée wrote:
> I'm the sole author (aside from a one line by Greg fixing encoding)
> and I was asked nicely on IRC to bring it into line with the rest of
> the files.
>
> Cc: Greg Kurz
> Signed-off-by: Alex Bennée
> ---
Reviewed-by: Greg Kurz
> scri
27.02.2019 18:25, Max Reitz wrote:
> CC-ing John because of the keyword "incremental".
>
> On 14.02.19 07:43, mahaocong wrote:
>> From: mahaocong
>>
>> This patch adds possibility to start mirroring with user-created-bitmap.
>> On full mode, mirror create a non-named-bitmap by scanning whole bloc
NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
implements special regions for such GPUs and emulates an NVLink bridge.
NVLink2-enabled POWER9 CPUs also provide address translation services
which inclu
On Mon, Mar 11, 2019 at 04:32:34PM +0800, Wei Yang wrote:
> Function object_new_with_propv already get the Type of the object, so we
> could leverage object_new_with_type here.
>
> [make check test pass]
>
> Signed-off-by: Wei Yang
> ---
> qom/object.c | 2 +-
> 1 file changed, 1 insertion(+),
Hi
On 3/12/19 8:49 AM, Wei Yang wrote:
> This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number.
>
> Signed-off-by: Wei Yang
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/arm/virt-acpi-build.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm
On Mon, 11 Mar 2019 06:52:33 PDT (-0700), pbonz...@redhat.com wrote:
On 11/03/19 13:46, Thomas Huth wrote:
On 11/03/2019 10.12, David Abdurachmanov wrote:
Re-enable PCI_DEVICES for RISC-V.
The patch is based on other /Kconfig.
Signed-off-by: David Abdurachmanov
Fixes: 82a230d5a303 ("riscv-sof
On Mon, 11 Mar 2019 21:44:22 +0100
Cédric Le Goater wrote:
> On 2/26/19 12:49 AM, David Gibson wrote:
> > On Fri, Feb 22, 2019 at 02:13:12PM +0100, Cédric Le Goater wrote:
> >> All is in place for KVM now. State synchronization and migration will
> >> come next.
> >
> > As with the kernel si
From: Greg Kurz
The RTAS event hotplug code for machine types 2.8 and newer depends on
the CAS negotiated ov5 in order to work properly. However, there's no
CAS when running under qtest. There has been a tentative to trick the
code by faking the OV5_HP_EVT bit, but it turned out to break other
as
From: Suraj Jitindar Singh
Enable the large decrementer by default for the pseries-4.0 machine type.
It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus
since they don't support the large decrementer.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <20190301024317.22137-4-sjitin
The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-03-11 18:26:37 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.0-201
From: Greg Kurz
Commit b8165118f52c broke CPU hotplug tests for old machine types:
$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test
-m=slow
/ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK
/ppc64
From: Alexey Kardashevskiy
The "systempagesize" name suggests that it is the host system page size
while it is the smallest page size of memory backing the guest RAM so
let's rename it to stop confusion. This should cause no behavioral change.
Signed-off-by: Alexey Kardashevskiy
Message-Id: <20
From: Suraj Jitindar Singh
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
for mitigations for indirect branch speculation. Currently the available
values are broken (default), fixed-ibs (fixed by serialising indirect
branches) and fixed-ccd (fixed by diabling the count ca
From: Fabiano Rosas
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas
Message-Id: <20190228225759.21328-4-faro...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/kvm.c | 47 --
From: Alexey Kardashevskiy
The current code assumes that we can address more bits on a PCI bus
for DMA than we really can but there is no way knowing the actual limit.
This makes a better guess for the number of levels and if the kernel
fails to allocate that, this increases the level numbers ti
From: Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability of the large decrementer for a guest.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <20190301024317.22137-1-sjitindarsi...@gmail.com>
[dwg: Trivial style fix]
Signed-off-by: David Gibso
From: Fabiano Rosas
There are four scenarios being handled in this function:
- single stepping
- hardware breakpoints
- software breakpoints
- fallback (no debug supported)
A future patch will add code to handle specific single step and
software breakpoints cases so let's split each scenario in
From: Cédric Le Goater
The POWER9 and POWER8 processors have different interrupt controllers,
and reporting their state requires calling different helper routines.
However, the interrupt presenters are still handled in the higher
level pic_print_info() routine because they are not related to the
From: Suraj Jitindar Singh
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also n
From: Suraj Jitindar Singh
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch.
From: Cédric Le Goater
This is a simple helper to translate XSCOM addresses to MMIO addresses
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-13-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_psi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff -
From: Mark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a
single vsrl_offset() function.
This commit also renames the existing get_vsr()/set_vsr() functions to
get_vsrl()/set_vsrl() which better describes their purpose.
Signed-off-by: Mark Cave-Aylan
From: Suraj Jitindar Singh
Prior to POWER9 the decrementer was a 32-bit register which decremented
with each tick of the timebase. From POWER9 onwards the decrementer can
be set to operate in a mode called large decrementer where it acts as a
n-bit decrementing register which is visible as a 64-b
From: Suraj Jitindar Singh
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and
hence of type hwaddr which is 64-bit. Previously it wasn't marked as such
which means that it could be treated as 32-bit. That will work in some
circumstances but if multiplied by another 32-bit value it could lead to
a 32
From: Cédric Le Goater
The PowerNV machine with need to encode the block id in the source
interrupt number before forwarding the source event notification to
the Router.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-5-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/x
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Alexey Kardashevskiy
Message-Id: <20190228225759.21328-2-faro...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/excp_helper.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff -
From: Suraj Jitindar Singh
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest
memory. Enable the in-kernel H_PAGE_INIT handler.
The in-kernel handler takes half the time to complete compared to
handling the H_CALL in userspace.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <2
From: Cédric Le Goater
By default on P9, the HW CAM line (23bits) is hardwired to :
0x000||0b1||4Bit chip number||7Bit Thread number.
When the block group mode is enabled at the controller level (PowerNV),
the CAM line is changed for CAM compares to :
4Bit chip number||0x001||7Bit
From: Cédric Le Goater
The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
set through XSCOM but the controls are now entirely done with MMIOs.
More interrupts are defined and the interrupt controller interface has
changed to XIVE. The POWER9 model is a first example of the usage
From: Suraj Jitindar Singh
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the
availability of certain mitigations to the guest. These haven't been
implemented under TCG, it is unlikely they ever will be, and it is unclear
as to whether they even need to be.
As such, make failu
From: Suraj Jitindar Singh
There are currently 3 mitigations the availability of which is controlled
by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these
mitigations by default for the pseries-4.0 machine type.
By now machine firmware should have been upgraded to allow thes
From: Cédric Le Goater
This is a simple model of the POWER9 XIVE interrupt controller for the
PowerNV machine which only addresses the needs of the skiboot
firmware. The PowerNV model reuses the common XIVE framework developed
for sPAPR as the fundamentals aspects are quite the same. The
differen
From: Alexey Kardashevskiy
On sPAPR vfio_listener_region_add() is called in 2 situations:
1. a new listener is registered from vfio_connect_container();
2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window().
In both cases vfio_listener_region_add() calls
memory_region_iommu_
From: Cédric Le Goater
The POWER9 and POWER8 processors have a different set of devices and a
different device tree layout.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 27 +--
From: Cédric Le Goater
Reset all regs but keep the MMIO BAR enabled as it is at realize time.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-14-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_psi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw
From: Mark Cave-Ayland
All TCG vector operations require pointers to the base address of the vector
rather than separate access to the top and bottom 64-bits. Convert the VMX TCG
instructions to use a new avr_full_offset() function instead of avr64_offset()
which can then itself be written as a s
From: Mark Cave-Ayland
When using -drive to configure the hd drive for the Old World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307212058.4890-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
---
hw/ppc
From: Andrew Randrianasulu
Original commit message:
This patch adds an emulation model for i2c controller found on most of the FSL
SoCs.
It also integrates the RTC (ds1338) that sits on the i2c Bus with e500 machine
model.
Patch was originally written by Amit Singh Tomar
see http://patchwork.
From: Mark Cave-Ayland
It isn't possible to include internal.h from cpu.h so move the Vsr* macros
into cpu.h alongside the other VMX/VSX register access functions.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307180520.13868-4-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Richard Henderson
From: Cédric Le Goater
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
res
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-12-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c | 10 +-
hw/ppc/pnv_psi.c | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_l
From: Cédric Le Goater
The POWER9 PowerNV machine will use a XIVE interrupt presenter type.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-6-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 6 +++---
hw/ppc/pnv_core.c | 2 +-
include/hw/ppc/
From: Mark Cave-Ayland
When VSX support was initially added, the fpr registers were added at
offset 0 of the VSR register and the vsrl registers were added at offset
1. This is in contrast to the VMX registers (the last 32 VSX registers) which
are stored in host-endian order.
Switch the fpr/vsrl
From: Mark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a
single fpr_offset() function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190307180520.13868-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
--
From: Mark Cave-Ayland
When using -drive to configure the hd drive for the New World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307212058.4890-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
---
hw/ppc
From: Cédric Le Goater
The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-4-...@kao
On 3/11/19 12:29 PM, Yuval Shaia wrote:
> Add counters to enable enhance debugging
>
> Signed-off-by: Yuval Shaia
> ---
> hw/rdma/rdma_backend.c| 70
> +++
> hw/rdma/rdma_rm.c | 7 +
> hw/rdma/rdma_rm_defs.h| 27 +++
From: Cédric Le Goater
It will ease the introduction of the LPC Controller model for POWER9.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190307223548.20516-5-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_lpc.c
From: Cédric Le Goater
The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-10-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c
From: Cédric Le Goater
We will use it to get the CPU interrupt presenter in XIVE when the
TIMA is accessed from the indirect page.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-3-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 16
hw/p
From: Cédric Le Goater
This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c | 14 ++
include/hw/ppc/pnv_lpc.h | 2 ++
2 fi
From: Suraj Jitindar Singh
There are currently 3 mitigations the availability of which is controlled
by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these
mitigations by default for the pseries-4.0 machine type.
By now machine firmware should have been upgraded to allow thes
From: Mark Cave-Ayland
Now that all VSX registers are stored in host endian order, there is no need
to go via different accessors depending upon the register number. Instead we
introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and
set_cpu_vsr{l,h}().
This also allows us
From: Cédric Le Goater
Provide a new class attribute to define XSCOM operations per CPU
family and add a couple of XSCOM addresses controlling the power
management states of the core on POWER9.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-11-...@kaod.org>
Signed-off-by: Dav
Gerd Hoffmann writes:
> HWADDR_PRIx can't be used in tracing, use PRIx64 instead.
>
> Signed-off-by: Gerd Hoffmann
> ---
> hw/display/trace-events | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/display/trace-events b/hw/display/trace-events
> index 80993cc4d913.
On 3/11/19 12:29 PM, Yuval Shaia wrote:
> This hook is not called and was implemented by mistake.
>
> Signed-off-by: Yuval Shaia
> Reviewed-by: Marcel Apfelbaum
> ---
> hw/rdma/vmw/pvrdma_main.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdm
From: Suraj Jitindar Singh
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
From: Cédric Le Goater
To ease the introduction of the PSI bridge model for POWER9, abstract
the POWER chip differences in a PnvPsi class model and introduce a
specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
controller is still XICS whereas POWER9 uses the new XIVE model.
Sig
From: Cédric Le Goater
We will use it to get the CPU interrupt presenter in XIVE when the
TIMA is accessed from the indirect page.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-3-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 16
hw/p
From: Alex Bennée
I'm the sole author (aside from a one line by Greg fixing encoding)
and I was asked nicely on IRC to bring it into line with the rest of
the files.
Cc: Greg Kurz
Signed-off-by: Alex Bennée
Signed-off-by: Thomas Huth
---
scripts/qemugdb/timers.py | 6 --
1 file changed,
From: Suraj Jitindar Singh
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch.
From: Mark Cave-Ayland
By using the VsrD macro in avr64_offset() the same offset calculation can be
used regardless of the host endian. This allows get_avr64() and set_avr64() to
be simplified accordingly.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307180520.13868-6-mark.cave-ayl...@ilan
On 3/11/19 12:29 PM, Yuval Shaia wrote:
> Use base object of PCIDevice in call to object_get_typename().
>
> Signed-off-by: Yuval Shaia
> ---
> hw/rdma/vmw/pvrdma_main.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_ma
From: Cédric Le Goater
The POWER9 PowerNV machine will use a XIVE interrupt presenter type.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-6-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 6 +++---
hw/ppc/pnv_core.c | 2 +-
include/hw/ppc/
From: Li Qiang
Spotted by ASAN while running 'make check'.
Fixes: 4b9b7000 ("tests: Add a test for qemu self announcements")
Suggested-by: Thomas Huth
Signed-off-by: Li Qiang
Signed-off-by: Thomas Huth
---
tests/test-announce-self.c | 21 ++---
1 file changed, 6 insertions(+)
From: Cédric Le Goater
The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-6-...@kaod.org>
S
From: Eric Blake
Managing parallel connections to two different monitors via
the implicit global_qtest makes it hard to copy-and-paste code
to tests that are not aware of the implicit state; the
management of global_qtest is even harder to follow because
it was masked behind set_context().
Inste
From: Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability of the large decrementer for a guest.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <20190301024317.22137-1-sjitindarsi...@gmail.com>
[dwg: Trivial style fix]
Signed-off-by: David Gibso
From: Suraj Jitindar Singh
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also n
From: Cédric Le Goater
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake t
Hi Peter,
the following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-03-11 18:26:37 +)
are available in the git repository at:
https://gitlab.com/huth/qemu.git tags/pull-request-2019
From: Cédric Le Goater
The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-4-...@kao
From: David Gibson
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and
hence of type hwaddr which is 64-bit. Previously it wasn't marked as such
which means that it could be treated as 32-bit. That will work in some
circumstances but if multiplied by another 32-bit value
From: Cédric Le Goater
The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.
The mapping addresses of each register range are correct but the si
On 3/11/19 12:29 PM, Yuval Shaia wrote:
> This hook was installed to close the device when VM is going down.
> After the device is closed there is no need to be informed on VM
> shutdown.
>
> Signed-off-by: Yuval Shaia
> Reviewed-by: Marcel Apfelbaum
> ---
> hw/rdma/vmw/pvrdma_main.c | 2 ++
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