Peter Xu writes:
> On Wed, Jul 18, 2018 at 05:38:11PM +0200, Markus Armbruster wrote:
>> Peter Xu writes:
>>
>> > After the Out-Of-Band work, the monitor iothread may be accessing the
>> > cur_mon as well (via monitor_qmp_dispatch_one()). Let's convert the
>> > cur_mon variable to be a per-thr
Prior to the update:
$ virsh domfsfreeze x-freeze; virsh domfsthaw x-freeze
error: Unable to freeze filesystems
error: internal error: unable to execute QEMU agent command
'guest-fsfreeze-freeze': failed to freeze /: Device or resource busy
Thawed 0 filesystem(s)
$ sudo apt install qemu-guest-
On 18.07.2018 23:31, Alistair Francis wrote:
> On Wed, Jul 18, 2018 at 12:22 AM, Thomas Huth wrote:
>> On 17.07.2018 22:27, Alistair Francis wrote:
>>> This is based on Thomas's work fixing introspection problems [1] and
>>> applied to the RISC-V port.
>>>
>>> 1: https://lists.gnu.org/archive/html
On Thu, Jul 19, 2018 at 09:20:34AM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Wed, Jul 18, 2018 at 05:38:11PM +0200, Markus Armbruster wrote:
> >> Peter Xu writes:
> >>
> >> > After the Out-Of-Band work, the monitor iothread may be accessing the
> >> > cur_mon as well (via moni
On 18.07.2018 23:13, Mark Cave-Ayland wrote:
> Hi all,
>
> Following on from a couple of patches I've previously posted to the
> mailing list at
> https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg08836.html I've
> made some good progress with trying to add bootindex support to OpenBIOS
> b
On 19.07.2018 08:42, Markus Armbruster wrote:
> Peter Maydell writes:
>
>> On 17 July 2018 at 20:50, Eduardo Habkost wrote:
>>> I have been looking at patches that touch typedefs.h and
>>> wondering: why do we make typedefs.h necessary at all? Why do we
>>> always add typedefs for every struct
On 19/07/2018 08:42, Markus Armbruster wrote:
> For a different point of view (which I happen to share), see
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst?id=024ddc0ce1049298bd3cae60ae45d9c5f0fb8b9c#n318
I think that does not entir
(updating Marcel's address to his GMail one)
On 07/18/18 23:13, Mark Cave-Ayland wrote:
> Hi all,
>
> Following on from a couple of patches I've previously posted to the
> mailing list at
> https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg08836.html I've
> made some good progress with try
On Thu, 19 Jul 2018 12:49:23 +0800
Peter Xu wrote:
> On Wed, Jul 18, 2018 at 11:36:40AM +0200, Cornelia Huck wrote:
> > On Wed, 18 Jul 2018 14:48:03 +0800
> > Peter Xu wrote:
> > > I totally have no idea on whether people would like to use vfio-pci
> > > and the balloon device at the same time.
On 2018年07月19日 00:32, Michael Roth wrote:
Quoting Jason Wang (2018-05-31 04:46:05)
On 2018年05月31日 15:28, wangyunjian wrote:
From: Yunjian Wang
The memory leak on success to create a tap device. And the nfds and
nvhosts may not be the same and need to be processed separately.
Fixes: 0782597
Peter Xu writes:
> On Thu, Jul 19, 2018 at 09:20:34AM +0200, Markus Armbruster wrote:
>> Peter Xu writes:
>>
>> > On Wed, Jul 18, 2018 at 05:38:11PM +0200, Markus Armbruster wrote:
>> >> Peter Xu writes:
>> >>
>> >> > After the Out-Of-Band work, the monitor iothread may be accessing the
>> >>
Hi, all
I found that qemu has a constraint in function numa_node_parse now:
If (node->has_memdev != have_memdevs) {
Error_setg(errp, "qemu: memdev option must be specified for either "
"all or no nodes");
Return;
}
This restricts us from being able to
From: "Dr. David Alan Gilbert"
We've been getting the warning:
migration_iteration_finish: Unknown ending state 2
on a cancel.
I think that's originally due to 39b9e17905c; although
I've only seen the warning, I think that in some cases
that we could find the VM stays paused after a cancel wh
On Thu, Jul 19, 2018 at 10:42:22AM +0200, Cornelia Huck wrote:
> On Thu, 19 Jul 2018 12:49:23 +0800
> Peter Xu wrote:
>
> > On Wed, Jul 18, 2018 at 11:36:40AM +0200, Cornelia Huck wrote:
> > > On Wed, 18 Jul 2018 14:48:03 +0800
> > > Peter Xu wrote:
>
> > > > I totally have no idea on whether p
On Thu, Jul 19, 2018 at 10:22:57AM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> We've been getting the warning:
>
> migration_iteration_finish: Unknown ending state 2
>
> on a cancel.
>
> I think that's originally due to 39b9e17905c; although
> I've only see
On Thu, Jul 19, 2018 at 11:05:34AM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Thu, Jul 19, 2018 at 09:20:34AM +0200, Markus Armbruster wrote:
> >> Peter Xu writes:
> >>
> >> > On Wed, Jul 18, 2018 at 05:38:11PM +0200, Markus Armbruster wrote:
> >> >> Peter Xu writes:
> >> >>
On 16 July 2018 at 23:23, Guenter Roeck wrote:
> Writes in PIO mode have two requirements:
>
> - A data interrupt must be generated after a write command has been
> issued to indicate that the chip is ready to receive data.
> - A block interrupt must be generated after each block to indicate
>
On 6 July 2018 at 12:54, Peter Maydell wrote:
> On 27 April 2018 at 14:16, Peter Maydell wrote:
>> On 12 March 2018 at 09:14, Gerd Hoffmann wrote:
>>> Add support for cursor dmabufs. qemu has to render the cursor for
>>> that, so in case a cursor is present qemu allocates a new dmabuf, blits
>>
On 17.07.2018 19:00, Juan Quintela wrote:
> Thomas Huth wrote:
>> On 17.07.2018 14:04, Juan Quintela wrote:
>>> Hi
>>>
>>> Notice that this is an RFC because they don't work. As said on my
>>> previous submmision, we need -softmmu/config-devices.h to make
>>> this work. This series just allow us
"Dr. David Alan Gilbert (git)" wrote:
> From: "Dr. David Alan Gilbert"
>
> We've been getting the warning:
>
> migration_iteration_finish: Unknown ending state 2
>
> on a cancel.
>
> I think that's originally due to 39b9e17905c; although
> I've only seen the warning, I think that in some cases
>
On 3 July 2018 at 22:35, Markus Armbruster wrote:
> Commit 71da4667db6 "monitor: separate QMP parser and dispatcher" moved
> the handle_qmp_command tracepoint from handle_qmp_command() to
> monitor_qmp_dispatch_one(). This delays tracing from enqueue time to
> dequeue time. Revert that. Dequeue
On 07/18/2018 03:56 PM, Philippe Mathieu-Daudé wrote:
>> +
>> +/* This syscall implements {get,set,swap}context for userland. */
>
> This comment confuses me because do_setcontext() is available at line 625.
But that's not wired up as a syscall.
>> +/* For ppc32, ctx_size is "reserved for f
The following changes since commit ea6abffa8a08d832feb759d359d5b935e3087cf7:
Update version for v3.0.0-rc1 release (2018-07-17 18:15:19 +0100)
are available in the Git repository at:
git://github.com/cohuck/qemu tags/s390x-20180719
for you to fetch changes up to
From: David Hildenbrand
Usually, when baselining two CPU models, whereby one of them has base
CPU features disabled (e.g. z14-base,msa=off), we fallback to an older
model that did not have these features in the base model. We always try to
create a "sane" CPU model (as far as possible), and one p
On Thu, 19 Jul 2018 13:06:59 +0200
Thomas Huth wrote:
> On 17.07.2018 19:00, Juan Quintela wrote:
> > So far so good, but look at virtio-pci.c:
> >
> > static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
> > {
> >...
> > }
> >
> > static void virtio_rng_pci_class_ini
On 19.07.2018 13:45, Cornelia Huck wrote:
> On Thu, 19 Jul 2018 13:06:59 +0200
> Thomas Huth wrote:
>
>> On 17.07.2018 19:00, Juan Quintela wrote:
>
>>> So far so good, but look at virtio-pci.c:
>>>
>>> static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
>>> {
>>>...
>
On Thu, 19 Jul 2018 13:58:02 +0200
Thomas Huth wrote:
> On 19.07.2018 13:45, Cornelia Huck wrote:
> > On Thu, 19 Jul 2018 13:06:59 +0200
> > Thomas Huth wrote:
> >> I agree with you that the current situation with virtio-pci. c is bad. I
> >> think we should split it up into individual files in
From: Xiao Guangrong
Thanks to Peter's suggestion, i split the long series (1) and this is the
first part.
I am not sure if Dave is happy to @reduced-size, will change immediately
if it's objected. :)
Changelog in v2:
1) introduce a parameter to make the main thread wait for free thread
thre
From: Xiao Guangrong
The compressed page is not normal page
Signed-off-by: Xiao Guangrong
---
migration/ram.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/migration/ram.c b/migration/ram.c
index 0ad234c692..1b016e048d 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -1903,7 +1903,6
Peter Xu writes:
> On Thu, Jul 19, 2018 at 11:05:34AM +0200, Markus Armbruster wrote:
>> Peter Xu writes:
>>
>> > On Thu, Jul 19, 2018 at 09:20:34AM +0200, Markus Armbruster wrote:
>> >> Peter Xu writes:
>> >>
>> >> > On Wed, Jul 18, 2018 at 05:38:11PM +0200, Markus Armbruster wrote:
>> >> >>
From: Xiao Guangrong
Currently, it includes:
pages: amount of pages compressed and transferred to the target VM
busy: amount of count that no free thread to compress data
busy-rate: rate of thread busy
reduced-size: amount of bytes reduced by compression
compression-rate: rate of compressed size
From: Xiao Guangrong
Instead of putting the main thread to sleep state to wait for
free compression thread, we can directly post it out as normal
page that reduces the latency and uses CPUs more efficiently
A parameter, compress-wait-thread, is introduced, it can be
enabled if the user really wa
From: Xiao Guangrong
It will be used by the compression threads
Signed-off-by: Xiao Guangrong
---
migration/ram.c | 40 ++--
1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index e68b0e6dec..ce6e69b649 100644
From: Xiao Guangrong
It is not used and cleans the code up a little
Signed-off-by: Xiao Guangrong
---
migration/ram.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index ce6e69b649..5aa624b3b9 100644
--- a/mig
From: Xiao Guangrong
flush_compressed_data() needs to wait all compression threads to
finish their work, after that all threads are free until the
migration feeds new request to them, reducing its call can improve
the throughput and use CPU resource more effectively
We do not need to flush all t
Peter Maydell writes:
> On 3 July 2018 at 22:35, Markus Armbruster wrote:
>> Commit 71da4667db6 "monitor: separate QMP parser and dispatcher" moved
>> the handle_qmp_command tracepoint from handle_qmp_command() to
>> monitor_qmp_dispatch_one(). This delays tracing from enqueue time to
>> dequeu
From: Xiao Guangrong
Detecting zero page is not a light work, moving it to the thread to
speed the main thread up
Signed-off-by: Xiao Guangrong
---
migration/ram.c | 112 +++-
1 file changed, 78 insertions(+), 34 deletions(-)
diff --git a/mi
From: Xiao Guangrong
Try to hold src_page_req_mutex only if the queue is not
empty
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Xiao Guangrong
---
include/qemu/queue.h | 1 +
migration/ram.c | 4
2 files changed, 5 insertions(+)
diff --git a/include/qemu/queue.h b/include/qem
On Thu, Jul 19, 2018 at 01:48:13AM -0400, Pankaj Gupta wrote:
>
> >
> > > This patch adds virtio-pmem Qemu device.
> > >
> > > This device presents memory address range information to guest
> > > which is backed by file backend type. It acts like persistent
> > > memory device for KVM guest.
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
v2:
* Ad
On 19 July 2018 at 13:22, Markus Armbruster wrote:
> Peter Maydell writes:
>> Coverity CID 1394216 points out that in this function a
>> little earlier we did a check on "if (!req && !err)", which
>> implies that we can get here with a NULL req pointer,
>> which will crash in qobject_to_json().
>
On Thu, 19 Jul 2018 01:48:13 -0400 (EDT)
Pankaj Gupta wrote:
> >
> > > This patch adds virtio-pmem Qemu device.
> > >
> > > This device presents memory address range information to guest
> > > which is backed by file backend type. It acts like persistent
> > > memory device for KVM guest.
On 19 July 2018 at 04:11, Jia He wrote:
> In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu
> output log with:
> if [ -z "$(echo "$errors" | grep -vi warning)" ]; then
>
> Thus without the warning prefix, all of the test fail.
>
> Since it is not unrecoverable error in kvm_arm_its
On Thu, Jul 19, 2018 at 02:14:56PM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Thu, Jul 19, 2018 at 11:05:34AM +0200, Markus Armbruster wrote:
> >> Peter Xu writes:
> >>
> >> > On Thu, Jul 19, 2018 at 09:20:34AM +0200, Markus Armbruster wrote:
> >> >> Peter Xu writes:
> >> >>
Hi!
On 06/28/2018 03:07 AM, Max Reitz wrote:
bdrv_refresh_filename() should invoke itself recursively on all
children, not just on file.
With that change, we can remove the manual invocations in blkverify,
quorum, commit, and mirror.
Signed-off-by: Max Reitz
Reviewed-by: Alberto Garcia
Revie
On Thu, 19 Jul 2018 13:16:35 +0100
Stefan Hajnoczi wrote:
> On Thu, Jul 19, 2018 at 01:48:13AM -0400, Pankaj Gupta wrote:
> >
> > >
> > > > This patch adds virtio-pmem Qemu device.
> > > >
> > > > This device presents memory address range information to guest
> > > > which is backed by
On Thu, 19 Jul 2018 08:48:19 -0400
Luiz Capitulino wrote:
> > It will be necessary to define specific constants for virtio-pmem
> > instead of passing errno from the host to guest.
>
> Yes, defining your own constants work. But I think the only fsync()
> error that will make sense for the gues
On 07/13/2018 12:49 PM, Max Reitz wrote:
Ping – any thoughts on the design, Kevin?
(Continuing to see how much of a mess our backing filename handling is
(half of the time, bs->backing_file is seen as a value in the image
header (so relative paths are interpreted relatively to the overlay),
hal
On Wed, Jul 18, 2018 at 05:08:21PM +0200, Markus Armbruster wrote:
> Marc-André, one question for you inline. Search for your name.
>
> Peter Xu writes:
>
> > On Thu, Jun 28, 2018 at 03:20:41PM +0200, Markus Armbruster wrote:
> >> Peter Xu writes:
> >>
> >> > On Wed, Jun 27, 2018 at 03:13:57P
The instance_init function of the xtensa CPUs creates a memory region,
but does not set an owner, so the memory region is not destroyed
correctly when the CPU object is removed. This can happen when
introspecting the CPU devices, so introspecting the CPU device will
leave a dangling memory region o
Richard Henderson writes:
> This allows the tests generated by debian-powerpc-user-cross
> to function properly, especially tests/test-coroutine.
>
> Technically this syscall is available to both ppc32 and ppc64,
> but only ppc32 glibc actually uses it. Thus the ppc64 path is
> untested.
>
> S
nand_init() does not only create the NAND device, it also realizes
the device with qdev_init_nofail() already. So we must not call
nand_init() from an instance_init function like sl_nand_init(),
otherwise we get superfluous NAND devices in the QOM tree after
introspecting the 'sl-nand' device. So m
From: Aleksandar Markovic
Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/mips-defs.h | 4
1 file changed, 4 insertions(+)
diff --g
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 249 +
From: Yongbok Kim
Config3.ISAOnExc is read only in nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 in
From: Yongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 66 +++
From: Aleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH.
The duplicate was introduced in commit 45506bdd.
Signed-off-by: Aleksandar Markovic
---
include/elf.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 934dbbd..c
From: Aleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and
linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers.
This adds 7 new syscall numbers, the last being NR_statx.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/sysc
From: Aleksandar Markovic
v5->v6:
- patch on updating CP0 register bit definitions expanded to include
Config2, Config3, and Config4 registers
- added 4 patches:
- elf: Remove duplicate preprocessor constant definition
- elf: Add ELF flags for MIPS machine variants
-
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5299f21..9535131 100644
--- a/target/mips/hel
From: Yongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 300
From: Aleksandar Markovic
Add MIPS machine variants ELF flags so that the emulation behavior
can be adjusted if needed.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include/elf.
From: Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 190 +++
From: Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 139
From: Yongbok Kim
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,
LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 114 +
From: Aleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
.mailmap| 7 +--
MAINTAINERS | 9 +
2
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
From: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/strace.c | 14 +-
linux-user/syscall.c | 25 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 157 ++
From: Stefan Markovic
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 144
1 file changed, 144 insertions(+)
diff --git a/targ
From: Aleksandar Markovic
v2->v3:
- added support for nanoMIPS-specifics in ELF headers
- added support for CP0 Config0.WR bit
- updated I7200 definition
- improved indentation of some switch statements
- slight reorganization of patches (splitting, order)
- rebased to the latest cod
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug
From: Yongbok Kim
Add emulation of misc nanoMIPS 16-bit instructions from instruction
pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 258 ++
From: Yongbok Kim
Add emulation of various nanoMIPS load and store instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 271
From: Yongbok Kim
Add some basic utility functions and macros for nanoMIPS decoding
engine.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 35 +++
1 file changed, 35 insertions(+)
dif
From: Yongbok Kim
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in env->insn_flags.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 --
1 file changed,
From: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 1d3dc9e..c9c20cf 100644
--- a/linux-user/mips/cpu_loop
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mi
From: Yongbok Kim
Add emulation of various flavors of nanoMIPS branch instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 277 +++
From: Yongbok Kim
Add emulation of NOT16, AND16, XOR16, OR16 instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 ++
1 file changed, 22 insertions(+)
d
From: Aleksandar Markovic
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 20
1 file changed, 20 insertions(+)
diff --git a/include/elf.
From: Yongbok Kim
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines
gen_save(), gen_restore(), and gen_adjust_sp() are provided for this
purpose.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 73 +
From: Stefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Signed-off-by: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 1 +
ta
From: James Hogan
We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/targ
From: Matthew Fortune
Added very very basic nanoMIPS boot code but this is hacked in
unconditionally currently.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 75 +++-
1 f
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 2072 ++-
1 file changed, 1681 insertions(+), 391 deletions(-)
diff --git a/ta
From: Stefan Markovic
Add emulation of MT ASE instructions for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 85 +++--
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/target/
From: James Hogan
ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
is no ISA bit, so fix set_pc() to skip the hflags update.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar
From: Paul Burton
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar M
From: Yongbok Kim
Fix ERET/ERETNC so that ADEL exception can be raised.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/op_helper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
From: Yongbok Kim
Updating BadInstr and BadInstrP registers was addded for nanoMIPS.
BadInstr and BadInstrP support for pre-nanoMIPS remains
unimplemented.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 23 +
From: Yongbok Kim
Add emulation of misc nanoMIPS instructions situated in pool32axf.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 94 +++
From: Yongbok Kim
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/tra
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index d1a7c1f..8bb1686 100644
--- a
From: Aleksandar Markovic
Starting from nanoMIPS introduction, machine variant can be
EM_MIPS or EM_NANOMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfl
From: Yongbok Kim
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksand
From: Stefan Markovic
Add XML support files for GDB for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
MAINTAINERS| 3 ++-
gdb-xml/nanomips-cp0.xml | 13 +
gdb-xml/nanomips-cpu.xml | 44 +
From: James Hogan
We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
otherwise we'll start interpreting the code as normal MIPS code.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/help
From: Stefan Markovic
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate_init.inc.c | 40
1 file changed, 40 insertions(+)
dif
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