On Tue, Aug 02, 2016 at 11:42:01AM +0200, Luke Gorrie wrote:
> Hi Michael & all,
>
> On 4 August 2015 at 21:00, Luke Gorrie wrote:
>
> Hi Michael,
>
> Sorry I didn't see this mail sooner -
>
> On 30 July 2015 at 10:36, Michael S. Tsirkin wrote:
>
> This reverts commit 294
The exact same routine will be used in PowerNV.
Signed-off-by: Cédric Le Goater
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/fdt.c | 49 +
hw/ppc/spapr.c | 36 +---
include/hw/ppc/fdt.h | 5 +
4 files
From: Sergey Fedorov
Move the code common between run_on_cpu() and async_run_on_cpu() into a
new function queue_work_on_cpu().
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
---
cpus.c | 42 ++--
From: Sergey Fedorov
Convert pthread_mutex_t and pthread_cond_t to QemuMutex and QemuCond.
This will allow to make some locks and conditional variables common
between user and system mode emulation.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-of
On Tue, Aug 02, 2016 at 08:32:32AM +0200, Juergen Gross wrote:
> Instead of calling xen_be_register() for each supported backend type
> for hvm and pv guests in their machine init functions use a common
> function in order not to have to add new backends twice.
>
> This at once fixes the error tha
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
---
linux-user/main.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 60ca69f..f5ddf96 100644
--- a
From: Sergey Fedorov
It is a minimalistic support because bsd-linux claims to be _not_
threadsafe.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Alex Bennée
---
bsd-user/main.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/bsd-user/main.c b
From: Sergey Fedorov
Make CPU work core functions common between system and user-mode
emulation. User-mode does not have BQL, so process_queued_cpu_work() is
protected by 'exclusive_lock'.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex
Under times of high memory stress the additional small mallocs by a
linked list are source of potential memory fragmentation. As we have
worked hard to avoid mallocs elsewhere when queuing work we might as
well do the same for the list. We convert the lists to a auto-resizeing
GArray which will re-
We currently make no checks on the flags passed to the clone syscall,
which means we will not fail clone attempts which ask for features
that we can't implement. Add sanity checking of the flags to clone
(which we were already doing in the "this is a fork" path, but not
for the "this is a new threa
Hello,
Here are a couple of enhancements for sPAPR but PowerNV should use
them also.
Thanks,
C.
Cédric Le Goater (2):
hw/ppc: use error_report instead of fprintf
hw/ppc: add a ppc_create_page_sizes_prop() helper routine
hw/ppc/Makefile.objs | 2 +-
hw/ppc/fdt.c | 49
This patchset adds checks on the flags passed to the clone syscall.
Previously we weren't checking the flags at all for the clone case,
which meant that some tests in the LTP testsuite would behave bizarrely
because we let the clone syscall succeed but didn't provide the
semantics requested by the
The 'nptl_flags' variable in do_fork() is set to a copy of
'flags', and then the CLONE_NPTL_FLAGS are cleared out of 'flags'.
However the only effect of this is that the later check on
"if (flags & CLONE_PARENT_SETTID)" is never true. Since we
will already have done the setting of parent_tidptr in
Under times of high memory stress the additional small mallocs by a
linked list are source of potential memory fragmentation. As we have
worked hard to avoid mallocs elsewhere when queuing work we might as
well do the same for the list. We convert the lists to a auto-resizeing
GArray which will re-
On Tue, Jul 19, 2016 at 12:07:53PM +0200, Igor Mammedov wrote:
> On Tue, 19 Jul 2016 10:28:35 +0200
> Greg Kurz wrote:
>
> > Commit 2aece63 "hostmem: detect host backend memory is being used properly"
> > added a way to know if a memory backend is busy or available for use. It
> > caused a slight
From: Pavel Fedin
Linux header update for in-kernel ITS emulation and KVM MSI routing.
The kernel can be found at
https://github.com/eauger/linux/tree/v4.7-rc6-its-emul-v7-gsi-routing-v5
Signed-off-by: Pavel Fedin
Signed-off-by: Eric Auger
---
v4 -> v5:
- upgrade
---
include/standard-heade
From: Pavel Fedin
This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.
Signed-off-by: Pavel Fedin
This series introduces support for in-kernel GICv3 ITS emulation.
It is based on a kernel API which is not yet released.
Tested on Cavium ThunderX with virtio-net-pci and vhost-net with both dt
and ACPI guests
Host Kernel dependencies:
- [PATCH v10 00/17] KVM: arm64: GICv3 ITS emulation
http://
Alex Bennée writes:
> Under times of high memory stress the additional small mallocs by a
> linked list are source of potential memory fragmentation. As we have
> worked hard to avoid mallocs elsewhere when queuing work we might as
> well do the same for the list. We convert the lists to a auto-
From: Pavel Fedin
The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
differen
From: Pavel Fedin
Introduce global kvm_arm_msi_use_devid flag and pass device IDs in
kvm_arch_fixup_msi_route(). Device IDs are required by the ITS.
Signed-off-by: Pavel Fedin
Signed-off-by: Eric Auger
---
v3 -> v4:
- OR route->flags with KVM_MSI_VALID_DEVID
---
target-arm/kvm.c | 6 +++
Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.
Signed-off-by: Eric Auger
Suggested-by: Peter Maydell
---
v4 -> v5:
- add #include "qemu/error-report.h"
- rebased on target-arm: Fix unreachable code in gicv3_class_name()
v4: creation
Conflicts:
From: Pavel Fedin
If supported by the configuration, ITS will be added automatically.
This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.
Signed-off-by: Pavel Fedin
Signed-off-by: Eric Auger
Reviewed-by: Peter Maydell
--
v3 -> v4:
- added P
On Tue, Aug 02, 2016 at 04:10:39PM +0800, Luwei Kang wrote:
> Add more AVX512 feature bits, include AVX512DQ, AVX512IFMA,
> AVX512BW, AVX512VL, AVX512VBMI. Its spec can be found at:
> https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
>
> Signed-off-by: Luwei Kang
As we'
This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
is added to the MADT table.
Signed-off-by: Eric Auger
---
v5: new
Tested with Tomasz' kernel series on guest side:
- [PATCH V7 0/8] Introduce ACPI world to ITS,
https://lkml.org/lkml/2016/6/20/321
- for running PCIe on the
> On Tue, Aug 02, 2016 at 01:58:46PM +0200, David Hildenbrand wrote:
> [...]
> > So we have:
> > a) "query-cpu-model-expansion" - tell us what the "host" or another CPU
> >model looks like. Either falling back to a static model or
> >completely exposing all properties.
>
> The query-cpu-
On Tue, 2 Aug 2016, Juergen Gross wrote:
> Instead of calling xen_be_register() for each supported backend type
> for hvm and pv guests in their machine init functions use a common
> function in order not to have to add new backends twice.
>
> This at once fixes the error that hvm domains couldn't
On Tue, 2 Aug 2016, Gerd Hoffmann wrote:
> On Di, 2016-08-02 at 08:32 +0200, Juergen Gross wrote:
> > Instead of calling xen_be_register() for each supported backend type
> > for hvm and pv guests in their machine init functions use a common
> > function in order not to have to add new backends twi
* Daniel P. Berrange (berra...@redhat.com) wrote:
> On Tue, Aug 02, 2016 at 04:06:42PM +0100, Paul Durrant wrote:
> > This patch adds a tracing backend which sends output using syslog().
> > The syslog backend is limited to POSIX compliant systems.
> >
> > openlog() is called with facility set to
On Tue, Aug 02, 2016 at 18:27:44 +0100, Alex Bennée wrote:
> Under times of high memory stress the additional small mallocs by a
> linked list are source of potential memory fragmentation. As we have
> worked hard to avoid mallocs elsewhere when queuing work we might as
> well do the same for the l
Followup to 87ac25fd, this time for ATAPI DMA.
Reported-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/atapi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index 95056d9..6189675 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -386,6 +386,7 @@ s
On 19/07/2016 16:31, Fam Zheng wrote:
> Image building targets are dependencies of test running targets, so when
> a docker image doesn't exist, it means it's skipped (due to dependency
> checks in pre script). Therefore, skip the test too.
>
> Signed-off-by: Fam Zheng
> Message-id: 1468934445-
- Original Message -
> From: "Eduardo Habkost"
> To: "Igor Mammedov"
> Cc: "Greg Kurz" , "Thomas Huth" ,
> qemu-devel@nongnu.org, pbonz...@redhat.com
> Sent: Tuesday, August 2, 2016 8:00:06 PM
> Subject: Re: [Qemu-devel] [PATCH] numa: set the memory backend "is_mapped"
> field
>
> On
On Tue, Aug 02, 2016 at 18:27:42 +0100, Alex Bennée wrote:
> From: Sergey Fedorov
>
> This patch is based on the ideas found in work of KONRAD Frederic [1],
> Alex Bennée [2], and Alvise Rigo [3].
>
> This mechanism allows to perform an operation safely in a quiescent
> state. Quiescent state me
It is naturally expected that some memory ordering should be provided
around qht_insert() and qht_lookup(). Document these assumptions in the
header file and put some comments in the source to denote how that
memory ordering requirements are fulfilled.
Signed-off-by: Paolo Bonzini
[Sergey Fedorov
From: Greg Kurz
Commit 2aece63 "hostmem: detect host backend memory is being used properly"
added a way to know if a memory backend is busy or available for use. It
caused a slight regression if we pass the same backend to a NUMA node and
to a pc-dimm device:
-m 1G,slots=2,maxmem=2G \
-object me
From: Igor Mammedov
When adding hostmem backend at runtime, QEMU might exit with error:
"os_mem_prealloc: Insufficient free host memory pages available to allocate
guest RAM"
It happens due to os_mem_prealloc() not handling errors gracefully.
Fix it by passing errp argument so that os_mem_pr
From: Cao jin
It is never used; all nonblocking connect now goes through
socket_connect(), which calls inet_connect_addr().
Cc: Daniel P. Berrange
Cc: Gerd Hoffmann
Cc: Paolo Bonzini
Signed-off-by: Cao jin
Message-Id: <1469097213-26441-2-git-send-email-caoj.f...@cn.fujitsu.com>
Signed-off-by
From: Dave Hansen
QEMU 2.6 added support for the XSAVE family of instructions, which
includes the XSETBV instruction which allows setting the XCR0
register.
But, when booting Linux kernels with XSAVE support enabled, I was
getting very early crashes where the instruction pointer was set
to 0x3.
The following changes since commit cc0100f464c94bf80ad36cd432f4a1ed58126b60:
MAINTAINERS: Update the Xilinx maintainers (2016-08-01 15:31:32 +0100)
are available in the git repository at:
git://github.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 3531bd22792beae5eba1
Tested-By: Peter Xu
Signed-off-by: Paolo Bonzini
---
scripts/checkpatch.pl | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index afa7f79..b7cb4ab 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2544,7 +2544,
From: Eric Blake
Make it obvious which macros are safe in which situations.
Useful since QEMU_ALIGN_UP and ROUND_UP both purport to do
the same thing, but differ on whether the alignment must be
a power of 2.
Signed-off-by: Eric Blake
Message-Id: <1469129688-22848-4-git-send-email-ebl...@redha
From: "Emilio G. Cota"
So far, QHT functions assume that the passed qht has previously been
initialized--otherwise they segfault.
This patch makes an exception for qht_statistics_init, with the goal
of simplifying calling code. For instance, qht_statistics_init is
called from the 'info jit' dump
From: "Emilio G. Cota"
In qdist_bin__internal(), to->entries is initialized to a 1-element array,
which we then leak when n == from->n. Fix it.
Signed-off-by: Emilio G. Cota
Message-Id: <1469459025-23606-2-git-send-email-c...@braap.org>
Signed-off-by: Paolo Bonzini
---
util/qdist.c | 2 +-
1
From: Cao jin
It is never used; all nonblocking connect now goes through
socket_connect(), which calls unix_connect_addr().
Cc: Daniel P. Berrange
Cc: Gerd Hoffmann
Cc: Paolo Bonzini
Signed-off-by: Cao jin
Message-Id: <1469097213-26441-3-git-send-email-caoj.f...@cn.fujitsu.com>
Signed-off-by
From: Cao jin
Since commit e65c67e4, inet_listen() is not used anymore, and all
inet listen operation goes through QIOChannel.
Cc: Daniel P. Berrange
Cc: Gerd Hoffmann
Cc: Paolo Bonzini
Cc: Eric Blake
Signed-off-by: Cao jin
Message-Id: <1469451771-1173-3-git-send-email-caoj.f...@cn.fujitsu
From: Igor Mammedov
commit f6e98444 (apic: Use apic_id as apic's migration instance_id)
breaks migration when in kernel irqchip is used for 2.6 and older
machine types.
It applies compat property only for userspace 'apic' type
instead of applying it to all apic types inherited from
'apic-common'
From: "Emilio G. Cota"
While at it, remove the unnecessary parentheses around dist->size.
Signed-off-by: Emilio G. Cota
Message-Id: <1469459025-23606-3-git-send-email-c...@braap.org>
Signed-off-by: Paolo Bonzini
---
util/qdist.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Commit 2e2aa316 removed internal flag msi_in_use, but it
existed in vmstate. Restore it for migration to older QEMU
versions.
Reported-by: Amit Shah
Suggested-by: Amit Shah
Cc: Markus Armbruster
Cc: Marcel Apfelbaum
Cc: Paolo Bonzini
Cc: Michael S. Tsirkin
Cc: Amit Shah
Cc: Cao jin
Signed
From: Igor Mammedov
QEMU fails migration with following error:
qemu-system-x86_64: Missing section footer for i2c_bus
qemu-system-x86_64: load of migration failed: Invalid argument
when migrating from:
qemu-system-x86_64-v2.6.0 -m 256M rhel72.img -M pc-i440fx-2.6
to
qemu-system-x86_64-v2.7.
From: "Emilio G. Cota"
Printf'ing a NULL string is undefined behaviour. Avoid it.
Reported-by: Peter Maydell
Signed-off-by: Emilio G. Cota
Message-Id: <1469459025-23606-4-git-send-email-c...@braap.org>
Signed-off-by: Paolo Bonzini
---
tests/test-qdist.c | 10 --
util/qdist.c |
From: Eric Blake
Commit ab7c548e added a check for invalid flags, but used an
early return on error instead of properly going through the
cleanup label.
Signed-off-by: Eric Blake
Message-Id: <1469129688-22848-2-git-send-email-ebl...@redhat.com>
Signed-off-by: Paolo Bonzini
---
nbd/server.c |
From: Eric Blake
Rather than asserting that nbdflags is within range, just give
it the correct type to begin with :) nbdflags corresponds to
the per-export portion of NBD Protocol "transmission flags", which
is 16 bits in response to NBD_OPT_EXPORT_NAME and NBD_OPT_GO.
Furthermore, upstream NBD
From: Eric Blake
Dell Equallogic iSCSI SANs have a very unusual advertised geometry:
$ iscsi-inq -e 1 -c $((0xb0)) iscsi://XXX/0
wsnz:0
maximum compare and write length:1
optimal transfer length granularity:0
maximum transfer length:0
optimal transfer length:0
maximum prefetch xdread xdwrite tra
From: Peter Xu
Some old Linux kernels (upstream before v4.0), or any released RHEL
kernels has problem in sending APIC EOI when IR is enabled. Meanwhile,
many of them only support explicit EOI for IOAPIC, which is only
introduced in IOAPIC version 0x20. This patch provide a way to boost
QEMU IOAP
From: Markus Armbruster
Missed when commit 5712db6 split off "fw_cfg_io" and "fw_cfg_mem".
Signed-off-by: Markus Armbruster
Message-Id: <1469777353-9383-1-git-send-email-arm...@redhat.com>
Reviewed-by: Laszlo Ersek
Signed-off-by: Paolo Bonzini
---
hw/nvram/fw_cfg.c | 1 +
1 file changed, 1 i
From: Robert Ho
The '-display' help information is not very correct. This patch sort
it a little.
Also, in its help information, reveals what implicit display option
will be chosen if no definition.
Signed-off-by: Robert Ho
Message-Id: <1469528231-26206-1-git-send-email-robert...@intel.com>
Rev
From: Peter Xu
For level triggered interrupts, we will get Remote IRR bit cleared after
guest kernel finished processing specific request. Before that, we
should ignore the same interrupt from triggering again.
Signed-off-by: Peter Xu
Message-Id: <1469974685-4144-1-git-send-email-pet...@redhat.
On Tue, Aug 02, 2016 at 03:20:41PM -0400, Paolo Bonzini wrote:
[...]
> > I have just noticed that this fell through the cracks, sorry.
> > Applied to numa-next. Thanks!
>
> Actually I am just finishing tests of a pull request that included it
> (because I was the one that caused the regression).
From: Shmulik Ladkani
In cases where iov_copy() is passed with zero 'bytes' argument and a
non-zero 'offset' argument, nothing gets copied - as expected.
However no copy iterations are performed, so 'offset' is left
unaltered, leading to the final assert(offset == 0) to fail.
Instead, change th
From: Fam Zheng
Since 69382d8b (qdev: Fix object reference leak in case device.realize()
fails), object_property_set_bool could release the object. The error
path wants the type name, so hold an reference before realizing it.
Cc: Igor Mammedov
Signed-off-by: Fam Zheng
Message-Id: <1470109301-1
- Original Message -
> From: "Fam Zheng"
> To: qemu-devel@nongnu.org
> Cc: f...@redhat.com, berra...@redhat.com, pbonz...@redhat.com,
> kw...@redhat.com, mre...@redhat.com,
> mdr...@linux.vnet.ibm.com, arm...@redhat.com, s...@weilnetz.de,
> qemu-bl...@nongnu.org
> Sent: Tuesday, August
On Tue, Aug 02, 2016 at 08:12:34PM +0200, David Hildenbrand wrote:
> > On Tue, Aug 02, 2016 at 01:58:46PM +0200, David Hildenbrand wrote:
> > [...]
> > > So we have:
> > > a) "query-cpu-model-expansion" - tell us what the "host" or another CPU
> > >model looks like. Either falling back to a sta
> > > This works too.
> > >
> > > You may also want to copy if(!kvm_gsi_routing_enabled()) from
> > > kvm_irqchip_add_msi_route() to align API (not needed in my case though).
> > > Or
> > > just check the result of these checks by if(!s->irq_routes) :)
> > > Thanks.
> >
> > Right. Do you like to
- Original Message -
Am 02.08.2016 um 08:52 hat Stefan Weil geschrieben:
Am 02.08.2016 um 08:11 schrieb Stefan Weil:
> Public bug reported:
>
> The QEMU PC emulation of DMA does not behave like real hardware or other
> virtualization software.
>
> >From the original bug report (Benjamin
Hi all,
This took a lot of fiddling, so I figured I'd document my findings
here in case it helps anybody else. If you don't want to have
CONFIG_ACPI in your kernel, but still would like to shutdown QEMU, the
following works for the q35 machine type:
ioperm(0x604, 2, 1);
outw(1 << 13, 0x60
** Description changed:
- Starting with a raw disk image, using "qemu-img convert" to convert from
- raw to VHD results in the output VHD file's virtual size being aligned
- to the nearest 516096 bytes (16 heads x 63 sectors per head x 512 bytes
- per sector), instead of preserving the input file'
Hi
On Tue, Aug 2, 2016 at 11:53 PM Paolo Bonzini wrote:
> From: "Emilio G. Cota"
>
> In qdist_bin__internal(), to->entries is initialized to a 1-element array,
> which we then leak when n == from->n. Fix it.
>
> Signed-off-by: Emilio G. Cota
> Message-Id: <1469459025-23606-2-git-send-email-c..
On Fri, Jul 29, 2016 at 10:42 AM, Peter Maydell
wrote:
> On 14 July 2016 at 01:03, Alistair Francis
> wrote:
>> Add a new function load_image_targphys_as() that allows the caller
>> to specify an AddressSpace to use when loading a targphys. The
>> original load_image_targphys() function doesn't
ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA command protocol."
One of the interesting tidbits here is that when a device transitions
from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer S
On 08/02/2016 01:22 PM, Kevin Wolf wrote:
Commit 0d978913 changed blockdev-backup to accept arbitrary node names
instead of device names (i.e. root nodes) for the backup target.
However, it forgot to make the same change in transactions and to update
http://i.imgur.com/PfBxuOb.gif
the docum
On Fri, Jul 29, 2016 at 8:56 AM, Peter Maydell wrote:
> On 14 July 2016 at 01:03, Alistair Francis
> wrote:
>> When loading ROMs allow the caller to specify an AddressSpace to use for
>> the load.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> V9:
>> - Fixup the ROM ordering
>> - Don't allow
On Tue, Aug 02, 2016 at 07:22:43PM +1000, Benjamin Herrenschmidt wrote:
> The current mapping, while correct for the base ports (which is all the
> driver uses these days), is wrong for the extended registers.
>
> I suspect the bugs come from incorrect tables in the CHRP IO Ref document,
> I have
On Tue, Aug 02, 2016 at 07:37:59PM +0200, Cédric Le Goater wrote:
> Hello,
>
> Here are a couple of enhancements for sPAPR but PowerNV should use
> them also.
Applied to ppc-for-2.8, thanks.
>
> Thanks,
>
> C.
>
> Cédric Le Goater (2):
> hw/ppc: use error_report instead of fprintf
> hw/p
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> Let's prepare for new Aspeed SoCs and rename the ast2400 file to a
> more generic one. There are no changes in the code apart from the
> header file include.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
> hw
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> This is a name replacement to prepare ground for other SoCs.
>
> Let's also remove the AST2400_SMC_BASE definition from the address
> space mappings, as it is not used. This controller was removed from
> the Aspeed SoC AST2500, so this p
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> Let's define an object class for each Aspeed SoC we support. A
> AspeedSoCInfo struct gathers the SoC specifications which can later
> be
> used by an instance of the class or by a board using the SoC.
>
> Signed-off-by: Cédric Le Goater
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> We plan to add more Aspeed boards to this file. There are no changes
> in the code.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
> hw/arm/Makefile.objs | 2 +-
> hw/arm/aspeed.c | 106
> +++
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> This is mostly a name replacement to prepare ground for other SoCs
> specificities. It also adds a TypeInfo struct for the palmetto-bmc
> board with a custom initialization for the same reason.
>
> Signed-off-by: Cédric Le Goater
Revie
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> aspeed_board_init() now uses a board identifier to customize some values
> specific to the board.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
>
> Changes since v2:
>
> - removed silicon-rev and cpu-model
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> This gives some explanation behind the magic number 0x120CE416.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
>
> Changes since v2:
>
> - more precise definitions of the hw-strap1 register
> - moved hw-st
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> Based on previous work done by Andrew Jeffery .
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
>
> Changes since v2:
>
> - more precise definitions of the hw-strap1 register
>
> hw/arm/aspeed_soc.c
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> The ast2500 eval board has a hardware strapping register value of
> 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1
> below.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
>
> Changes since
On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
> ---
> hw/arm/aspeed.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index e71500c64bd3..6d7b70df70da 100644
> --- a/hw/arm/a
On Tue, 08/02 13:00, Paolo Bonzini wrote:
>
> > I'd prefer if Paolo's remark (about blk_drain()'s ability to produce
> > more failed requests, stashed in s->rq) were captured in either the
> > commit message, or in a code comment. Something like:
> >
> > /* We drop queued requests after blk_dra
Hi Eric,
On 2016/8/3 2:07, Eric Auger wrote:
> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
> is added to the MADT table.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v5: new
>
> Tested with Tomasz' kernel series on guest side:
> - [PATCH V7 0/8] Introduce ACPI world to
On 2016年08月02日 14:37, Cornelia Huck wrote:
On Tue, 2 Aug 2016 10:39:22 +0800
Jason Wang wrote:
On 2016年08月02日 02:00, Cornelia Huck wrote:
On Mon, 1 Aug 2016 16:07:58 +0800
Jason Wang wrote:
+if (k->query_guest_notifiers &&
+k->query_guest_notifiers(qbus->parent) &&
+v
On Tue, Aug 02, 2016 at 01:22:59PM +0530, Nikunj A Dadhania wrote:
> Reported-by: Anton Blanchard
> Signed-off-by: Nikunj A Dadhania
> ---
>
> Can be squashed with the original commit
Done.
>
> target-ppc/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/t
On Tue, Aug 02, 2016 at 08:24:13AM +0200, Peter Krempa wrote:
> On Tue, Aug 02, 2016 at 16:20:50 +1000, David Gibson wrote:
> > On Tue, Aug 02, 2016 at 10:34:34AM +0530, Bharata B Rao wrote:
> > > On Tue, Aug 02, 2016 at 02:25:08PM +1000, David Gibson wrote:
> > > > On Power, support for vCPU hotpl
On Mon, Aug 01, 2016 at 12:49:38PM +0530, Rajalakshmi Srinivasaraghavan wrote:
> The following vector insert instructions are added from ISA 3.0.
>
> vinsertb - Vector Insert Byte
> vinserth - Vector Insert Halfword
> vinsertw - Vector Insert Word
> vinsertd - Vector Insert Doubleword
>
> Signed-
On Tue, Aug 02, 2016 at 01:23:00PM +0530, Nikunj A Dadhania wrote:
> Missed the following bit in the instruction coding.
>
> src1 ← EXTZ(RA(56:63))
>
> Reported-by: Anton Blanchard
> Signed-off-by: Nikunj A Dadhania
> ---
>
> Can be squashed with the original commit
Done.
>
> target-ppc/tr
On Tue, 08/02 15:45, Paolo Bonzini wrote:
>
>
> - Original Message -
> > From: "Fam Zheng"
> > To: qemu-devel@nongnu.org
> > Cc: f...@redhat.com, berra...@redhat.com, pbonz...@redhat.com,
> > kw...@redhat.com, mre...@redhat.com,
> > mdr...@linux.vnet.ibm.com, arm...@redhat.com, s...@wei
On Tue, 08/02 20:59, Paolo Bonzini wrote:
>
>
> On 19/07/2016 16:31, Fam Zheng wrote:
> > Image building targets are dependencies of test running targets, so when
> > a docker image doesn't exist, it means it's skipped (due to dependency
> > checks in pre script). Therefore, skip the test too.
>
On 08/02/2016 02:26 PM, Jason Wang wrote:
On 2016年07月26日 09:49, Zhang Chen wrote:
This a COLO net ascii figure:
Primary qemu Secondary qemu
+--+
++
| +-
On Tue, Aug 02, 2016 at 03:48:23PM -0400, Paolo Bonzini wrote:
> > > > This works too.
> > > >
> > > > You may also want to copy if(!kvm_gsi_routing_enabled()) from
> > > > kvm_irqchip_add_msi_route() to align API (not needed in my case though).
> > > > Or
> > > > just check the result of these ch
Reported from Alexey Kardashevskiy:
3f1fea0fb5bf "kvm-irqchip: do explicit commit when update irq" produces
a crash on pseries guest running with VFIO on POWER8 machine as it does
not support KVM_CAP_IRQCHIP (KVM_CAP_IRQ_XICS is there instead). At the
result, KVMState::irq_routes is NULL when VFIO
Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
hw/arm/stm32f205_soc.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff
If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
V3:
- Use OR instead of + for masking
- Improve clarity of print statement
V2:
- Fix up if statement braces
- Remove stm32f2xx_tim
This patchset continues with the Netduino 2 and STM32F205 SoC
work.
This patch series makes a small change to the STM32F2xx
SoC to tidy up the code.
Next a feature is added to the STM32F2xx timer to display the
PWM duty cycle, when debugging is enabled.
Then the STM32F2xx SPI and ADC devices are
Add the STM32F2xx SPI device.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
V4:
- Add VMState
- Small fixes
V2:
- Address Peter C's comments
default-configs/arm-softmmu.mak | 1 +
hw/ssi/Makefile.objs| 1 +
hw/ssi/stm32f2xx_spi.c | 225 +
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