On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > This is a name replacement to prepare ground for other SoCs. > > Let's also remove the AST2400_SMC_BASE definition from the address > space mappings, as it is not used. This controller was removed from > the Aspeed SoC AST2500, so this provides us a better common base for > the address space mapping on both SoCs. > > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Reviewed-by: Andrew Jeffery <and...@aj.id.au>
> ---
> hw/arm/aspeed_soc.c | 95 ++++++++++++++++++++++-------------
> ----------
> hw/arm/palmetto-bmc.c | 4 +-
> include/hw/arm/aspeed_soc.h | 16 ++++----
> 3 files changed, 57 insertions(+), 58 deletions(-)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index b272f4e48cfc..1bec478fef68 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -1,5 +1,5 @@
> /*
> - * AST2400 SoC
> + * ASPEED SoC family
> *
> * Andrew Jeffery <and...@aj.id.au>
> * Jeremy Kerr <j...@ozlabs.org>
> @@ -20,20 +20,19 @@
> #include "qemu/log.h"
> #include "hw/i2c/aspeed_i2c.h"
>
> -#define AST2400_UART_5_BASE 0x00184000
> -#define AST2400_IOMEM_SIZE 0x00200000
> -#define AST2400_IOMEM_BASE 0x1E600000
> -#define AST2400_SMC_BASE AST2400_IOMEM_BASE /* Legacy SMC */
> -#define AST2400_FMC_BASE 0X1E620000
> -#define AST2400_SPI_BASE 0X1E630000
> -#define AST2400_VIC_BASE 0x1E6C0000
> -#define AST2400_SDMC_BASE 0x1E6E0000
> -#define AST2400_SCU_BASE 0x1E6E2000
> -#define AST2400_TIMER_BASE 0x1E782000
> -#define AST2400_I2C_BASE 0x1E78A000
> -
> -#define AST2400_FMC_FLASH_BASE 0x20000000
> -#define AST2400_SPI_FLASH_BASE 0x30000000
> +#define ASPEED_SOC_UART_5_BASE 0x00184000
> +#define ASPEED_SOC_IOMEM_SIZE 0x00200000
> +#define ASPEED_SOC_IOMEM_BASE 0x1E600000
> +#define ASPEED_SOC_FMC_BASE 0x1E620000
> +#define ASPEED_SOC_SPI_BASE 0x1E630000
> +#define ASPEED_SOC_VIC_BASE 0x1E6C0000
> +#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
> +#define ASPEED_SOC_SCU_BASE 0x1E6E2000
> +#define ASPEED_SOC_TIMER_BASE 0x1E782000
> +#define ASPEED_SOC_I2C_BASE 0x1E78A000
> +
> +#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
> +#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
>
> static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
> static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
> @@ -43,29 +42,29 @@ static const int timer_irqs[] = { 16, 17, 18, 35,
> 36, 37, 38, 39, };
> * handled by a device mapping.
> */
>
> -static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned
> size)
> +static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned
> size)
> {
> qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
> __func__, offset, size);
> return 0;
> }
>
> -static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t
> value,
> +static void aspeed_soc_io_write(void *opaque, hwaddr offset,
> uint64_t value,
> unsigned size)
> {
> qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64
> " [%u]\n",
> __func__, offset, value, size);
> }
>
> -static const MemoryRegionOps ast2400_io_ops = {
> - .read = ast2400_io_read,
> - .write = ast2400_io_write,
> +static const MemoryRegionOps aspeed_soc_io_ops = {
> + .read = aspeed_soc_io_read,
> + .write = aspeed_soc_io_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> -static void ast2400_init(Object *obj)
> +static void aspeed_soc_init(Object *obj)
> {
> - AST2400State *s = AST2400(obj);
> + AspeedSoCState *s = ASPEED_SOC(obj);
>
> s->cpu = cpu_arm_init("arm926");
>
> @@ -106,17 +105,17 @@ static void ast2400_init(Object *obj)
> AST2400_A0_SILICON_REV);
> }
>
> -static void ast2400_realize(DeviceState *dev, Error **errp)
> +static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> {
> int i;
> - AST2400State *s = AST2400(dev);
> + AspeedSoCState *s = ASPEED_SOC(dev);
> Error *err = NULL, *local_err = NULL;
>
> /* IO space */
> - memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
> - "ast2400.io", AST2400_IOMEM_SIZE);
> - memory_region_add_subregion_overlap(get_system_memory(),
> AST2400_IOMEM_BASE,
> - &s->iomem, -1);
> + memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
> + "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
> + memory_region_add_subregion_overlap(get_system_memory(),
> + ASPEED_SOC_IOMEM_BASE, &s-
> >iomem, -1);
>
> /* VIC */
> object_property_set_bool(OBJECT(&s->vic), true, "realized",
> &err);
> @@ -124,7 +123,7 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0,
> ASPEED_SOC_VIC_BASE);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
> qdev_get_gpio_in(DEVICE(s->cpu),
> ARM_CPU_IRQ));
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
> @@ -136,7 +135,7 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
> AST2400_TIMER_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
> ASPEED_SOC_TIMER_BASE);
> for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
> qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic),
> timer_irqs[i]);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
> @@ -148,12 +147,12 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0,
> ASPEED_SOC_SCU_BASE);
>
> /* UART - attach an 8250 to the IO space as our UART5 */
> if (serial_hds[0]) {
> qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic),
> uart_irqs[4]);
> - serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
> + serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
> uart5, 38400, serial_hds[0],
> DEVICE_LITTLE_ENDIAN);
> }
>
> @@ -163,7 +162,7 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0,
> ASPEED_SOC_I2C_BASE);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
> qdev_get_gpio_in(DEVICE(&s->vic), 12));
>
> @@ -175,8 +174,8 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, AST2400_FMC_BASE);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1,
> AST2400_FMC_FLASH_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0,
> ASPEED_SOC_FMC_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1,
> ASPEED_SOC_FMC_FLASH_BASE);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,
> qdev_get_gpio_in(DEVICE(&s->vic), 19));
>
> @@ -188,8 +187,8 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
> AST2400_SPI_FLASH_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0,
> ASPEED_SOC_SPI_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
> ASPEED_SOC_SPI_FLASH_BASE);
>
> /* SDMC - SDRAM Memory Controller */
> object_property_set_bool(OBJECT(&s->sdmc), true, "realized",
> &err);
> @@ -197,14 +196,14 @@ static void ast2400_realize(DeviceState *dev,
> Error **errp)
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, AST2400_SDMC_BASE);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0,
> ASPEED_SOC_SDMC_BASE);
> }
>
> -static void ast2400_class_init(ObjectClass *oc, void *data)
> +static void aspeed_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = ast2400_realize;
> + dc->realize = aspeed_soc_realize;
>
> /*
> * Reason: creates an ARM CPU, thus use after free(), see
> @@ -213,17 +212,17 @@ static void ast2400_class_init(ObjectClass *oc,
> void *data)
> dc->cannot_destroy_with_object_finalize_yet = true;
> }
>
> -static const TypeInfo ast2400_type_info = {
> - .name = TYPE_AST2400,
> +static const TypeInfo aspeed_soc_type_info = {
> + .name = TYPE_ASPEED_SOC,
> .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(AST2400State),
> - .instance_init = ast2400_init,
> - .class_init = ast2400_class_init,
> + .instance_size = sizeof(AspeedSoCState),
> + .instance_init = aspeed_soc_init,
> + .class_init = aspeed_soc_class_init,
> };
>
> -static void ast2400_register_types(void)
> +static void aspeed_soc_register_types(void)
> {
> - type_register_static(&ast2400_type_info);
> + type_register_static(&aspeed_soc_type_info);
> }
>
> -type_init(ast2400_register_types)
> +type_init(aspeed_soc_register_types)
> diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
> index 67676a8a8042..4d11905cfb18 100644
> --- a/hw/arm/palmetto-bmc.c
> +++ b/hw/arm/palmetto-bmc.c
> @@ -28,7 +28,7 @@ static struct arm_boot_info palmetto_bmc_binfo = {
> };
>
> typedef struct PalmettoBMCState {
> - AST2400State soc;
> + AspeedSoCState soc;
> MemoryRegion ram;
> } PalmettoBMCState;
>
> @@ -63,7 +63,7 @@ static void palmetto_bmc_init(MachineState
> *machine)
> PalmettoBMCState *bmc;
>
> bmc = g_new0(PalmettoBMCState, 1);
> - object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
> + object_initialize(&bmc->soc, (sizeof(bmc->soc)),
> TYPE_ASPEED_SOC);
> object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc-
> >soc),
> &error_abort);
>
> diff --git a/include/hw/arm/aspeed_soc.h
> b/include/hw/arm/aspeed_soc.h
> index e68807d475b7..bf63ae90cabe 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -1,5 +1,5 @@
> /*
> - * ASPEED AST2400 SoC
> + * ASPEED SoC family
> *
> * Andrew Jeffery <and...@aj.id.au>
> *
> @@ -9,8 +9,8 @@
> * the COPYING file in the top-level directory.
> */
>
> -#ifndef AST2400_H
> -#define AST2400_H
> +#ifndef ASPEED_SOC_H
> +#define ASPEED_SOC_H
>
> #include "hw/arm/arm.h"
> #include "hw/intc/aspeed_vic.h"
> @@ -20,7 +20,7 @@
> #include "hw/i2c/aspeed_i2c.h"
> #include "hw/ssi/aspeed_smc.h"
>
> -typedef struct AST2400State {
> +typedef struct AspeedSoCState {
> /*< private >*/
> DeviceState parent;
>
> @@ -34,11 +34,11 @@ typedef struct AST2400State {
> AspeedSMCState smc;
> AspeedSMCState spi;
> AspeedSDMCState sdmc;
> -} AST2400State;
> +} AspeedSoCState;
>
> -#define TYPE_AST2400 "ast2400"
> -#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
> +#define TYPE_ASPEED_SOC "aspeed-soc"
> +#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj),
> TYPE_ASPEED_SOC)
>
> #define AST2400_SDRAM_BASE 0x40000000
>
> -#endif /* AST2400_H */
> +#endif /* ASPEED_SOC_H */
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