On Tue, 5 Jul 2016 10:12:49 +0530
Bharata B Rao wrote:
> Introduce CPUState.prefer_arch_id_over_cpu_index and
> MachineClass.prefer_arch_id_over_cpu_index that allow target
> machines to optionally switch to using arch_id instead of cpu_index
> as instance_id in vmstate_register(). This will hel
On Tue, 5 Jul 2016 14:59:20 +1000
David Gibson wrote:
> On Tue, Jul 05, 2016 at 10:12:51AM +0530, Bharata B Rao wrote:
> > xics maintains an array of ICPState structures which is indexed
> > by cpu_index. Change this to index the ICPState array by arch_id
> > for pseries-2.7 onwards. This allows
On Sat, 07/02 14:36, Max Reitz wrote:
> On 28.06.2016 03:47, Fam Zheng wrote:
> > This was the only exceptional module init function that does something
> > else than a simple list of bdrv_register() calls, in all the block
> > drivers.
>
> This sounds like this patch specifically wants to drop th
On Tue, 5 Jul 2016 10:12:47 +0530
Bharata B Rao wrote:
> device_add/del based CPU hotplug and unplug support is upstream for
> sPAPR PowerPC and is under development for x86. Both of these will
> support CPU device removal in random order (and not necessarily in LIFO
> order). Random order remov
On 07/05/2016 02:56 PM, Fam Zheng wrote:
On Mon, 07/04 14:40, Paolo Bonzini wrote:
Now that json-streamer tries not to leak tokens on incomplete parse,
the tokens can be freed twice if QEMU destroys the json-streamer
object during the parser->emit call. To fix this, create the new
empty GQueue
On Tue, 5 Jul 2016 10:12:49 +0530
Bharata B Rao wrote:
> Introduce CPUState.prefer_arch_id_over_cpu_index and
> MachineClass.prefer_arch_id_over_cpu_index that allow target
> machines to optionally switch to using arch_id instead of cpu_index
> as instance_id in vmstate_register(). This will hel
On Tue, 07/05 15:16, Changlong Xie wrote:
> On 07/05/2016 02:56 PM, Fam Zheng wrote:
> > On Mon, 07/04 14:40, Paolo Bonzini wrote:
> > > Now that json-streamer tries not to leak tokens on incomplete parse,
> > > the tokens can be freed twice if QEMU destroys the json-streamer
> > > object during th
On Tue, 5 Jul 2016 10:12:49 +0530
Bharata B Rao wrote:
> Introduce CPUState.prefer_arch_id_over_cpu_index and
> MachineClass.prefer_arch_id_over_cpu_index that allow target
> machines to optionally switch to using arch_id instead of cpu_index
> as instance_id in vmstate_register(). This will hel
On Tue, 5 Jul 2016 12:05:35 +0530
Bharata B Rao wrote:
> On Tue, Jul 05, 2016 at 07:49:38AM +0200, Igor Mammedov wrote:
> > On Tue, 5 Jul 2016 10:46:07 +0530
> > Bharata B Rao wrote:
> >
> > > On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote:
> > > > On Tue, Jul 05, 2016 at 10:12:48
> I could actually see the use of non-raw over NBD. We support nested
> protocols (where you can use qcow2->qcow2->file), that is, where a file
> contains a qcow2 file whose contents are themselves a qcow2 image.
> (Perhaps useful in nested guests, where the outer qcow2 layer serves a
> disk to an
On Tue, 5 Jul 2016 12:05:35 +0530
Bharata B Rao wrote:
> On Tue, Jul 05, 2016 at 07:49:38AM +0200, Igor Mammedov wrote:
> > On Tue, 5 Jul 2016 10:46:07 +0530
> > Bharata B Rao wrote:
> >
> > > On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote:
> > > > On Tue, Jul 05, 2016 at 10:1
Am 05.07.2016 um 03:53 schrieb Eric Blake:
On 07/04/2016 07:49 AM, Peter Lieven wrote:
Hi,
the above commit:
commit d05aa8bb4a8b6aa9a915ec5074fb12ae632d2323
Author: Eric Blake
Date: Wed Jun 1 15:10:03 2016 -0600
block: Add .bdrv_co_pwrite_zeroes()
introduces a regression (at least fo
On Mon, Jul 04, 2016 at 06:22:56PM +0300, Michael S. Tsirkin wrote:
[...]
> > @@ -2425,6 +2427,9 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
> > AcpiDmarHardwareUnit *drhd;
> > uint8_t dmar_flags = 0;
> > X86IOMMUState *iommu = x86_iommu_get_default();
> > +AcpiDm
On Mon, 4 Jul 2016 18:39:21 +0200
Igor Mammedov wrote:
> On Mon, 4 Jul 2016 17:20:59 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Jun 24, 2016 at 06:06:03PM +0200, Igor Mammedov wrote:
> > > object_property_add_child() silently fails with error that it
> > > can't create duplicate propery
On Mon, Jul 04, 2016 at 04:22:49PM +0200, Paolo Bonzini wrote:
>
>
> On 21/06/2016 09:47, Peter Xu wrote:
> > This patch introduces x86 IOMMU IEC (Interrupt Entry Cache)
> > invalidation notifier list. When vIOMMU receives IEC invalidate
> > request, all the registered units will be notified with
On Tue, Jul 05, 2016 at 09:22:30AM +0200, Igor Mammedov wrote:
> On Tue, 5 Jul 2016 12:05:35 +0530
> Bharata B Rao wrote:
>
> > On Tue, Jul 05, 2016 at 07:49:38AM +0200, Igor Mammedov wrote:
> > > On Tue, 5 Jul 2016 10:46:07 +0530
> > > Bharata B Rao wrote:
> > >
> > > > On Tue, Jul 05, 2016 at
On Mon, Jul 04, 2016 at 04:23:32PM +0200, Paolo Bonzini wrote:
> FWIW I prefer this to the "v10.2".
Let me drop v10.2 then. Thanks,
-- peterx
Le 04/07/2016 à 18:06, Peter Maydell a écrit :
> Add support for the /dev/loop-control ioctls:
> LOOP_CTL_ADD
> LOOP_CTL_REMOVE
> LOOP_CTL_GET_FREE
>
> Signed-off-by: Peter Maydell
Reviewed-by: Laurent Vivier
> ---
> linux-user/ioctls.h | 4
> linux-user/linux_loop.h | 11 +
From: Alexander Yarygin
If bootindex is specified for a device, we need to IPL from
it. Currently it works for ccw devices, but not for SCSI. To be able to
IPL from the specific device, pc-bios needs to know its address.
For this reason we add special QEMU_SCSI IPL type into the IPLB
structure, t
From: Sascha Silbe
A lot of what virtio_ccw_device_realize() does isn't specific to
virtio; it would apply to emulated CCW as well. Factor it out to make
it easier to implement emulated CCW devices later on.
Signed-off-by: Sascha Silbe
Reviewed-by: Dong Jia Shi
Reviewed-by: Halil Pasic
Signed
From: "Eugene (jno) Dvurechenski"
There is ,bootindex=%d argument to specify the lookup order of
boot devices.
If a bootindex assigned to the device, then IPL Parameter Info Block
is created for that device when it is IPLed from.
If it is a mere SCSI device (not FCP), then IPIB is created with
The following patches (and the s390x pci patches already on the
list) make up the last batch of s390x patches I plan to do for
2.7 (except for bug fixes that may crop up, of course).
We have several fixes/enhancements in the boot code and a bit
of refactoring in the css code that makes the future
From: David Hildenbrand
When migrating from a different QEMU version, the start_address and
bios_start_address may differ. During migration these values are migrated
and overwrite the values that were detected by QEMU itself.
On a reboot, QEMU will reload its own BIOS, but use the migrated start
Dear Fam (or Zheng?),
Fam Zheng writes:
> This was the only exceptional module init function that does something
> else than a simple list of bdrv_register() calls, in all the block
> drivers.
>
> The qcrypto_hash_supports is actually a static check, determined at
> compile time. Follow the blo
From: Jing Liu
The previous patch moved virtual css bridge and bus out from
virtio-ccw, but kept the direct reference of virtio-ccw specific
unplug function inside css-bridge.c.
To make the virtual css bus and bridge useful for non-virtio devices,
this introduces a common unplug function pointer
From: Sascha Silbe
Introduce a TYPE_* define (like we already use for a couple of other
QOM types) for the name of the virtual CSS bridge QOM type instead of
sprinkling the same string literal over several source files.
Signed-off-by: Sascha Silbe
Signed-off-by: Cornelia Huck
---
hw/s390x/s39
From: Jing Liu
Currently, common base layers virtual css bridge and bus are
defined in hw/s390x/virtio-ccw.c(h). In order to support
multiple types of devices in the virtual channel subsystem,
especially non virtio-ccw, refactoring work needs to be done.
This work is just a pure code move withou
On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> Next round of patches. Changes:
>
> * Moved it all to a new sercon.c file.
> * Code maps cp437 to utf8 now, giving a much nicer display. Compare
>"Use the ↑ and ↓ keys to change the selection." (this series) with
>
Contains:
- pc-bios/s390-ccw: Pass selected SCSI device to IPL
Signed-off-by: Cornelia Huck
---
pc-bios/s390-ccw.img | Bin 26424 -> 26440 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/pc-bios/s390-ccw.img b/pc-bios/s390-ccw.img
index
ea5fd9a4797530e79e88f591f66c4de8e93a60
On Tue, 07/05 09:58, Sascha Silbe wrote:
> Dear Fam (or Zheng?),
Hi Sascha,
Zheng is the last name here. :)
>
> Fam Zheng writes:
>
> > This was the only exceptional module init function that does something
> > else than a simple list of bdrv_register() calls, in all the block
> > drivers.
>
On Tue, 5 Jul 2016 13:08:28 +0530
Bharata B Rao wrote:
> On Tue, Jul 05, 2016 at 09:22:30AM +0200, Igor Mammedov wrote:
> > On Tue, 5 Jul 2016 12:05:35 +0530
> > Bharata B Rao wrote:
> >
> > > On Tue, Jul 05, 2016 at 07:49:38AM +0200, Igor Mammedov wrote:
> > > > On Tue, 5 Jul 2016 10:46:07 +05
This is v11 of Intel IR work. It is rebased to mst's branch
"tags/for_upstream", commit:
"278a2a2 vmw_pvscsi: remove unnecessary internal msi state flag"
This series mainly fixed several issues in v10 review comments, fixed
one bug with RHEL guests, added acked-by for Paolo, and a fresh new
reb
Introducing parent class for intel-iommu devices named "x86-iommu". This
is preparation work to abstract shared functionalities out from Intel
and AMD IOMMUs. Currently, only the parent class is introduced. It does
nothing yet.
Signed-off-by: Peter Xu
---
hw/i386/Makefile.objs | 2 +-
h
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 11 +++
include/hw/i386/intel_iommu.h | 1 -
include/hw/i386/x86-iommu.h | 2 ++
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a430d7d..3ee5782 100644
--- a
Instead of searching the device tree every time, one static variable is
declared for the default system x86 IOMMU device.
Signed-off-by: Peter Xu
---
hw/i386/acpi-build.c| 9 ++---
hw/i386/x86-iommu.c | 23 +++
include/hw/i386/x86-iommu.h | 6 ++
3 f
Enable IR in IOMMU Extended Capability register.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 6 ++
hw/i386/intel_iommu_internal.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 8ea408d..3d99544 100644
--- a/hw/i386/
Remove VT-d calls in common q35 codes. Instead, we provide a general
find_add_as() for x86-iommu type.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 15 ---
include/hw/i386/intel_iommu.h | 5 -
include/hw/i386/x86-iommu.h | 3 +++
3 files changed, 11 insertions(
Adding one property for intel-iommu devices to specify whether we should
support interrupt remapping. By default, IR is disabled. To enable it,
we should use (take Intel IOMMU as example):
-device intel_iommu,intremap=on
This property can be shared by Intel and future AMD IOMMUs.
Signed-off-by
Queued invalidation is required for IR. This patch add basic support for
interrupt cache invalidate requests. Since we currently have no IR cache
implemented yet, we can just skip all interrupt cache invalidation
requests for now.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 9 ++
In ACPI DMA remapping report structure, enable INTR flag when specified.
Signed-off-by: Peter Xu
---
hw/i386/acpi-build.c | 14 +-
include/hw/i386/intel_iommu.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.
Handle writting to IRE bit in global command register.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c793031..a12091e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386
On Tue 05 Jul 2016 09:58:25 AM CEST, Sascha Silbe wrote:
> The quorum driver needs SHA256 which was introduced in gnutls 2.11.1.
Are you sure about that?
* Version 1.7.4 (released 2007-02-05)
[...]
** API and ABI modifications:
GNUTLS_MAC_SHA256,
GNUTLS_MAC_SHA384,
GNUTLS_MAC_SHA512: New gnutl
Defined Interrupt Remap Table Address register to store IR table
pointer. Also, do proper handling on global command register writes to
store table pointer and its size.
One more debug flag "DEBUG_IR" is added for interrupt remapping.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c |
On 04/07/2016 21:53, Gerd Hoffmann wrote:
> Hi,
>
What about graphics threads ? In particular I'd be thinking of spice
which uses threads and chardevs.
>>>
>>> I think it should be quiesced after pause_all_vcpus returns. Marc-André
>>> should know, but it's better to check with Gerd
Abstract IOAPIC entry parsing logic into a helper function.
Signed-off-by: Peter Xu
---
hw/intc/ioapic.c | 110 +++
1 file changed, 54 insertions(+), 56 deletions(-)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 36dd42a..c4469e4 10064
Several data structs are defined to better support the rest of the
patches: IRTE to parse remapping table entries, and IOAPIC/MSI related
structure bits to parse interrupt entries to be filled in by guest
kernel.
Signed-off-by: Peter Xu
---
include/hw/i386/intel_iommu.h | 74
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be explicitly enumerated under
one specific remapping hardware unit. This patch adds the root-complex
IOAPIC into the default DMAR device.
Please refer to VT-d spec 8.3.1.1 for more i
On 04/07/2016 14:58, Gerd Hoffmann wrote:
> On Mo, 2016-07-04 at 13:38 +0100, Peter Maydell wrote:
>> On 4 July 2016 at 07:30, Gerd Hoffmann wrote:
>>> Hi,
>>>
>>> Here comes the ipxe update for 2.7, rebasing the ipxe module to latest
>>> master and also adding boot roms for e1000e and vmxnet3
This patch introduces x86 IOMMU IEC (Interrupt Entry Cache)
invalidation notifier list. When vIOMMU receives IEC invalidate
request, all the registered units will be notified with specific
invalidation requests.
Intel IOMMU is the first provider that generates such a event.
Signed-off-by: Peter X
Adding translation fault definitions for interrupt remapping. Please
refer to VT-d spec section 7.1.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu_internal.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index
* Eduardo Habkost (ehabk...@redhat.com) wrote:
> On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote:
> [...]
> > @@ -2084,6 +2085,27 @@ static int kvm_get_msrs(X86CPU *cpu)
> > }
> >
> > assert(ret == cpu->kvm_msr_buf->nmsrs);
> > +/*
> > + * MTRR masks
Let IOAPIC the first consumer of x86 IOMMU IEC invalidation
notifiers. This is only used for split irqchip case, when vIOMMU
receives IR invalidation requests, IOAPIC will be notified to update
kernel irq routes. For simplicity, we just update all IOAPIC routes,
even if the invalidated entries are
This patch enables interrupt remapping for PCI devices.
To play the trick, one memory region "iommu_ir" is added as child region
of the original iommu memory region, covering range 0xfeeX (which is
the address range for APIC). All the writes to this range will be taken
as MSI, and translation
* Eduardo Habkost (ehabk...@redhat.com) wrote:
> On Mon, Jul 04, 2016 at 08:16:07PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > A special case based on the previous phys-bits property; if it's
> > the magic value 0 then use the hosts capabilities.
> >
>
From: Jan Kiszka
As neither QEMU nor KVM support more than 255 CPUs so far, this is
simple: we only need to switch the destination ID translation in
vtd_remap_irq_get if EIME is set.
Once CFI support is there, it will have to take EIM into account as
well. So far, nothing to do for this.
This p
This patch translates all IOAPIC interrupts into MSI ones. One pseudo
ioapic address space is added to transfer the MSI message. By default,
it will be system memory address space. When IR is enabled, it will be
IOMMU address space.
Currently, only emulated IOAPIC is supported.
Idea suggested by
Changing the original MSIMessage parameter in kvm_irqchip_add_msi_route
into the vector number. Vector index provides more information than the
MSIMessage, we can retrieve the MSIMessage using the vector easily. This
will avoid fetching MSIMessage every time before adding MSI routes.
Meanwhile, th
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver i
Adding two hooks to be notified when adding/removing msi routes. There
are two kinds of MSI routes:
- in kvm_irqchip_add_irq_route(): before assigning IRQFD. Used by
vhost, vfio, etc.
- in kvm_irqchip_send_msi(): when sending direct MSI message, if
direct MSI not allowed, we will first create
This patch enables SID validation. Invalid interrupts will be dropped.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 69 ---
include/hw/i386/intel_iommu.h | 17 +++
2 files changed, 75 insertions(+), 11 deletions(-)
diff --git a/hw/i
These will help us monitoring irqchip route activities more easily.
Signed-off-by: Peter Xu
Reviewed-by: Paolo Bonzini
---
kvm-all.c| 5 +
trace-events | 3 +++
2 files changed, 8 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 3764ba9..ef81ca5 100644
--- a/kvm-all.c
+++ b/kvm-a
One more IEC notifier is added to let msi routes know about the IEC
changes. When interrupt invalidation happens, all registered msi routes
will be updated for all PCI devices.
Since both vfio and vhost are possible gsi route consumers, this patch
will go one step further to keep them safe in spli
When user specify "kernel-irqchip=on", throw error and then quit.
Signed-off-by: Peter Xu
Reviewed-by: Paolo Bonzini
---
hw/i386/intel_iommu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 8a91e64..76471ad 100644
--- a/hw/i386/i
In the past, we are doing gsi route commit for each irqchip route
update. This is not efficient if we are updating lots of routes in the
same time. This patch removes the committing phase in
kvm_irqchip_update_msi_route(). Instead, we do explicit commit after all
routes updated.
Signed-off-by: Pet
On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote:
> This was the only exceptional module init function that does something
> else than a simple list of bdrv_register() calls, in all the block
> drivers.
>
> The qcrypto_hash_supports is actually a static check, determined at
> compile time
From: Radim Krčmář
Linux guests do not gracefully handle cases when the invalidation mask
they wanted is not supported, probably because real hardware always
allowed all.
We can just say that all 16 masks are supported, because both
ioapic_iec_notifier and kvm_update_msi_routes_all invalidate al
On 4 July 2016 at 16:26, Gerd Hoffmann wrote:
> Hi,
>
> Reverts patch and also remove pc-bios/bios-fast.bin.
>
> please pull,
> Gerd
>
> The following changes since commit 3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-201
On Tue, 07/05 09:45, Daniel P. Berrange wrote:
> On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote:
> > This was the only exceptional module init function that does something
> > else than a simple list of bdrv_register() calls, in all the block
> > drivers.
> >
> > The qcrypto_hash_suppor
On Mon, 07/04 19:09, Paolo Bonzini wrote:
> Hi,
>
> I meant to send these close to soft freeze because the final patch is
> prone to conflicts, but it turns out I didn't send them. Still they're
> pretty mechanical so I'm shooting them out now. Any thoughts?
I didn't review patch 3 line by line
Dear Alberto,
Alberto Garcia writes:
> On Tue 05 Jul 2016 09:58:25 AM CEST, Sascha Silbe wrote:
>
>> The quorum driver needs SHA256 which was introduced in gnutls 2.11.1.
>
> Are you sure about that?
>
> * Version 1.7.4 (released 2007-02-05)
>
> [...]
>
> ** API and ABI modifications:
> GNUTLS_M
currently all the libgfapi logs defaults to '/dev/stderr' as it was hardcoded
in a call to glfs logging api, in case if debug level is chosen to DEBUG/TRACE
gfapi logs will be huge and fill/overflow the console view.
this patch provides a commandline option to mention log file path which helps
in
On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote:
> The point of using qcrypto_hash_supports() is that it isolates the
> block code Makefile rules from the details of the current specific
> impl of the hash APIs in QEMU. As a prime example of why this is
> important, try rebasing to G
Hi
On Tue, Jul 5, 2016 at 12:35 AM, Michael S. Tsirkin wrote:
> On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote:
>> Hi
>>
>> On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote:
>> > Why does vhost_user_set_log_base need to return error?
>> > If backend is not there to han
On Tue, Jul 05, 2016 at 11:18:29AM +0200, Alberto Garcia wrote:
> On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote:
>
> > The point of using qcrypto_hash_supports() is that it isolates the
> > block code Makefile rules from the details of the current specific
> > impl of the hash APIs
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > QEMU sets the guests physical address bits to 40; this is wrong
> > on most hardware, and can be detected by the guest.
> > It a
On Tue, Jul 05, 2016 at 04:57:58PM +0800, Fam Zheng wrote:
> On Tue, 07/05 09:45, Daniel P. Berrange wrote:
> > On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote:
> > > This was the only exceptional module init function that does something
> > > else than a simple list of bdrv_register() ca
On Mon, Jul 04, 2016 at 08:16:08PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> On 32 bit systems fix up phys_bits to be consistent with what
> we tell the guest; don't ever bother with using the phys_bits
> property.
> @@ -2990,6 +2986,15 @@ static void x86_cp
On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> QEMU sets the guests physical address bits to 40; this is wrong
> on most hardware, and can be detected by the guest.
> It also stops you using really huge multi-TB VMs.
>
> Red Hat
* Daniel P. Berrange (berra...@redhat.com) wrote:
> On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > QEMU sets the guests physical address bits to 40; this is wrong
> > on most hardware, and can be detected by the guest.
> >
On Tue, Jul 5, 2016 at 3:49 AM, Hailiang Zhang
wrote:
> On 2016/7/4 20:22, Baptiste Reynal wrote:
>>
>> On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang
>> wrote:
>>>
>>> For now, we still didn't support live memory snapshot, we have discussed
>>> a scheme which based on userfaultfd long time ago.
>
On Di, 2016-07-05 at 09:06 +0100, Daniel P. Berrange wrote:
> On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > Next round of patches. Changes:
> >
> > * Moved it all to a new sercon.c file.
> > * Code maps cp437 to utf8 now, giving a much nicer display. Compare
On Tue, Jul 05, 2016 at 10:26:56AM +0100, Daniel P. Berrange wrote:
> On Tue, Jul 05, 2016 at 11:18:29AM +0200, Alberto Garcia wrote:
> > On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote:
> >
> > > The point of using qcrypto_hash_supports() is that it isolates the
> > > block code Mak
On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > QEMU sets the guests physical address bit
On 4 July 2016 at 17:46, Michael S. Tsirkin wrote:
> The following changes since commit e2c8f9e44e07d8210049abaa6042ec3c956f1dd4:
>
> Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into
> staging (2016-07-04 10:49:17 +0100)
>
> are available in the git repository at:
>
>
On Tue, Jul 05, 2016 at 12:00:48PM +0200, Gerd Hoffmann wrote:
> On Di, 2016-07-05 at 09:06 +0100, Daniel P. Berrange wrote:
> > On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > Next round of patches. Changes:
> > >
> > > * Moved it all to a new sercon.c fi
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git)
> > > wrote:
> > > > From: "Dr. David Alan Gilbert"
On 2016/7/5 17:57, Baptiste Reynal wrote:
On Tue, Jul 5, 2016 at 3:49 AM, Hailiang Zhang
wrote:
On 2016/7/4 20:22, Baptiste Reynal wrote:
On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang
wrote:
For now, we still didn't support live memory snapshot, we have discussed
a scheme which based on us
We use colo-base.h to track connection and parse packet
Signed-off-by: Zhang Chen
Signed-off-by: Li Zhijian
Signed-off-by: Wen Congyang
---
net/filter-rewriter.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/net/filter-rewriter.c b/net/
We will rewrite tcp packet secondary received and sent.
When colo guest is a tcp server.
Firstly, client start a tcp handshake. the packet's seq=client_seq,
ack=0,flag=SYN. COLO primary guest get this pkt and mirror(filter-mirror)
to secondary guest, secondary get it use filter-redirector.
Then,pr
Filter-rewriter is a part of COLO project.
It will rewrite some of secondary packet to make
secondary guest's tcp connection established successfully.
In this module we will rewrite tcp packet's ack to the secondary
from primary,and rewrite tcp packet's seq to the primary from
secondary.
usage:
c
Filter-rewriter is a part of COLO project.
So this patch set depend on colo-compare.
It will rewrite some of secondary packet to make
secondary guest's connection established successfully.
In this module we will rewrite tcp packet's ack to the secondary
from primary,and rewrite tcp packet's seq to
Eric Blake writes:
> On 07/04/2016 03:41 AM, Lluís Vilanova wrote:
>> Signed-off-by: Lluís Vilanova
>> Reviewed-by: Stefan Hajnoczi
>> ---
>> hmp-commands-info.hx |6 +-
>> hmp-commands.hx |7 +-
>> monitor.c| 17 +-
>> qapi/trace.json | 32 +--
>> qmp-c
On Tue, Jul 05, 2016 at 11:13:26AM +0100, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Mon, Jul 04, 2016 at 08:16:03PM +0100, D
* Eduardo Habkost (ehabk...@redhat.com) wrote:
> On Mon, Jul 04, 2016 at 08:16:09PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > Add some sanity checks on the phys-bits setting now that
> > the user can set it.
> >a) That it's in a sane range (52..32)
The qcrypto hash APIs now guarantee that sha256 is available at
compile time, so skipping registration is rarely needed. A check
at time of open is kept to ensure good error reporting in the
(unlikely) case sha256 is runtime disabled.
This reverts commit e94867ed5f241008d0f53142b2704a075f9ed505.
-
GLib >= 2.16 provides GChecksum API which is good enough
for md5, sha1, sha256 and sha512. Use this as a final
fallback if neither nettle or gcrypt are available. This
lets us remove the stub hash impl, and so callers can
be sure those 4 algs are always available at compile
time. They may still be
This uses the GChecksum APIs as final hash impl, instead of
a no-op stub. This lets us remove conditional registration
of the quorum driver.
Daniel P. Berrange (2):
crypto: use glib as fallback for hash algorithm
Revert "block: don't register quorum driver if SHA256 support is
unavailable"
On 05/07/2016 12:06, Michael S. Tsirkin wrote:
> > -m 2G,slots=16,maxmem=2T
> >
> > On a host with a 39bit physaddress limit do you error
> > on that or not? I think oVirt is currently doing something
> > similar to that, but I'm trying to get confirmation.
>
> That would only be a proble
On Tue, Jul 05, 2016 at 12:59:42PM +0200, Paolo Bonzini wrote:
>
>
> On 05/07/2016 12:06, Michael S. Tsirkin wrote:
> > > -m 2G,slots=16,maxmem=2T
> > >
> > > On a host with a 39bit physaddress limit do you error
> > > on that or not? I think oVirt is currently doing something
> > > simila
On Tue, Jul 05, 2016 at 11:18:38AM +0200, Marc-André Lureau wrote:
> Hi
>
> On Tue, Jul 5, 2016 at 12:35 AM, Michael S. Tsirkin wrote:
> > On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote:
> >> Hi
> >>
> >> On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote:
> >> > Why doe
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