.can_receive callback changes semantics that once return 0, backend will
try sending again until explicitly flushed, change the device to meet
that.
dp8393x_can_receive checks SONIC_CR_RXEN bit in SONIC_CR register and
SONIC_ISR_RBE bit in SONIC_ISR register, try flushing the queue when
either bit
Needs a short paragraph. List out the initally support peripherals.
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
wrote:
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> Changes since v1:
> * not present on v1
>
> Changes since v2:
> * not present on v2
>
> Changes since v3:
>
On Sun, 5 Jul 2015 21:18:11 -0700
Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 6:41 AM, Aurelien Jarno wrote:
> > On 2015-06-30 21:12, Serge Vakulenko wrote:
> >> Signed-off-by: Serge Vakulenko
> >> ---
> >> hw/mips/Makefile.objs |3 +
> >> hw/mips/mips_pic32mx7.c | 1652 +
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
> On Sat, 07/04 10:47, Max Filippov wrote:
>> Hello,
>>
>> I'm using QEMU with TAP network and after the commit
>> 0a2df857a703 "Merge remote-tracking branch
>> 'remotes/stefanha/tags/net-pull-request' into staging"
>> I've noticed that activation o
On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
We can know if VM in destination should go into COLO mode by refer to
the info that has been migrated from PVM.
Signed-off-by: zhanghailiang
Signed-off-by: Yang Hongyang
Signed-off-by: Lai
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
wrote:
> Tested by booting a minimal linux system on the emulated plateform
"Linux" "platform"
>
> Note: Qdev construction helper functions are removed with this patch.
>
So is the goal of the inline header movements to minimise the file
sc
On Mon, 07/06 10:27, Max Filippov wrote:
> On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
> > On Sat, 07/04 10:47, Max Filippov wrote:
> >> Hello,
> >>
> >> I'm using QEMU with TAP network and after the commit
> >> 0a2df857a703 "Merge remote-tracking branch
> >> 'remotes/stefanha/tags/net-pull-r
On Mon, 07/06 15:36, Fam Zheng wrote:
> On Mon, 07/06 10:27, Max Filippov wrote:
> > On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
> > > On Sat, 07/04 10:47, Max Filippov wrote:
> > >> Hello,
> > >>
> > >> I'm using QEMU with TAP network and after the commit
> > >> 0a2df857a703 "Merge remote-tr
Many of the same comments I had before for IMX31 apply.
Liviu, CCd is actually working on a simlar problem for multiple SoCs
of the same family using a mostly the same definition. I think the
same applies to the i.MXxx families.
How I suggest this can one can be done to avoid the code dup is:
1:
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
wrote:
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> Changes since v1:
> * Added a ds1338 I2C device for qtest purpose.
>
> Changes since v2:
> * none
>
> Changes since v3:
> * Rework GPL header
> * use I2C constructor hel
On Mon, Jul 6, 2015 at 10:36 AM, Fam Zheng wrote:
> On Mon, 07/06 10:27, Max Filippov wrote:
>> On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
>> > On Sat, 07/04 10:47, Max Filippov wrote:
>> >> Hello,
>> >>
>> >> I'm using QEMU with TAP network and after the commit
>> >> 0a2df857a703 "Merge re
On 04/07/2015 23:19, Michael S. Tsirkin wrote:
> The fact that address_space_write/_read actually does a byteswap if
> host!=target endian should probably be documented.
FWIW, it's not if host != target endian. It's if memory region
endianness != target endianness. See memory_region_wrong_endi
On Sun, 5 Jul 2015 21:27:04 -0700
Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 10:56 PM, Antony Pavlov
> wrote:
> > On Tue, 30 Jun 2015 21:12:34 -0700
> > Serge Vakulenko wrote:
> >
> >> Signed-off-by: Serge Vakulenko
> >> ---
> >> hw/mips/Makefile.objs |3 +
> >> hw/mips/mips_p
Hi,
Recently we encountered a problem in our project: 2 CPUs in VM are not brought
up normally after reboot.
Our host is using KVM kmod 3.6 and QEMU 2.1.
A SLES 11 sp3 VM configured with 8 vcpus,
cpu model is configured with 'host-passthrough'.
After VM's first time started up, everything seem
On Mon, 07/06 10:45, Max Filippov wrote:
> On Mon, Jul 6, 2015 at 10:36 AM, Fam Zheng wrote:
> > On Mon, 07/06 10:27, Max Filippov wrote:
> >> On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
> >> > On Sat, 07/04 10:47, Max Filippov wrote:
> >> >> Hello,
> >> >>
> >> >> I'm using QEMU with TAP ne
On Sun, Jul 5, 2015 at 11:15 PM, Serge Vakulenko
wrote:
> Implement pic32 SPI peripheral interface.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/pic32_spi.c | 121
>
SPI controllers go in hw/ssi.
> 1 file changed, 121 insertions(+)
>
On Sun, Jul 5, 2015 at 11:14 PM, Serge Vakulenko
wrote:
> Data definitions and function declarations for simulation
> of pic32 microcontrollers.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/pic32_peripherals.h | 210
>
> 1 file changed, 210 ins
- Le 6 Juil 15, à 8:40, Peter Crosthwaite a
écrit :
> On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
> wrote:
> > Move constructor to DeviceClass methods
> > * imx_serial_init
> > * imx_serial_realize
> > imx32_serial_properties is renamed to imx_serial_properties.
> > The Qdev c
On Sun, Jul 5, 2015 at 11:15 PM, Serge Vakulenko
wrote:
> Implement access to SD card, attached to pic32 SPI port.
>
Can you use sd.c SD card definition?
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/pic32_sdcard.c | 428
> +
> 1 file changed
On Sun, Jul 5, 2015 at 11:14 PM, Serge Vakulenko
wrote:
> Implement pic32 UART peripheral interface.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/pic32_uart.c | 228
> +++
> 1 file changed, 228 insertions(+)
> create mode 100644 hw/mips/pic
QEMU targets ISAs contain instruction that can break the execution
flow with exceptions. When exception breaks the execution of the translation
block it may corrupt PC and icount values.
This set of patches fixes exception handling for MIPS, PowerPC, and i386
targets.
Incorrect execution for i38
This patch introduces loop exit function, which also
restores guest CPU state according to the value of host
program counter.
Reviewed-by: Richard Henderson
Reviewed-by: Aurelien Jarno
Signed-off-by: Pavel Dovgalyuk
---
cpu-exec.c |9 +
include/exec/exec-all.h |1
This patch introduces new versions of raise_exception functions
that receive TB return address as an argument.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/cpu.h |4
target-i386/excp_helper.c | 26 +++---
2 files changed, 23 insertions(+), 7 deletions(-)
This patch fixes exception handling for other helper functions.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/cc_helper.c |2 +-
target-i386/misc_helper.c | 10 +-
target-i386/ops_sse.h |2 +-
target-i386/svm_helper.c |4 ++--
4 files changed, 9 insertions(+), 9 del
This patch introduces several helpers to pass return address
which points to the TB. Correct return address allows correct
restoring of the guest PC and icount. These functions should be used when
helpers embedded into TB invoke memory operations.
Reviewed-by: Richard Henderson
Signed-off-by: Pa
This patch fixes exception handling for FPU instructions.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/fpu_helper.c | 146 +-
1 files changed, 80 insertions(+), 66 deletions(-)
diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
index
This patch fixes exception handling for div instructions.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/int_helper.c | 32
1 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index b0d78e6..3dcd2
This patch removes useless PC updates before executing instructions.
PC can be recovered with correct exception handling by using TB return address.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/translate.c | 25 -
1 files changed, 0 insertions(+), 25 deletions(-)
dif
This patch fixes exception handling for seg_helper functions.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/seg_helper.c | 646 +++---
1 files changed, 330 insertions(+), 316 deletions(-)
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling does not correctly
restore icount for the instruction which caused the
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
> On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
> >* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
> >>We can know if VM in destination should go into COLO mode by refer to
> >>the info that has been migrated from PVM.
> >>
> >>Signe
This patch fixes exception handling for memory helpers.
Signed-off-by: Pavel Dovgalyuk
---
target-i386/mem_helper.c | 39 ++-
1 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 1aec8a5..
This patch fixes exception handling in PowerPC.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling does not correctly
restore icount for the instruction which caused the
Hi.
If a base qcow2 image snapshot chain like this:
base.qcow2: [A] -> [B] -> [C]
[C] is the current image where guest read/write to,usually we create a new
image base on the base.qcow2 like this
qemu-img create -f qcow2 -o backing_file=/path/base.qcow2 new.qcow2
so the data of new.qcow2 is
On Mon, Jul 06, 2015 at 09:46:14AM +0200, Paolo Bonzini wrote:
>
>
> On 04/07/2015 23:19, Michael S. Tsirkin wrote:
> > The fact that address_space_write/_read actually does a byteswap if
> > host!=target endian should probably be documented.
>
> FWIW, it's not if host != target endian. It's if
On 2015-07-05 16:25, Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 3:02 AM, Aurelien Jarno wrote:
> > On 2015-06-30 21:12, Serge Vakulenko wrote:
> >> @@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
> >> */
> >> if (!kvm_enabled()) {
> >> env->timer = timer_n
On 2015-07-05 17:03, Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 3:11 AM, Aurelien Jarno wrote:
> > On 2015-06-30 21:12, Serge Vakulenko wrote:
> >> Signed-off-by: Serge Vakulenko
> >> ---
> >> hw/mips/cputimer.c | 18 +-
> >> 1 file changed, 5 insertions(+), 13 deletions(-)
On 2015-07-05 20:48, Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 6:37 AM, Aurelien Jarno wrote:
> > On 2015-06-30 21:12, Serge Vakulenko wrote:
> >> Signed-off-by: Serge Vakulenko
> >> ---
> >> target-mips/cpu.h| 2 ++
> >> target-mips/translate_init.c | 46
> >> +++
On 2015-07-05 23:14, Serge Vakulenko wrote:
> Currently the clock rate for all MIPS platforms is fixed at 100MHz.
> Need to make it 40MHz for pic32mx7.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/cputimer.c| 15 +++
> hw/mips/mips_fulong2e.c | 2 +-
> hw/mips/mips_j
On 05/07/2015 23:08, Peter Crosthwaite wrote:
> There was a complicated subtractive arithmetic for determining the
> padding on the CPUTLBEntry structure. Simplify this with a union.
>
> Signed-off-by: Peter Crosthwaite
> ---
> include/exec/cpu-defs.h | 23 ---
> 1 file cha
On Mon, Jul 6, 2015 at 1:01 AM, wrote:
>
>
> - Le 6 Juil 15, à 8:40, Peter Crosthwaite
> a écrit :
>
> On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
> wrote:
>> Move constructor to DeviceClass methods
>> * imx_serial_init
>> * imx_serial_realize
>>
>> imx32_serial_properties is r
On 2015-07-05 23:14, Serge Vakulenko wrote:
> The LFSR algorithm, used for generating random TLB indexes for TLBWR
> instruction,
> was inclined to produce a degenerate sequence in some cases.
> For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
> 7, 2, 7, 2, 7, 2, 7, 2, 7, 2,
On 06/07/2015 10:33, Michael S. Tsirkin wrote:
> Also, by luck, some values work the same whatever the endian-ness.
> E.g. dma_memory_set fills the buffer with a given pattern, so
> nothing changes if you byte-swap it.
>
> Here's an example that's wrong: dp8393x. Typically it's accessing
> memor
On 07/04/15 01:00, Laurent Vivier wrote:
On 04/07/2015 00:42, Paolo Bonzini wrote:
Loading the BIOS in the mac99 machine is interesting, because there is a
PROM in the middle of the BIOS region (from 16K to 32K). Before memory
region accesses were clamped, when QEMU was asked to load a BIOS fr
On 07/03/15 09:18, David Gibson wrote:
On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
Current PPC code relies on -mem-path being used in order for
hugepage support to be detected. With the introduction of
MemoryBackendFile we can now handle this via:
-object memory-file-backend
On 2015/7/6 16:29, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
We can know if VM in destination should go into COLO mode by refer to
the info that h
On 06/07/2015 10:51, Alexander Graf wrote:
> On 07/04/15 01:00, Laurent Vivier wrote:
>>
>> On 04/07/2015 00:42, Paolo Bonzini wrote:
>>> Loading the BIOS in the mac99 machine is interesting, because there is a
>>> PROM in the middle of the BIOS region (from 16K to 32K). Before memory
>>> region
On 06/07/2015 09:54, zhanghailiang wrote:
>
> From host, we found that QEMU vcpu1 thread and vcpu7 thread were not
> consuming any cpu (Should be in idle state),
> All of VCPUs' stacks in host is like bellow:
>
> [] kvm_vcpu_block+0x65/0xa0 [kvm]
> [] __vcpu_run+0xd1/0x260 [kvm]
> [] kvm_arch_v
On Mon, Jul 6, 2015 at 1:43 AM, Paolo Bonzini wrote:
>
>
> On 05/07/2015 23:08, Peter Crosthwaite wrote:
>> There was a complicated subtractive arithmetic for determining the
>> padding on the CPUTLBEntry structure. Simplify this with a union.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> inc
On 06/07/2015 10:58, Peter Crosthwaite wrote:
>> > Which compiler version started implementing anonymous structs?
>> >
> ISO C11 standardises it apparently. But various parts of the tree use
> them now. target-arm/cpu.h, target-i386/kvm.c,
> linux-user/syscall_defs.h and linux-headers/linux/kvm.h
On 2015-07-05 23:14, Serge Vakulenko wrote:
> Data definitions and function declarations for simulation
> of pic32 microcontrollers.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/pic32_peripherals.h | 210
>
> 1 file changed, 210 insertions(+)
>
On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
>
>
> On 06/07/2015 10:33, Michael S. Tsirkin wrote:
> > Also, by luck, some values work the same whatever the endian-ness.
> > E.g. dma_memory_set fills the buffer with a given pattern, so
> > nothing changes if you byte-swap it.
> >
On 6 July 2015 at 10:06, Michael S. Tsirkin wrote:
> On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
>> Why host endian and not device (in this case little) endian?
> It's the endian of the originator of the transaction.
> And emulated device code is all compiled in host endian-nes
On 6 July 2015 at 02:27, Dmitry Osipenko wrote:
> The timer should fire the interrupt only if the IT (interrupt enable) bit
> state of the control register is enabled.
>
> Signed-off-by: Dmitry Osipenko
> Reviewed-by: Peter Crosthwaite
If you need to update a patch, please resend the whole seri
On 2015-07-05 20:05, Serge Vakulenko wrote:
> >> } else {
> >> /* A MIPS configured with compatibility or VInt (Vectored
> >> Interrupts)
> >> diff --git a/target-mips/helper.c b/target-mips/helper.c
> >> index 8e3204a..7e25998 100644
> >> --- a/target-mips/helper.c
> >> +++ b/target
On 07/02/2015 09:09 PM, Zavadovsky Yan wrote:
> I tested this patch on my 4-cores cpu.
> Debug and release builds both.
> Win32 and Win64 binaries both. (I used old Fedora 17-18 with SJLJ mingw-w64
> to crossbuild for Win64.)
> With default Qemu BIOS and with myself-builded OVMF(also debug and rel
On 2015-07-05 20:31, Serge Vakulenko wrote:
> On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
> wrote:
> > On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno wrote:
> >> On 2015-06-30 21:12, Serge Vakulenko wrote:
> >>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> >>> index c476166..ab830ee 1
On 2015-07-05 23:14, Serge Vakulenko wrote:
> EIC is required for pic32 microcontroller.
>
> Signed-off-by: Serge Vakulenko
> ---
> hw/mips/cputimer.c | 17 +++--
> hw/mips/mips_int.c | 8 +++-
> target-mips/cpu.h| 8 +++-
> target-mips/helper.c | 18 ---
On 2015-07-05 23:14, Serge Vakulenko wrote:
> Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation.
>
> Signed-off-by: Serge Vakulenko
> ---
> target-mips/translate_init.c | 46
>
> 1 file changed, 46 insertions(+)
>
> diff --git a/target-
* Wen Congyang (ghost...@gmail.com) wrote:
> At 2015/7/3 23:30, Dr. David Alan Gilbert Wrote:
> >* Wen Congyang (we...@cn.fujitsu.com) wrote:
> >>Block replication is a very important feature which is used for
> >>continuous checkpoints(for example: COLO).
> >>
> >>Usage:
> >>Please refer to docs/b
While testing with a 1GB VHD file created on win7, found that the VHD file
size reported on Windows is different from that is reported by qemu-img
info or within a Linux KVM guest.
Created a dynamic VHD file on win7, on Windows, it is reported 1024MB
(2097152 sectors). But with qemu-img info or wi
From: Sergey Fedorov
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.
Signed-off-by: Sergey Fedorov
Message-id: 1435676538-31345-1-git-send-email-serge.f...@gmail.com
in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150706
for you to fetch changes up to 257621a9566054472d1d55a819880d0f9da02bda:
arm_mptimer: Respect IT bit state (2015-07-06 10:2
On 2015/7/6 16:45, Paolo Bonzini wrote:
On 06/07/2015 09:54, zhanghailiang wrote:
From host, we found that QEMU vcpu1 thread and vcpu7 thread were not
consuming any cpu (Should be in idle state),
All of VCPUs' stacks in host is like bellow:
[] kvm_vcpu_block+0x65/0xa0 [kvm]
[] __vcpu_run+0x
The arm_gic_common reset function was missing reset code for
several of the GIC's state fields:
* bpr[]
* abpr[]
* priority1[]
* priority2[]
* sgi_pending[]
* irq_target[] (SMP configurations only)
These probably went unnoticed because most guests will either
never touch them, or will write
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), an
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1435672316-3311-3-git-send-email-peter.may
From: Dmitry Osipenko
The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Peter Crosthwaite
Signed-off-by: Peter Maydell
---
hw/timer/arm_mptimer.c | 2 +-
1 file changed, 1 insertion(
From: Johannes Schlatow
The interval interrupt is not set if the timer is in decrement mode.
This is because x >=0 and x < interval after leaving the while-loop.
Signed-off-by: Johannes Schlatow
Message-id: 20150630135821.51f3b4fd@johanness-latitude
Reviewed-by: Peter Crosthwaite
Signed-off-by
On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
> On 6 July 2015 at 10:06, Michael S. Tsirkin wrote:
> > On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
> >> Why host endian and not device (in this case little) endian?
>
> > It's the endian of the originator of the t
From: Dmitry Osipenko
The running timer can't be stopped because timer control code just
doesn't handle disabling the timer. Fix it by deleting the timer if
the enable bit is cleared.
The timer won't start periodic ticking if a ONE-SHOT -> PERIODIC mode
change happens after a one-shot tick was c
On 6 July 2015 at 11:03, Michael S. Tsirkin wrote:
> On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
>> But address_space_rw() is just the "memcpy bytes to the
>> target's memory" operation -- if you have a pile of bytes
>> then there are no endianness concerns. If you don't have
>>
On 07/06/2015 05:42 PM, Dr. David Alan Gilbert wrote:
> * Wen Congyang (ghost...@gmail.com) wrote:
>> At 2015/7/3 23:30, Dr. David Alan Gilbert Wrote:
>>> * Wen Congyang (we...@cn.fujitsu.com) wrote:
Block replication is a very important feature which is used for
continuous checkpoints(fo
Works fine here,
Thanks !
- Mail original -
De: "Fam Zheng"
À: "qemu-devel"
Cc: "Kevin Wolf" , "Jeff Cody" ,
qemu-bl...@nongnu.org, mre...@redhat.com, js...@redhat.com, "aderumier"
, "stefanha" , "pbonzini"
Envoyé: Lundi 6 Juillet 2015 05:28:11
Objet: [PATCH] blockjob: Don't sleep t
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
> This patch introduces several helpers to pass return address
> which points to the TB. Correct return address allows correct
> restoring of the guest PC and icount. These functions should be used when
> helpers embedded into TB invoke memory operations.
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
> This patch introduces loop exit function, which also
> restores guest CPU state according to the value of host
> program counter.
>
> Reviewed-by: Richard Henderson
> Reviewed-by: Aurelien Jarno
>
> Signed-off-by: Pavel Dovgalyuk
> ---
> cpu-exec.
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
> This patch improves exception handling in MIPS.
> Instructions generate several types of exceptions.
> When exception is generated, it breaks the execution of the current
> translation
> block. Implementation of the exceptions handling does not correct
On Mon, Jul 06, 2015 at 11:04:24AM +0100, Peter Maydell wrote:
> On 6 July 2015 at 11:03, Michael S. Tsirkin wrote:
> > On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
> >> But address_space_rw() is just the "memcpy bytes to the
> >> target's memory" operation -- if you have a pile
t:
git://github.com/OSLL/qemu-xtensa.git tags/20150706-xtensa
for you to fetch changes up to 1479073b7e849fa03e5892eea0e0b5dadde1a98a:
target-xtensa: fix gdb register map construction (2015-07-06 13:25:12 +0300)
Xtensa fixes:
-
On 3 July 2015 at 09:22, Mark Cave-Ayland wrote:
> On 19/05/15 21:29, Richard Henderson wrote:
>
>> And do not issue an error_report in that case.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> hw/virtio/virtio-pci.c | 15 ++-
>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>
Am 06.07.2015 um 11:44 schrieb Chun Yan Liu:
While testing with a 1GB VHD file created on win7, found that the VHD file
size reported on Windows is different from that is reported by qemu-img
info or within a Linux KVM guest.
Created a dynamic VHD file on win7, on Windows, it is reported 1024MB
On Mon, Jul 06, 2015 at 10:06:50AM +0800, Hong Bo Li wrote:
>
>
> On 7/5/2015 2:25, Michael S. Tsirkin wrote:
> >On Fri, Jul 03, 2015 at 07:09:59PM +0800, Hong Bo Li wrote:
> >>>But I would like to note that pci device drivers require driver handshake
> >>>before device goes away.
> >>>IIUC s390
On 06/07/2015 11:59, zhanghailiang wrote:
>
>
> Besides, the follow is the cpus message got from host.
> 80FF72F5-FF6D-E411-A8C8-00821800:/home/fsp/hrg # virsh
> qemu-monitor-command instance-000
> * CPU #0: pc=0x7f64160c683d thread_id=68570
> CPU #1: pc=0x810301f1 (halted
On Sun, 5 Jul 2015 23:14:56 -0700
Serge Vakulenko wrote:
> This file implements a platform for Microchip PIC32MX7 microcontroller,
> with three boards (machine types) supported:
>
> pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-16 board
> pic32mx7-max32 PIC32MX7 micr
On 04/07/2015 03:12, Alexey Kardashevskiy wrote:
>>
>>> One step back :) Whole dance is what here? There are:
>>> 1) del+set_size(0)
>>> 2) set_size(not zero)+add
>>
>> Then no need for begin/commit. :)
>
> I got a new problem here - set_size(0) + set_size(not 0) do not invoke
> region_del/regio
On Mon, Jul 06, 2015 at 12:11:10PM +1000, Alexey Kardashevskiy wrote:
> This adds support for Dynamic DMA Windows (DDW) option defined by
> the SPAPR specification which allows to have additional DMA window(s)
>
> This implements DDW for emulated and VFIO devices. As all TCE root regions
> are map
On Mon, Jul 06, 2015 at 12:11:01PM +1000, Alexey Kardashevskiy wrote:
> Currently TCE tables are created once at start and their size never
> changes. We are going to change that by introducing a Dynamic DMA windows
> support where DMA configuration may change during the guest execution.
>
> This
On Mon, Jul 06, 2015 at 10:53:47AM +0200, Alexander Graf wrote:
> On 07/03/15 09:18, David Gibson wrote:
> >On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
> >>Current PPC code relies on -mem-path being used in order for
> >>hugepage support to be detected. With the introduction of
>
On Mon, Jul 06, 2015 at 12:10:56PM +1000, Alexey Kardashevskiy wrote:
>
> (cut-n-paste from kernel patchset)
>
> Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
> where devices are allowed to do DMA. These ranges are called DMA windows.
> By default, there is a single
On Mon, Jul 06, 2015 at 12:11:06PM +1000, Alexey Kardashevskiy wrote:
> sPAPR IOMMU is managing two copies of an TCE table:
> 1) a guest view of the table - this is what emulated devices use and
> this is where H_GET_TCE reads from;
> 2) a hardware TCE table - only present if there is at least one
On Mon, Jul 06, 2015 at 12:11:08PM +1000, Alexey Kardashevskiy wrote:
> On systems with guest visible IOMMU, adding a new memory region onto
> PCI bus calls vfio_listener_region_add() for every DMA window. This
> installs a notifier for IOMMU memory regions. The notifier is supposed
> to be removed
On 06/07/2015 04:10, Alexey Kardashevskiy wrote:
> This updates linux-headers against master 4.2-rc1 (commit
> d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754). This is the result of
> ./scripts/update-linux-headers.sh work.
>
> Cc: Paolo Bonzini
> Cc: Michael S. Tsirkin
> Signed-off-by: Alexey Karda
Jun Koi writes:
> On Sat, Jul 4, 2015 at 1:12 AM, Peter Maydell
> wrote:
> On 3 July 2015 at 18:10, Jun Koi wrote:
>> On Sat, Jul 4, 2015 at 1:06 AM, Peter Maydell
>> wrote:
>>> On 3 July 2015 at 18:02, Jun Koi wrote:
>>> > If this is true, then what if this TB is running infinitely, and
On 07/06/2015 09:06 PM, David Gibson wrote:
On Mon, Jul 06, 2015 at 12:11:10PM +1000, Alexey Kardashevskiy wrote:
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO dev
On Mon, Jul 6, 2015 at 10:57 AM, Fam Zheng wrote:
> On Mon, 07/06 10:45, Max Filippov wrote:
>> On Mon, Jul 6, 2015 at 10:36 AM, Fam Zheng wrote:
>> > On Mon, 07/06 10:27, Max Filippov wrote:
>> >> On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng wrote:
>> >> > On Sat, 07/04 10:47, Max Filippov wrote:
On 07/06/2015 09:43 AM, Paolo Bonzini wrote:
On 05/07/2015 23:08, Peter Crosthwaite wrote:
There was a complicated subtractive arithmetic for determining the
padding on the CPUTLBEntry structure. Simplify this with a union.
Signed-off-by: Peter Crosthwaite
---
include/exec/cpu-defs.h | 23
On 07/05/2015 09:50 PM, Peter Crosthwaite wrote:
It does not work in multi-arch as it requires the CPU specific
TARGET_VIRT_ADDR_SPACE_BITS global define. Just use the generic
version that does no masking. Targets should be responsible for
passing in a sane virtual address.
Signed-off-by: Peter
On 07/05/2015 09:48 PM, Peter Crosthwaite wrote:
Ping!
If this or orphaned, I'd like to send the PULL on the H-freeze.
Didn't all this get reviewed? I thought it did...
r~
Regards,
Peter
On Tue, Jun 23, 2015 at 8:57 PM, Peter Crosthwaite
wrote:
These two functions are mostly trying to
Am 06.07.2015 um 13:44 schrieb Richard Henderson:
> On 07/05/2015 09:48 PM, Peter Crosthwaite wrote:
>> Ping!
>>
>> If this or orphaned, I'd like to send the PULL on the H-freeze.
>
> Didn't all this get reviewed? I thought it did...
If everything is reviewed I could take it for my CPU pull late
On 07/06/15 13:09, David Gibson wrote:
On Mon, Jul 06, 2015 at 10:53:47AM +0200, Alexander Graf wrote:
On 07/03/15 09:18, David Gibson wrote:
On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
Current PPC code relies on -mem-path being used in order for
hugepage support to be detect
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