On 2015-07-05 20:31, Serge Vakulenko wrote:
> On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
> <serge.vakule...@gmail.com> wrote:
> > On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno <aurel...@aurel32.net> wrote:
> >> On 2015-06-30 21:12, Serge Vakulenko wrote:
> >>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> >>> index c476166..ab830ee 100644
> >>> --- a/target-mips/cpu.h
> >>> +++ b/target-mips/cpu.h
> >>> @@ -664,7 +669,9 @@ static inline int
> >>> cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
> >>> if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> >>> /* A MIPS configured with a vectorizing external interrupt
> >>> controller
> >>> will feed a vector into the Cause pending lines. The core
> >>> treats
> >>> - the status lines as a vector level, not as indiviual masks.
> >>> */
> >>> + the status lines as a vector level, not as individual masks.
> >>> */
> >>> + pending >>= CP0Ca_IP + 2;
> >>> + status >>= CP0Ca_IP + 2;
> >>> r = pending > status;
> >>
> >> I don't think it's needed. As the pending and status field have been
> >> masked above, we don't need to shift them to do the comparison.
>
> This is not true. The values still need to be shifted to get rid of
> soft interrupt bits, otherwise the comparison becomes incorrect.
It means we need to have a different mask with the internal interrupt
controller and with the external one. I therefore think it's better to
do the masking differently. For that you can add a CP0Ca_RIPL_mask
constant and use it for the VEIC case, and move the current masking in
the non VEIC case.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
