From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination with v7
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Merged VBAR and VBAR_EL1 reginfo
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Globally replace Aarch# with AArch#
---
target-arm/cpu.h | 25 -
target-arm/helper.c
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9 +
On 9 October 2014 14:00, wrote:
> From: KONRAD Frederic
>
> This removes num_irq parameter from gic_init_irqs_and_distributor as it is not
> used.
>
> Signed-off-by: KONRAD Frederic
> ---
Thanks, applied to target-arm.next.
-- PMM
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Consolidate SCTLR and SCTLR_EL1 reginfo entries
---
hw/arm/pxa2xx.c
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Switch to use distinct CPREG secure flags.
- Merged CSSELR and
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4d9f6f8..64208bc 100644
--- a/targe
On 10/10/2014 02:16 AM, Magnus Reftel wrote:
> On Thu, Oct 9, 2014 at 11:30 PM, Eric Blake wrote:
>> On 10/09/2014 01:12 PM, Magnus Reftel wrote:
>>> +if (parse_uint(arg, &seed, &end, 0) != 0 || *end != 0 || seed >
>>> UINT_MAX) {
>>
>> Slightly shorter as:
>>
>> if (parse_uint_full(arg, &see
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
can't read snapshot volume of vhd, and can't support other storage
features of vhd file.
This patch add read parent information in function "vpc_open", read
bitmap in "vpc_read", and change bitmap in "vpc_write".
Signed-off-by: Xi
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
On 10/10/2014 05:39 AM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> This patch-pair adds the QEMUSizedBuffer based in-memory QEMUFile
> written by Stefan Berger and Joel Schopp. I've made some
> fixes and modified the existing test-vmstate to use it for some test c
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 inser
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Switch to use distinct CPREG secure flags
v4 -> v
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
---
target-arm/cpu.h| 12 +++-
target-arm/helper.c | 8 +---
2 files changed, 16 insertions(+), 4 deletions(-)
dif
On 14 September 2014 21:29, Max Filippov wrote:
> On Sun, Sep 14, 2014 at 12:36 PM, Peter Maydell
> wrote:
>> The XtensaConfig structs will be defined but not used if they are
>> for the opposite endianness from that of the binary being built;
>> keep the compiler from complaining about this by m
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8ba72ed..fa12602 10064
On 10 October 2014 16:19, Ard Biesheuvel wrote:
> Move the registering of CPU reset handlers to before the point where
> we leave the function in the -bios (not -kernel) case, so CPU reset
> works correctly with -bios as well.
>
> Signed-off-by: Ard Biesheuvel
> ---
Applied to target-arm.next,
On 09/10/2014 11:05 PM, Fam Zheng wrote:
> Signed-off-by: Fam Zheng
> ---
> blockdev.c | 48
> qapi-schema.json | 3 +++
> 2 files changed, 51 insertions(+)
>
> +++ b/qapi-schema.json
> @@ -1251,11 +1251,14 @@
> #
> # A discriminated rec
On 08/26/2014 03:36 PM, Max Reitz wrote:
> Add a test for qcow2's fast bdrv_make_empty implementation on images
> without internal snapshots.
This test may need to be limited to compat=1.1 files.
>
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/098 | 78
> ++
The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.
To avoid this regressing the behaviou
Xorg server hangs when using xfig and typing a text with space:
#0 qxl_wait_for_io_command (qxl=) at qxl_io.c:47
#1 0x7f826a49a299 in qxl_download_box (surface=0x221d030, x1=231, y1=259,
x2=, y2=) at qxl_surface.c:143
while (!(ram_header->int_pending & QXL_INTERRUPT_IO_CMD))
On Fri, Oct 10, 2014 at 8:24 PM, Peter Maydell wrote:
> On 14 September 2014 21:29, Max Filippov wrote:
>> On Sun, Sep 14, 2014 at 12:36 PM, Peter Maydell
>> wrote:
>>> The XtensaConfig structs will be defined but not used if they are
>>> for the opposite endianness from that of the binary being
On 10/10/2014 12:49 PM, Peter Maydell wrote:
> The DZP bit in the DCZID system register should be set if
> the control bits which prohibit use of the DC ZVA instruction
> have been set (it stands for Data Zero Prohibited). However
> we had the sense of the test inverted; fix this so that the
> bit
This is a rather specific use case. Note that linux can use
partitionless diskspace just fine, and depending on the bootmanager, one
can use single partition as a virtual disk to boot linux too (syslinux
supports this mode for one). Implementing this feature in qemu does not
make much sense to me
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.
Signed-off-by: Peter Maydell
---
target-arm/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
The ARM ARM requires that the FPINST and FPINST2 VFP control
registers are not accessible to code at EL0. We were already
correctly implementing this for reads of these registers; add
the missing check for the write code path.
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 3 +++
1 fi
411a696be1a7272b1c:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2014-10-09 15:09:05 +0100)
>
> are available in the git repository at:
>
>
> git://github.com/cohuck/qemu.git tags/s390x-20141010
>
> for you to fe
The local variable 'ac' in send_qmp_error_event() is declared with the
wrong type, which causes clang to complain when it is initialized
and again when it is used:
block.c:3655:20: warning: implicit conversion from enumeration type 'enum
IoOperationType' to different enumeration type 'BlockErrorA
On 10/10/2014 01:33 PM, Peter Maydell wrote:
> The local variable 'ac' in send_qmp_error_event() is declared with the
> wrong type, which causes clang to complain when it is initialized
> and again when it is used:
>
> block.c:3655:20: warning: implicit conversion from enumeration type 'enum
> Io
Following cleanup of the vga device code in commit d2e043a8041,
the arrays dmask4 and dmask16 are now unused. gcc doesn't warn
about this, but clang does; remove them.
Signed-off-by: Peter Maydell
---
hw/display/vga.c | 26 --
1 file changed, 26 deletions(-)
diff --git a
On Fri, 2014-10-10 at 20:44 +0100, Peter Maydell wrote:
> Following cleanup of the vga device code in commit d2e043a8041,
> the arrays dmask4 and dmask16 are now unused. gcc doesn't warn
> about this, but clang does; remove them.
Ah right, I missed those, thanks.
> Signed-off-by: Peter Maydell
>
Hello,
I am trying to add a block device dynamically using qmp and are having some
issues.
After successfully adding the block device using "blockdev-add" and verifying
that it has been added using "query-block", I am unable to see the block device
in the VM under /dev/sdXX
I am using ubuntu1
On 2014/10/11 0:17, Xiaodong Gong wrote:
> Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
> can't read snapshot volume of vhd, and can't support other storage
> features of vhd file.
>
> This patch add read parent information in function "vpc_open", read
> bitmap in "vpc_read"
kvm.git + qemu.git:da01e614_b6011bd8
test on Ivytown_EP
kernel version: 3.17.0
when create guest with bridge, and the bridge network driver is virtio, the
guest can get ip.
the bug cannot reproduce.
** Changed in: qemu
Status: New => Fix Released
--
You received this bug notification bec
From: Gonglei
The caller of qemu_vfree() maybe not check whether parameter
ptr pointer is NULL or not, such as vpc_open().
Using g_free() is more safe.
Signed-off-by: Gonglei
---
util/oslib-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/oslib-posix.c b/util/os
On 2014/10/11 10:54, arei.gong...@huawei.com wrote:
From: Gonglei
The caller of qemu_vfree() maybe not check whether parameter
ptr pointer is NULL or not, such as vpc_open().
Using g_free() is more safe.
It seems that free(NULL) is harmless.
From section 7.20.3.2/2 of the C99 standard:
The
On 2014/10/11 11:10, Zhanghailiang wrote:
> On 2014/10/11 10:54, arei.gong...@huawei.com wrote:
>> From: Gonglei
>>
>> The caller of qemu_vfree() maybe not check whether parameter
>> ptr pointer is NULL or not, such as vpc_open().
>> Using g_free() is more safe.
>>
>
> It seems that free(NULL) i
On 10/10/2014 08:54 PM, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> The caller of qemu_vfree() maybe not check whether parameter
> ptr pointer is NULL or not, such as vpc_open().
> Using g_free() is more safe.
NACK. g_free is only safe for pointers allocated by g_malloc.
qemu_vfree is fo
On 10/10/2014 09:21 PM, Gonglei wrote:
>
> Actually, I had noted that C standard says it is a no-operation.
> But that doesn't mean that every C-library handles it like that.
EVERY libc that is C89 compliant handles it like that. The last
platform that failed on free(NULL) was SunOS 4, which is
On 2014/10/11 11:26, Eric Blake wrote:
> On 10/10/2014 09:21 PM, Gonglei wrote:
>
>>
>> Actually, I had noted that C standard says it is a no-operation.
>> But that doesn't mean that every C-library handles it like that.
>
> EVERY libc that is C89 compliant handles it like that. The last
> plat
On 10/10/2014 09:32 PM, Gonglei wrote:
>>> Actually, I had noted that C standard says it is a no-operation.
>>> But that doesn't mean that every C-library handles it like that.
>>
>> EVERY libc that is C89 compliant handles it like that. The last
>> platform that failed on free(NULL) was SunOS 4,
On 2014/10/11 11:44, Eric Blake wrote:
> On 10/10/2014 09:32 PM, Gonglei wrote:
>
Actually, I had noted that C standard says it is a no-operation.
But that doesn't mean that every C-library handles it like that.
>>>
>>> EVERY libc that is C89 compliant handles it like that. The last
>>
Hi all,
When i try to passthrough BCM5719 Gigabit Ethernet to guest using the qemu
master branch, it aborted,
and show kvm_set_phys_mem:error registering slot:Bad Address.
qemu command:
#./qemu/qemu/x86_64-softmmu/qemu-system-x86_64 --enable-kvm -smp 4 -m 4096 -vnc
:99 -device virtio-scsi-pci,
On Fri, 10/10 16:52, Ken Chiang wrote:
> Hello,
>
> I am trying to add a block device dynamically using qmp and are having some
> issues.
>
> After successfully adding the block device using "blockdev-add" and verifying
> that it has been added using "query-block", I am unable to see the block
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