Hi all,
Some news on that point.
After a discussion with Paul Brook, Thiemo Seufer and Ralf Baechle on
IRC yesterday, we got convinced that the current IRQ handling is not
correct.
The hardware interrupt is currently deasserted by the CPU itself (in
cpu-exec.c). It should be deasserted by the in
On Tue, 23 Jan 2007, Aurelien Jarno wrote:
> There is currently a bug concerning the IRQ acknowlege on the MIPS
> system emulation. It concerns both the QEMU and Malta boards, though it
> is only detectable with a 2.4 kernel and thus on the Malta board. The
> symptom is a storm of "We got a spurio
On Mon, Jan 22, 2007 at 11:55:11AM +0100, Aurelien Jarno wrote:
> Carlo Marcelo Arenas Belon a écrit :
> >
> > The following patch moves the initialization of bm->cur_addr to match
> > FreeBSD behavior while being also compatible with all other guests
> >
the following snippet kept the initiali
Greetings,
the following patch moves the initialization for bm->cur_addr from the
ide_dma_start function to bmdma_addr_writel, so that it is set in sync
with the call to set the destination address for DMA (bm->addr) and to
avoid timeouts in guests that set this address after they have called
t
"Aurelien Jarno" <[EMAIL PROTECTED]> wrote:
Then after playing with the current code, I am sure we are missing a
simple interrupt controller for the MIPS CPU. It supports 6 hardware
interrupts (IP2 to IP7) and we are using two of them in the current
emulation: one for the i8259a and the other fo
> It should be good to have a well-defined modular IRQ routing
> architecture in the Qemu.
We've got most of one for the ARM targets (see hw/arm_pic.h). This file
contains both the target independent bits and the ARM specific bits for
emulating the CPU IRQ/FIQ pins.
Annother possibility to abst
hi
with newer kernel-headers, i get the following compile error:
gcc-3.3 -Wall -O2 -g -fno-strict-aliasing -fomit-frame-pointer -I.
-I.. -I/var/tmp/fst/src/qemu-0.8.2/target-i386
-I/var/tmp/fst/src/qemu-0.8.2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64
-D_LARGEFILE_SOURCE -I/var/tmp/fst/src/qemu-0.8.2/f
Hi,
On Tue, 23 Jan 2007, VMiklos wrote:
> /var/tmp/fst/src/qemu-0.8.2/usb-linux.c:29:28: linux/compiler.h: No
> such file or directory
> make[1]: *** [usb-linux.o] Error 1
> make[1]: Leaving directory `/var/tmp/fst/src/qemu-0.8.2/i386-softmmu'
> make: *** [subdir-i386-softmmu] Error 2
>
> is thi
On Tue, 2007-01-23 at 17:03 +0100, VMiklos wrote:
> hi
>
> with newer kernel-headers, i get the following compile error:
> gcc-3.3 -Wall -O2 -g -fno-strict-aliasing -fomit-frame-pointer -I.
> -I.. -I/var/tmp/fst/src/qemu-0.8.2/target-i386
> -I/var/tmp/fst/src/qemu-0.8.2 -D_GNU_SOURCE -D_FILE_OFFSE
Alexander Voropay a écrit :
> "Aurelien Jarno" <[EMAIL PROTECTED]> wrote:
>
>> Then after playing with the current code, I am sure we are missing a
>> simple interrupt controller for the MIPS CPU. It supports 6 hardware
>> interrupts (IP2 to IP7) and we are using two of them in the current
>> emul
Hi all,
Please find below a patch to fix the IRQ issue on the MIPS platform. I
have tested it on both 2.4 and 2.6 kernel and it works fine.
Here are a few comments on the patch to understand how it works.
- The CPU hardware interrupt (CPU_INTERRUPT_HARD) is not deasserted by
the CPU anymore, b
On Tue, Jan 23, 2007 at 07:42:20PM +0100, Aurelien Jarno wrote:
> Hi all,
>
> Please find below a patch to fix the IRQ issue on the MIPS platform. I
> have tested it on both 2.4 and 2.6 kernel and it works fine.
>
Here is an updated patch including the comments from Paul Brook via IRC.
Thanks Pa
Paul Brook wrote:
It should be good to have a well-defined modular IRQ routing
architecture in the Qemu.
We've got most of one for the ARM targets (see hw/arm_pic.h). This file
contains both the target independent bits and the ARM specific bits for
emulating the CPU IRQ/FIQ pins.
Annother
Good. I prefer this implementation to the current one!
Fabrice.
Aurelien Jarno wrote:
On Tue, Jan 23, 2007 at 07:42:20PM +0100, Aurelien Jarno wrote:
Hi all,
Please find below a patch to fix the IRQ issue on the MIPS platform. I
have tested it on both 2.4 and 2.6 kernel and it works fine.
The attached patch adds SMBus host support to the emulated PIIX4 power
management device (acpi.c), and adds an emulated serial EEPROM device
accessible via the SMBus interface.
I tried to follow the Intel 82371AB spec for the SMBus support; the
interface should be generic enough to implement a va
Ed Swierk wrote:
The attached patch adds SMBus host support to the emulated PIIX4 power
management device (acpi.c), and adds an emulated serial EEPROM device
accessible via the SMBus interface.
I tried to follow the Intel 82371AB spec for the SMBus support; the
interface should be generic enough
On 1/23/07, Fabrice Bellard <[EMAIL PROTECTED]> wrote:
OK, but avoid using mmap() in the device code. Moreover, files in the
BIOS directory are not writable.
OK. Would it be better to do the following:
- add a command-line option -seeprom that sets the file to use as
backing store for the smbu
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/01/23 22:45:22
Modified files:
target-mips: cpu.h op.c op_helper.c translate.c
Log message:
Implementing dmfc/dmtc.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.
Here's a revised patch with the mmap stuff removed. I'll refine the
persistence support, but in the meantime the EEPROM device is usable
even if it forgets its contents when qemu exits.
--Ed
Index: qemu-0.8.2/hw/acpi.c
===
--- qemu-0
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/01/24 01:12:42
Modified files:
hw : ide.c
Log message:
Fix DMA timeouts on FreeBSD, by Carlo Marcelo Arenas Belon.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ide.c?
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/01/24 01:47:51
Modified files:
. : Makefile.target cpu-exec.c vl.h
hw : gt64xxx.c i8259.c mips_malta.c mips_r4k.c
mips_timer.c
targe
Windows 2000 boots and PC Wizard 2007 displays the following
information under the Mainboard category:
> SMBus/i2c Bus : Yes
>> General Information
Device : 82371AB/EB/MB PIIX4/E/M Power Management Controller
Revision : 0
Frequency : 16 KHz
Address : 0xB100
>> Device
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