Hi all, Some news on that point.
After a discussion with Paul Brook, Thiemo Seufer and Ralf Baechle on IRC yesterday, we got convinced that the current IRQ handling is not correct. The hardware interrupt is currently deasserted by the CPU itself (in cpu-exec.c). It should be deasserted by the interrupt controller (the i8259a in our case), so that pending interrupts are not missed. This is wrong for MIPS, but also for x86_64 and PowerPC. ARM is correctly implemented though. Then after playing with the current code, I am sure we are missing a simple interrupt controller for the MIPS CPU. It supports 6 hardware interrupts (IP2 to IP7) and we are using two of them in the current emulation: one for the i8259a and the other for the timer. In both case the current code assert and deassert a CPU_INTERRUPT_HARD. The interrupt controller should assert and deassert the CPU_INTERRUPT_HARD upon the contents of the CP0 cause and CP0 status (ie mask) registers. Currently we are totally ignoring that interrupts can be masked and leave this task to the operating system. I will try to write the missing code this night. Bye, Aurelien -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [EMAIL PROTECTED] | [EMAIL PROTECTED] `- people.debian.org/~aurel32 | www.aurel32.net _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
