On Tue, 23 Jan 2007, Aurelien Jarno wrote: > There is currently a bug concerning the IRQ acknowlege on the MIPS > system emulation. It concerns both the QEMU and Malta boards, though it > is only detectable with a 2.4 kernel and thus on the Malta board. The > symptom is a storm of "We got a spurious interrupt from PIIX4." > > This is due to the kernel requesting the interrupt number from the > i8259A where no interrupt is waiting. In such a case the i8259A answers > by an IRQ 7. > > When an hardware interrupt occurs, the i8259A memorizes the interrupt > and sends it to the MIPS CPU. This is done via the pic_irq_request() > function. The result is that the bit 10 of the CP0 Cause register is > set to one (interrupt 2). But when the interrupt is finished, the i8259a > registers IRR and ISR are cleared, but not the CP0 Cause register. The > CPU always thinks there is an interrupt to serve, which is wrong.
I can confirm this issue. For our (custom) OS I worked around this by manualy clearing CP0 Cause (even though I think I shouldn't be allowed to do that since CP0:IP[7-2] are read-only, but that's another story... ;-) > Does anyone has an idea of a sane implementation for that? It seems > only the MIPS platform has to clear a register of the CPU when an > interrupt is finished. What about passing another hook to pic_init which, if set, would be called when no more interrupts are pending? Would that be too specific this problem to be an acceptable solution? Regards, Marius -- Marius Groeger <[EMAIL PROTECTED]> SYSGO AG Embedded and Real-Time Software Voice: +49 6136 9948 0 FAX: +49 6136 9948 10 www.sysgo.com | www.elinos.com | www.osek.de | www.pikeos.com _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
