Re: [PATCH v2 043/101] target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1

On Sun, 22 Jun 2025 at 01:00, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sve.c | 10 ++ > target/arm/tcg/sve.decode | 8 +++- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/target/arm/tcg/translate-sve.c b

Re: FreeBSD 14.1 aarch64 iso URL is down

On Tue, Jun 24, 2025 at 11:16 AM Stefan Hajnoczi wrote: > > On Tue, Jun 24, 2025 at 12:28 PM Warner Losh wrote: > > > > On Tue, Jun 24, 2025 at 10:02 AM Thomas Huth wrote: > > > > > > On 22/06/2025 03.46, Warner Losh wrote: > > > > > > > > > > > > On Sat, Jun 21, 2025, 6:01 PM Stefan Hajnoczi >

Re: [PULL 00/11] tcg patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v6 0/3] Add SCLP event type CPI

On 16/06/2025 16.01, Shalini Chellathurai Saroja wrote: Implement the Service-Call Logical Processor (SCLP) event type Control-Program Identification (CPI) in QEMU. Changed since v5: - Add identifiers as class properties instead of object properties - Add description for all the class properties

Re: FreeBSD 14.1 aarch64 iso URL is down

On Tue, Jun 24, 2025 at 10:02 AM Thomas Huth wrote: > > On 22/06/2025 03.46, Warner Losh wrote: > > > > > > On Sat, Jun 21, 2025, 6:01 PM Stefan Hajnoczi > > wrote: > > > > On Sat, Jun 21, 2025 at 7:59 PM Stefan Hajnoczi > > wrote: >

Re: [PATCH v3 16/29] hw/i386/acpi-build: Move aml_pci_edsm to a generic place

Hi Igor, Jonathan, On 6/20/25 2:27 PM, Igor Mammedov wrote: > On Fri, 20 Jun 2025 10:19:36 +0100 > Jonathan Cameron wrote: > >> On Mon, 16 Jun 2025 11:46:45 +0200 >> Eric Auger wrote: >> >>> Move aml_pci_edsm to pci-bridge.c since we want to reuse that for >>> ARM and acpi-index support. >>> >>>

Re: [PATCH v2 2/3] target/arm: Fix sve_access_check for SME

On 6/24/25 06:58, Peter Maydell wrote: +switch (dc_isar_feature(aa64_sme, s)) { +case true: Why this rather than if (dc_isar_feature(aa64_sme, s)) { ? +if (s->pstate_sm) { +ret = sme_enabled_check(s); +} else if (!dc_isar_feature(aa64_sve, s)) { +

Re: [PATCH v3 19/29] hw/arm/virt: Pass the bus on the ged creation

Hi Jonathan, On 6/20/25 11:38 AM, Jonathan Cameron wrote: > On Mon, 16 Jun 2025 11:46:48 +0200 > Eric Auger wrote: > >> The bus will be needed on ged realize for acpi pci hp setup. >> >> Signed-off-by: Eric Auger > I guess doing this in separate patches for previous and this one > maybe makes it

Re: [PATCH 1/3] memory: reintroduce BQL-free fine-grained PIO/MMIO

On Tue, 24 Jun 2025 09:07:11 +0200 Gerd Hoffmann wrote: > Hi, > > > Gerd mentioned this in the relevant bz: > > > > Note: root cause for the initrd issue noted in comment 5 is seabios > > running into problems with ehci -> io errors -> corrupted initrd. > > Sometimes i

Re: [PATCH v3 06/11] migration: Rename save_live_complete_precopy to save_complete

On Tue, Jun 24, 2025 at 04:36:39PM +0200, Juraj Marcin wrote: [...] > There are still mentions of 'save_live_complete_precopy' in: > > include/migration/register.h:100 > * parallel with @save_live_complete_precopy handlers. > docs/devel/migration/vfio.rst:78 > * A ``save_

Re: [PATCH] vfio: add license tag to some files

On 6/24/25 11:19, John Levon wrote: On Tue, Jun 24, 2025 at 10:05:44AM +0100, Daniel P. Berrangé wrote: On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: + Daniel On 6/23/25 11:30, John Levon wrote: Add SPDX-License-Identifier to some files missing it in hw/vfio/. Signed-off

Re: [PATCH v2 042/101] target/arm: Tighten USDOT (vectors) decode

On 6/24/25 03:13, Peter Maydell wrote: -USDOT_ 01000100 .. 0 . 011 110 . . @rda_rn_rm +USDOT__4s 01000100 10 0 . 011 110 . . @rda_rn_rm_e0 This sets esz to 0, when it used to be 2. The helper function looks like it looks at the simd_oprsz() so I think th

Re: [PULL 24/24] i386/tdx: handle TDG.VP.VMCALL

On 6/24/25 17:08, Daniel P. Berrangé wrote: On Tue, Jun 24, 2025 at 11:03:19AM -0400, Stefan Hajnoczi wrote: On Mon, Jun 23, 2025 at 4:37 PM Cédric Le Goater wrote: On 6/23/25 20:57, Stefan Hajnoczi wrote: On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé wrote: On Mon, Jun 23, 2025 at 0

Re: [PULL 24/24] i386/tdx: handle TDG.VP.VMCALL

On Mon, Jun 23, 2025 at 4:37 PM Cédric Le Goater wrote: > > On 6/23/25 20:57, Stefan Hajnoczi wrote: > > On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé > > wrote: > >> > >> On Mon, Jun 23, 2025 at 09:04:33AM -0400, Stefan Hajnoczi wrote: > >>> On Mon, Jun 23, 2025 at 4:04 AM Daniel P. Berran

Re: [PATCH v3 01/28] Add boot-certificates to s390-ccw-virtio machine type option

On 6/20/25 11:45 AM, Zhuoying Cai wrote: On 6/6/25 10:00 AM, Daniel P. Berrangé wrote: On Wed, Jun 04, 2025 at 05:56:29PM -0400, Zhuoying Cai wrote: Add boot-certificates as a parameter of s390-ccw-virtio machine type option. The `boot-certificates=/path/dir:/path/file` parameter is impleme

Re: [PATCH v2 3/3] target/arm: Fix 128-bit element ZIP, UZP, TRN

On Sun, 22 Jun 2025 at 22:36, Richard Henderson wrote: > > We missed the instructions UDEF when the vector size is too small. I think this part also applies to FMMLA_d and trans_LD1RO_zprr and trans_LD1RO_zprr ? We should also probably put something in so that if the user asks for a CPU with a m

Re: [PATCH v3 07/11] migration: qemu_savevm_complete*() helpers

On 2025-06-13 10:07, Peter Xu wrote: > Since we use the same save_complete() hook for both precopy and postcopy, > add a set of helpers to invoke the hook() to dedup the code. > > Signed-off-by: Peter Xu > --- Reviewed-by: Juraj Marcin

Re: [PATCH v3 06/11] migration: Rename save_live_complete_precopy to save_complete

Hi Peter, On 2025-06-13 10:07, Peter Xu wrote: > Now after merging the precopy and postcopy version of complete() hook, > rename the precopy version from save_live_complete_precopy() to > save_complete(). > > Dropping the "live" when at it, because it's in most cases not live when > happening (in

Re: [PATCH v2 034/101] target/arm: Implement SME2 FMLAL, BFMLAL

On Sun, 22 Jun 2025 at 00:55, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sme.c | 93 ++ > target/arm/tcg/sme.decode | 71 ++ > 2 files changed, 164 insertions(+) > > diff --git a/targ

Re: [PATCH v3 02/11] migration/hmp: Fix postcopy-blocktime per-vCPU results

On 2025-06-13 10:07, Peter Xu wrote: > Unfortunately, it was never correctly shown.. > > This is only found when I started to look into making the blocktime feature > more useful (so as to avoid using bpftrace, even though I'm not sure which > one will be harder to use..). > > So the old dump wou

Re: [PATCH] MAINTAINERS: add reviewers for some s390 areas

On 23/06/2025 18.00, Matthew Rosato wrote: To improve review coverage, assign additional people as reviewers for multiple s390 sections. Signed-off-by: Matthew Rosato --- MAINTAINERS | 12 1 file changed, 12 insertions(+) Thanks for your help, guys! I've queued the patch now

Re: [PATCH v2 2/3] target/arm: Fix sve_access_check for SME

On Sun, 22 Jun 2025 at 22:36, Richard Henderson wrote: > > Do not assume SME implies SVE. Ensure that the > non-streaming check is present along the SME path, > since it is not implied by sme_*_enabled_check. > > Cc: qemu-sta...@nongnu.org > Signed-off-by: Richard Henderson > --- > target/arm/t

Re: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE

2025-06-23T18:39:02-03:00, Daniel Henrique Barboza : > Hi Radim, > > It seems like this patch is breaking 'make check-functional': That is a nice command to know of, thanks! > 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT > 90.06s killed by signal 15 SIGTERM

Re: [PATCH 1/1] hw/s390x: Use preferred API call for IPLB chain write

On 6/24/25 2:27 AM, Thomas Huth wrote: On 23/06/2025 22.12, jro...@linux.ibm.com wrote: From: Jared Rossi Replace a recently introduced legacy API call with the preferred API call. fixes: 0927875 (hw/s390x: Build an IPLB for each boot device) Signed-off-by: Jared Rossi ---   hw/s390x/ip

Re: [PATCH] vfio: add license tag to some files

On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: > + Daniel > > On 6/23/25 11:30, John Levon wrote: > > Add SPDX-License-Identifier to some files missing it in hw/vfio/. > > > > Signed-off-by: John Levon > > --- > > hw/vfio/trace.h | 3 +++ > > hw/vfio/Kconfig | 2 +

Re: [PATCH v2 1/3] target/arm: Fix SME vs AdvSIMD exception priority

On Sun, 22 Jun 2025 at 22:36, Richard Henderson wrote: > > We failed to raise an exception when > sme_excp_el == 0 and fp_excp_el == 1. > > Cc: qemu-sta...@nongnu.org > Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks") > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translat

Re: [PATCH v6 2/3] hw/s390x: add Control-Program Identification to QOM

On 16/06/2025 16.01, Shalini Chellathurai Saroja wrote: Add Control-Program Identification (CPI) data to the QEMU Object Model (QOM), along with the timestamp in which the data was received as shown below. virsh # qemu-monitor-command vm --pretty '{"execute":"qom-list", "arguments":{"path":"/mac

Re: [PATCH v2 09/10] net: Add passt network backend

On 24/06/2025 10:16, Markus Armbruster wrote: Laurent Vivier writes: This commit introduces support for passt as a new network backend. passt is an unprivileged, user-mode networking solution that provides connectivity for virtual machines by launching an external helper process. The implemen

Re: [PATCH 1/3] memory: reintroduce BQL-free fine-grained PIO/MMIO

On Mon, 23 Jun 2025 09:36:05 -0400 Peter Xu wrote: > On Mon, Jun 23, 2025 at 02:51:46PM +0200, Igor Mammedov wrote: > > On Fri, 20 Jun 2025 12:53:06 -0400 > > Peter Xu wrote: > > > > > On Fri, Jun 20, 2025 at 05:14:16PM +0200, Igor Mammedov wrote: > > > > This patch brings back Jan's idea [

Re: [PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

Hi, Gentle ping on this patch. Thanks, Jay Chang On Tue, Apr 1, 2025 at 6:34 PM Jay Chang wrote: > RISC-V Privileged Spec states: > "In harts with S-mode, the medeleg and mideleg registers must exist, and > setting a bit in medeleg or mideleg will delegate the corresponding trap > , when occur

Re: [PATCH] s390x: Fix leak in machine_set_loadparm

Thomas Huth writes: > On 12/05/2025 17.37, Fabiano Rosas wrote: >> Philippe Mathieu-Daudé writes: >> >>> On 12/5/25 16:07, Philippe Mathieu-Daudé wrote: On 9/5/25 19:49, Fabiano Rosas wrote: > ASAN spotted a leaking string in machine_set_loadparm(): >>> >>> What about ccw_device_set_lo

Re: [PATCH v2 09/10] net: Add passt network backend

On Tue, Jun 24, 2025 at 01:55:20PM +0200, Markus Armbruster wrote: > Laurent Vivier writes: > > > On 24/06/2025 10:16, Markus Armbruster wrote: > >> Laurent Vivier writes: > >> > >>> This commit introduces support for passt as a new network backend. > >>> passt is an unprivileged, user-mode net

RE: [PATCH v2 11/19] intel_iommu: Handle PASID entry adding

Hi Eric, >-Original Message- >From: Eric Auger > >Subject: Re: [PATCH v2 11/19] intel_iommu: Handle PASID entry adding > >Hi Zhenzhong, > >On 6/20/25 9:18 AM, Zhenzhong Duan wrote: >> When guest modifies a PASID entry, QEMU will capture the guest p

Re: [PATCH v2 044/101] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT

On Sun, 22 Jun 2025 at 00:54, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/helper-sme.h| 11 + > target/arm/tcg/sme_helper.c| 42 ++ > target/arm/tcg/translate-sme.c | 23 +++ > target/arm/tcg

Re: [PATCH v2 042/101] target/arm: Tighten USDOT (vectors) decode

On Sun, 22 Jun 2025 at 00:58, Richard Henderson wrote: > > Rename to USDOT__4s and force size=2 during decode. > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sve.c | 4 ++-- > target/arm/tcg/sve.decode | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > >

Re: [PATCH] vfio: add license tag to some files

On Mon, Jun 23, 2025 at 10:30:53AM +0100, John Levon wrote: > Add SPDX-License-Identifier to some files missing it in hw/vfio/. > > Signed-off-by: John Levon > --- > hw/vfio/trace.h | 3 +++ > hw/vfio/Kconfig | 2 ++ > hw/vfio/meson.build | 2 ++ > hw/vfio/trace-events | 2 ++ > 4 fil

Re: [PATCH 1/4] vfio/container: Fix SIGSEGV when open container file fails

On 6/23/25 12:22, Zhenzhong Duan wrote: When open /dev/vfio/vfio fails, SIGSEGV triggers because vfio_listener_unregister() doesn't support a NULL bcontainer pointer. Fixes: a1f267a7d4d9 ("vfio/container: reform vfio_container_connect cleanup") Signed-off-by: Zhenzhong Duan Reviewed-by: Cédr

Re: [PATCH] vfio: add license tag to some files

On Tue, Jun 24, 2025 at 11:41:11AM +0200, Philippe Mathieu-Daudé wrote: > On 24/6/25 11:05, Daniel P. Berrangé wrote: > > On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: > > > + Daniel > > > > > > On 6/23/25 11:30, John Levon wrote: > > > > Add SPDX-License-Identifier to some fil

Re: [PATCH] vfio: add license tag to some files

On 6/24/25 11:32, John Levon wrote: On Tue, Jun 24, 2025 at 11:27:57AM +0200, Cédric Le Goater wrote: On 6/24/25 11:19, John Levon wrote: On Tue, Jun 24, 2025 at 10:05:44AM +0100, Daniel P. Berrangé wrote: On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: + Daniel On 6/23/2

Re: [PATCH v2 041/101] target/arm: Rename SVE SDOT and UDOT patterns

On Sun, 22 Jun 2025 at 00:59, Richard Henderson wrote: > > Emphasize the 4-way nature of these dot products. > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sve.c | 12 ++-- > target/arm/tcg/sve.decode | 12 ++-- > 2 files changed, 12 insertions(+), 12

Re: [PATCH v2 040/101] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT

On Sun, 22 Jun 2025 at 00:58, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/helper.h| 8 > target/arm/tcg/translate-sme.c | 85 ++ > target/arm/tcg/vec_helper.c| 51 > target/arm/tcg/sme

Re: [PATCH 1/4] vfio/container: Fix SIGSEGV when open container file fails

On 6/23/25 12:22, Zhenzhong Duan wrote: When open /dev/vfio/vfio fails, SIGSEGV triggers because vfio_listener_unregister() doesn't support a NULL bcontainer pointer. Fixes: a1f267a7d4d9 ("vfio/container: reform vfio_container_connect cleanup") Signed-off-by: Zhenzhong Duan --- hw/vfio/contai

Re: [PATCH] vfio: add license tag to some files

On 6/23/25 11:30, John Levon wrote: Add SPDX-License-Identifier to some files missing it in hw/vfio/. Signed-off-by: John Levon Applied to vfio-next. Thanks, C.

Re: [PATCH v7 0/5] Enable shared device assignment

On 18.06.25 23:58, Peter Xu wrote: Hi, Chenyi, On Thu, Jun 12, 2025 at 04:27:41PM +0800, Chenyi Qiang wrote: Relationship with in-place conversion - In-place page conversion is the ongoing work to allow mmap() of guest_memfd to userspace so that both private

Re: [PATCH] vfio: add license tag to some files

On 6/24/25 11:41, John Levon wrote: On Tue, Jun 24, 2025 at 11:35:52AM +0200, Cédric Le Goater wrote: These files came from hw/vfio/ and were then modified so would carry the same license. Please let me know what you'd like me to do. Ah. Please consider them as new. These are infrastructure f

Re: [PATCH] vfio: add license tag to some files

On 24/6/25 11:05, Daniel P. Berrangé wrote: On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: + Daniel On 6/23/25 11:30, John Levon wrote: Add SPDX-License-Identifier to some files missing it in hw/vfio/. Signed-off-by: John Levon --- hw/vfio/trace.h | 3 +++ hw/vfi

Re: [PATCH] vfio: add license tag to some files

On Tue, Jun 24, 2025 at 11:27:57AM +0200, Cédric Le Goater wrote: > On 6/24/25 11:19, John Levon wrote: > > On Tue, Jun 24, 2025 at 10:05:44AM +0100, Daniel P. Berrangé wrote: > > > > > On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: > > > > + Daniel > > > > > > > > On 6/23/25

Re: [PATCH] vfio: add license tag to some files

On Tue, Jun 24, 2025 at 10:05:44AM +0100, Daniel P. Berrangé wrote: > On Tue, Jun 24, 2025 at 10:34:40AM +0200, Cédric Le Goater wrote: > > + Daniel > > > > On 6/23/25 11:30, John Levon wrote: > > > Add SPDX-License-Identifier to some files missing it in hw/vfio/. > > > > > > Signed-off-by: John

Re: [PATCH v5 1/3] Add support for emulation of CRC32 instructions

On Wed, Feb 26, 2025 at 05:03:04PM +, Aleksandar Rakic wrote: > From: Aleksandar Rakic > > Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. > Reuse zlib crc32() and Linux crc32c(). > > Enable CRC for mips64r6. > > Cherry-picked 4cc974938aee1588f852590509004e340c072940 >

Re: [Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls

On Mon, Jun 23, 2025 at 09:56:14AM -0700, Dongli Zhang wrote: > Date: Mon, 23 Jun 2025 09:56:14 -0700 > From: Dongli Zhang > Subject: [Regression] Re: [PULL 35/35] qom: reverse order of > instance_post_init calls > > This commit may broken the "vendor=" configura

Re: [PATCH v2 09/10] net: Add passt network backend

Laurent Vivier writes: > This commit introduces support for passt as a new network backend. > passt is an unprivileged, user-mode networking solution that provides > connectivity for virtual machines by launching an external helper process. > > The implementation reuses the generic stream data ha

Re: [PATCH v5 1/3] Add support for emulation of CRC32 instructions

HTEC Public Hi, > I confirm my "reviewed-by" for v5 1/3 (v5 is the same as the initial > one I reviewed, except tests are added). > Reviewed-by: Aleksandar Rikalo Can someone please commit this change? Thanks in advance! Kind regards, Aleksadar Rakic

Re: [PATCH 0/4] Docs: bump sphinx version to 6.2.1

John Snow writes: > This is a re-send of Akihiko Odaki's series, rebased and altered to cope > with the new QAPI static analysis tests now running on GitLab CI. Works fine for me on a Fedora 41 box (Sphinx 7.3.8) Tested-by: Markus Armbruster

Re: [PATCH] s390x: Fix leak in machine_set_loadparm

On 12/05/2025 17.37, Fabiano Rosas wrote: Philippe Mathieu-Daudé writes: On 12/5/25 16:07, Philippe Mathieu-Daudé wrote: On 9/5/25 19:49, Fabiano Rosas wrote: ASAN spotted a leaking string in machine_set_loadparm(): What about ccw_device_set_loadparm() in hw/s390x/ccw-device.c? Yep, tha

Re: [RFC v6 1/3] hw/misc/aspeed_otp: Add ASPEED OTP memory device model

On 6/24/25 04:22, Kane Chen wrote: From: Kane-Chen-AS Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provid

Re: [PATCH v2 06/12] python: upgrade to python3.9+ syntax

John Snow writes: > This patch is fully automated, using pymagic, isort and autoflake. > > Create a script named pymagic.sh: > > = > > pyupgrade --exit-zero-even-if-changed --keep-percent-format \ > --py39-plus "$@" > > autoflake -i "$@" > > isort --settings-file

Re: [PATCH] rust: log: implement io::Write

> +/// A RAII guard for QEMU's logging infrastructure. Creating the guard > +/// locks the log file, and dropping it (letting it go out of scope) unlocks > +/// the file. > +/// > +/// As long as the guard lives, it can be written to using > [`std::io::Write`]. > +/// > +/// The locking is recurs

Re: [RFC 01/10] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel

On Tue, May 27, 2025 at 05:56:07PM +0800, Ewan Hai wrote: > Date: Tue, 27 May 2025 17:56:07 +0800 > From: Ewan Hai > Subject: Re: [RFC 01/10] i386/cpu: Mark CPUID[0x8005] as reserved for > Intel > > > > On 5/27/25 5:15 PM, Zhao Liu wrote: > > > >

Re: [PATCH 1/3] memory: reintroduce BQL-free fine-grained PIO/MMIO

Hi, > Gerd mentioned this in the relevant bz: > > Note: root cause for the initrd issue noted in comment 5 is seabios > running into problems with ehci -> io errors -> corrupted initrd. > Sometimes it doesn't boot at all, probably in case the io errors > happen t

Re: [PATCH] rust: log: implement io::Write

> /// A macro to log messages conditionally based on a provided mask. > @@ -24,6 +96,8 @@ pub enum Log { > /// log level and, if so, formats and logs the message. It is the Rust > /// counterpart of the `qemu_log_mask()` macro in the C implementation. > /// > +/// Errors from writing to the log

Re: [RFC v6 3/3] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs

On 6/24/25 04:22, Kane Chen wrote: From: Kane-Chen-AS The has_otpmem attribute is enabled in the SBC subclasses for AST2600 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS --- hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_sbc.c | 2 ++ includ

Re: [RFC v6 2/3] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC

On 6/24/25 04:22, Kane Chen wrote: From: Kane-Chen-AS This patch connects the aspeed.otpmem device to the ASPEED Secure Boot Controller (SBC) model. It implements OTP memory access via the SBC's command interface and enables emulation of secure fuse programming flows. The following OTP command

Re: [PATCH 1/1] hw/s390x: Use preferred API call for IPLB chain write

On 23/06/2025 22.12, jro...@linux.ibm.com wrote: From: Jared Rossi Replace a recently introduced legacy API call with the preferred API call. fixes: 0927875 (hw/s390x: Build an IPLB for each boot device) Signed-off-by: Jared Rossi --- hw/s390x/ipl.c | 10 +- 1 file changed, 9 inser

Re: [PATCH v5 0/3] docs: define policy forbidding use of "AI" / LLM code generators

Alex Bennée writes: > Stefan Hajnoczi writes: > >> Any final comments before I merge this? > > It's well reviewed lets get it merged. Stefan, would you like a PR from me?

Re: [PULL 0/3] Memory/SDHCI/ParallelFlash patches for v7.2.0-rc0

On 21/12/23 22:19, Salvatore Bonaccorso wrote: Hi Philippe, On Wed, Nov 09, 2022 at 08:43:19AM +0100, Philippe Mathieu-Daudé wrote: On 8/11/22 21:57, Stefan Hajnoczi wrote: I've dropped the SDHCI CVE fix due to the CI failure. The rest of the commits are still in the staging tree and I plan t

RE: [PATCH v2 10/19] intel_iommu: Handle PASID entry removing and updating

Hi Eric, >-Original Message- >From: Eric Auger >Subject: Re: [PATCH v2 10/19] intel_iommu: Handle PASID entry removing and >updating > >Hi Zhenzhong, > >On 6/20/25 9:18 AM, Zhenzhong Duan wrote: >I would suggest: Handle PASID entry removal and update instead

RE: [PATCH v2 09/19] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked

>-Original Message- >From: Eric Auger >Subject: Re: [PATCH v2 09/19] intel_iommu: Introduce two helpers >vtd_as_from/to_iommu_pasid_locked > >Hi Zhenzhong, > >On 6/20/25 9:18 AM, Zhenzhong Duan wrote: >> PCI device supports two request types, Requests-with

Re: [PATCH 0/8] net: Add passt netdev backend

On Mon, Jun 23, 2025 at 4:10 PM Laurent Vivier wrote: > > On 23/06/2025 10:03, Jason Wang wrote: > > On Wed, Jun 18, 2025 at 4:39 PM Laurent Vivier wrote: > >> > >> This series introduces support for passt as a new network backend for > >> QEMU. > >> > >> passt is a modern, unprivileged, user-mod

Re: [PATCH 1/1] hw/s390x: Use preferred API call for IPLB chain write

On 6/23/25 13:12, jro...@linux.ibm.com wrote: From: Jared Rossi Replace a recently introduced legacy API call with the preferred API call. fixes: 0927875 (hw/s390x: Build an IPLB for each boot device) Signed-off-by: Jared Rossi --- hw/s390x/ipl.c | 10 +- 1 file changed, 9 insertio

Re: [PATCH v5 0/3] docs: define policy forbidding use of "AI" / LLM code generators

MU accepting patches) when a patch includes (or is >> derived from) AI generated code. >> >> By implication, I think that QEMU must (for now) explicitly decline >> to (knowingly) accept AI generated code. >> >> Perhaps a few years down the line the legal uncertainty will have >> reduced and we can re-evaluate this policy. >> >> Discuss... > > Any final comments before I merge this? It's well reviewed lets get it merged. -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH v2 16/20] amd_iommu: Set all address spaces to default translation mode on reset

On 6/13/25 4:46 AM, Sairaj Kodilkar wrote: On 5/31/2025 3:00 AM, Alejandro Jimenez wrote: Hey Sairaj, On 5/29/25 2:16 AM, Sairaj Kodilkar wrote: On 5/2/2025 7:46 AM, Alejandro Jimenez wrote: On reset, restore the default address translation mode for all the address spaces managed by th

Re: [PATCH v2 12/12] block/io_uring: use non-vectored read/write when possible

On Thu, Jun 19, 2025 at 08:08:28PM -0400, Stefan Hajnoczi wrote: > The io_uring_prep_readv2/writev2() man pages recommend using the > non-vectored read/write operations when possible for performance > reasons. > > I didn't measure a significant difference but it doesn't hurt to have > this optimiz

Re: virsh migrate fails when --copy-storage-all option is given!

CC: libvirt devel list Hi Kevin/Peter, Thank you so much for addressing this issue. I tried out few more things and here is my analysis: Even when I removed the readonly option from guest xml I was still seeing the issue in migration,In the qemu-commandline I could still see auto-read-only opti

Re: [PATCH v3 00/23] vfio-user client

On 6/23/25 18:09, Mark Cave-Ayland wrote: On 22/06/2025 13:57, Cédric Le Goater wrote: Hello, On 6/21/25 14:22, John Levon wrote: On Fri, Jun 20, 2025 at 10:32:10AM +0200, Cédric Le Goater wrote: Before merging, I would like to be able to experiment a minimum. Does a dummy device (server s

Re: [PATCH v2 034/101] target/arm: Implement SME2 FMLAL, BFMLAL

On Sun, 22 Jun 2025 at 00:55, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sme.c | 93 ++ > target/arm/tcg/sme.decode | 71 ++ > 2 files changed, 164 insertions(+) Reviewed-by: Peter

Re: [PULL 00/14] loongarch-to-apply queue

On Sun, Jun 22, 2025 at 10:39 PM gaosong wrote: > > 在 2025/6/21 上午2:12, Stefan Hajnoczi 写道: > > On Thu, Jun 19, 2025 at 11:11 PM gaosong wrote: > >> 在 2025/6/20 上午4:39, Stefan Hajnoczi 写道: > >>> gpg:using RSA key CA473C44D6A09C189A193FCD452B96852B268216 > >>> gpg: Can't check sign

Re: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE

Hi Radim, It seems like this patch is breaking 'make check-functional': 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT 90.06s killed by signal 15 SIGTERM Checking the logs I verified that the problem can be reproduced by running the 'spike' machine as follo

Re: [PATCH v2 068/101] target/arm: Implement SME2 SEL

On 6/21/25 16:50, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 25 + target/arm/tcg/sme.decode | 9 + 2 files changed, 34 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/transl

Re: [PATCH v2 08/12] aio-posix: gracefully handle io_uring_queue_init() failure

On Thu, Jun 19, 2025 at 08:08:24PM -0400, Stefan Hajnoczi wrote: > io_uring may not be available at runtime due to system policies (e.g. > the io_uring_disabled sysctl) or creation could fail due to file > descriptor resource limits. > > Handle failure scenarios as follows: > > If another AioCont

Re: [PATCH v2 004/101] tcg: Add base arguments to check_overlap_[234]

On 6/23/25 03:06, Peter Maydell wrote: On Sun, 22 Jun 2025 at 00:58, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 55 ++- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg

Re: [PATCH v2] linux-user: Add syscall dispatch support

On 6/4/25 05:00, Arusekk wrote: --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -865,3 +865,12 @@ void setup_sigtramp(abi_ulong sigtramp_page) unlock_user(tramp, sigtramp_page, 2 * 8); } #endif + +bool is_vdso_sigreturn(abi_ulong pc) +{ +#ifndef TARGET_X86_64 +if (p

Re: [PATCH v2 032/101] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors)

On Sun, 22 Jun 2025 at 00:56, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-sme.c | 31 +++ > target/arm/tcg/sme.decode | 20 > 2 files changed, 51 insertions(+) > > diff --git a/target/arm/tcg

Re: [PATCH 1/1] hw/s390x: Use preferred API call for IPLB chain write

On 6/23/25 4:12 PM, jro...@linux.ibm.com wrote: > From: Jared Rossi > > Replace a recently introduced legacy API call with the preferred API call. > > fixes: 0927875 (hw/s390x: Build an IPLB for each boot device) > Signed-off-by: Jared Rossi > --- > hw/s390x/ipl.c | 10 +- > 1 file cha

Re: [PULL 24/24] i386/tdx: handle TDG.VP.VMCALL

On 6/23/25 20:57, Stefan Hajnoczi wrote: On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé wrote: On Mon, Jun 23, 2025 at 09:04:33AM -0400, Stefan Hajnoczi wrote: On Mon, Jun 23, 2025 at 4:04 AM Daniel P. Berrangé wrote: On Mon, Jun 23, 2025 at 03:03:19PM +0800, Xiaoyao Li wrote: On 6/23

Re: page coloring and accelerated shadow paging

Hi All, On 6/23/25 08:47, Michael Clark wrote: [snipped] btw this started as a sketch in a gist in June 20th of last year: https://gist.github.com/michaeljclark/8f9b81e5e40488035dc252c9da3ecc2e # the glyph architecture current: https://metaparadigm.com/~mclark/glyph.pdf latest: https://metap

Re: virsh migrate fails when --copy-storage-all option is given!

On Mon, Jun 23, 2025 at 23:25:28 +0530, Anushree Mathur wrote: > CC: libvirt devel list > > Hi Kevin/Peter, > > Thank you so much for addressing this issue. I tried out few more things and > here is my analysis: > > Even when I removed the readonly option from guest xml I was still seeing the >

Re: [PATCH v2 01/12] aio-posix: fix race between io_uring CQE and AioHandler deletion

On Thu, Jun 19, 2025 at 08:08:17PM -0400, Stefan Hajnoczi wrote: > When an AioHandler is enqueued on ctx->submit_list for removal, the > fill_sq_ring() function will submit an io_uring POLL_REMOVE operation to > cancel the in-flight POLL_ADD operation. > > There is a race when another thread enque

Re: [PATCH v5 0/3] docs: define policy forbidding use of "AI" / LLM code generators

or > to assert compliance with the DCO terms (b) or (c) (which is a stated > pre-requisite for QEMU accepting patches) when a patch includes (or is > derived from) AI generated code. > > By implication, I think that QEMU must (for now) explicitly decline > to (knowingly) accept AI g

Re: [PATCH v2 039/101] target/arm: Remove helper_gvec_sudot_idx_4b

On 6/23/25 10:00, Peter Maydell wrote: On Sun, 22 Jun 2025 at 00:53, Richard Henderson wrote: Add gen_helper_gvec_sudot_idx_4b as an expander which swaps arguments and uses helper_gvec_usdot_idx_4b. Signed-off-by: Richard Henderson --- target/arm/tcg/helper.h | 2 -- target/arm/tcg/tr

Re: [PATCH v2] linux-user: fix resource leaks in gen-vdso

On 5/13/25 08:03, Daniel P. Berrangé wrote: There are a number of resource leaks in gen-vdso. In theory they are harmless because this is a short lived process, but when building QEMU with --extra-cflags="-fsanitize=address" problems ensure. The gen-vdso program is run as part of the build, and t

Re: [PATCH-for-10.1 v4 0/8] hw/arm: GIC 'its=off' ACPI table fixes

Hi Eric, On 6/17/25 10:26, Eric Auger wrote: Hi Gustavo, On 6/17/25 3:01 PM, Gustavo Romero wrote: Hi Eric, Thanks a lot for doing a first pass on this series! On 6/17/25 06:35, Eric Auger wrote: Hi Gustavo, On 6/16/25 3:18 PM, Gustavo Romero wrote: Since v2: - Fixed no_tcg_its inverted l

Re: [PULL 24/24] i386/tdx: handle TDG.VP.VMCALL

On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé wrote: > > On Mon, Jun 23, 2025 at 09:04:33AM -0400, Stefan Hajnoczi wrote: > > On Mon, Jun 23, 2025 at 4:04 AM Daniel P. Berrangé > > wrote: > > > > > > On Mon, Jun 23, 2025 at 03:03:19PM +0800, Xiaoyao Li wrote: > > > > On 6/23/2025 2:43 PM, C

Re: [PATCH v2 00/27] tcg/optimize: Track and use known 1's

Ping. On 6/3/25 01:08, Richard Henderson wrote: We already track and use known 0's; do the same for 1's. This actually simplifies some of the logical operations, where before required checking for a constant value. Changes for v2: - Some simplifications suggested by Paolo. - Merge affect

[Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls

This commit may broken the "vendor=" configuration. For instance, the hypervisor CPU vendor is AMD. I am going to use "-cpu Skylake-Server,vendor=GenuineIntel". Because of the commit, the vendor is still AMD. [root@vm ~]# cpuid -1 -l 0x0 CPU: vendor_id = "AuthenticAMD" If I revert this pa

Re: [PATCH] MAINTAINERS: add reviewers for some s390 areas

On 6/23/25 12:00 PM, Matthew Rosato wrote: To improve review coverage, assign additional people as reviewers for multiple s390 sections. Signed-off-by: Matthew Rosato Acked-by: Jason J. Herne

Re: [PATCH v2 035/101] target/arm: Implement SME2 FDOT

On 6/23/25 09:38, Peter Maydell wrote: On Sun, 22 Jun 2025 at 00:54, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 5 target/arm/tcg/sme_helper.c| 44 ++ target/arm/tcg/translate-sme.c | 18

Re: [PATCH] MAINTAINERS: add reviewers for some s390 areas

On 6/23/25 12:00 PM, Matthew Rosato wrote: > To improve review coverage, assign additional people as reviewers for > multiple s390 sections. > > Signed-off-by: Matthew Rosato > --- Acked-by: Collin Walling > MAINTAINERS | 12 > 1 file changed, 12 insertions(+) > > diff --git a/M

Re: [PATCH] MAINTAINERS: add reviewers for some s390 areas

On 6/23/25 12:00 PM, Matthew Rosato wrote: To improve review coverage, assign additional people as reviewers for multiple s390 sections. Signed-off-by: Matthew Rosato Acked-by: Jared Rossi --- MAINTAINERS | 12 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/M

Re: [PATCH v2 015/101] target/arm: Add isar feature tests for SME2, SVE2p1

On 6/23/25 03:44, Peter Maydell wrote: +static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id) +{ +return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id); +} I think we should put these "utility" functions that are testing for a combination of architectur

Re: [PATCH] MAINTAINERS: add reviewers for some s390 areas

Acked-by: Farhan Ali On 6/23/2025 9:00 AM, Matthew Rosato wrote: To improve review coverage, assign additional people as reviewers for multiple s390 sections. Signed-off-by: Matthew Rosato --- MAINTAINERS | 12 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINT

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