On Sun, 22 Jun 2025 at 01:00, Richard Henderson <richard.hender...@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/tcg/translate-sve.c | 10 ++++++++++ > target/arm/tcg/sve.decode | 8 +++++++- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c > index 29b6f09260..95121cce8e 100644 > --- a/target/arm/tcg/translate-sve.c > +++ b/target/arm/tcg/translate-sve.c > @@ -3409,6 +3409,11 @@ TRANS_FEAT(SUDOT_zzxw_4s, aa64_sve_i8mm, > gen_gvec_ool_arg_zzxz, > TRANS_FEAT(USDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, > gen_helper_gvec_usdot_idx_4b, a) > > +TRANS_FEAT(SDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzxz, > + gen_helper_gvec_sdot_idx_2h, a) > +TRANS_FEAT(UDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzxz, > + gen_helper_gvec_udot_idx_2h, a) > + > #define DO_SVE2_RRX(NAME, FUNC) \ > TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ > a->rd, a->rn, a->rm, a->index) > @@ -7108,6 +7113,11 @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, > gen_gvec_ool_zzzz, > TRANS_FEAT(USDOT_zzzz_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, > gen_helper_gvec_usdot_4b, a, 0) > > +TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, > + gen_helper_gvec_sdot_2h, a, 0) > +TRANS_FEAT(UDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, > + gen_helper_gvec_udot_2h, a, 0) > + > TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, > gen_helper_crypto_aesmc, a->rd, a->rd, 0) > TRANS_FEAT_NONSTREAMING(AESIMC, aa64_sve2_aes, gen_gvec_ool_zz, > diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode > index 7ed186c9bd..5234d0f0ae 100644 > --- a/target/arm/tcg/sve.decode > +++ b/target/arm/tcg/sve.decode > @@ -856,6 +856,9 @@ SDOT_zzxw_4d 01000100 11 1 ..... 000000 ..... ..... > @rrxr_1 esz=3 > UDOT_zzxw_4s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 > UDOT_zzxw_4d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 > > +SDOT_zzxw_2s 01000100 10 0 ..... 110010 ..... ..... @rrxr_2 esz=2 > +UDOT_zzxw_2s 01000100 10 0 ..... 110011 ..... ..... @rrxr_2 esz=2 > + > # SVE2 integer multiply-add (indexed) > MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 > MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 > @@ -1597,7 +1600,10 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... > ..... @rda_rn_rm > CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx > SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx > > -## SVE mixed sign dot product > +## SVE dot product > + > +SDOT_zzzz_2s 01000100 00 0 ..... 110 010 ..... ..... @rda_rn_rm_e0 > +UDOT_zzzz_2s 01000100 00 0 ..... 110 011 ..... ..... @rda_rn_rm_e0
These also look like they have the wrong esz ? -- PMM
