Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-14 Thread LIU Zhiwei
On 2020/7/14 21:59, Frank Chang wrote: On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: On 7/13/20 7:59 PM, Frank Chang wrote: > The latest spec specified: > > Only the low *lg2(SEW) bits* are read to obtain the shift amount f

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-14 Thread Frank Chang
On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/13/20 7:59 PM, Frank Chang wrote: > > The latest spec specified: > > > > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a > > *register value*. > > The *immediate* is treated as a

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-14 Thread Richard Henderson
On 7/13/20 7:59 PM, Frank Chang wrote: > The latest spec specified: > > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a > *register value*. > The *immediate* is treated as an *unsigned shift amount*, with a *maximum > shift > amount of 31*. Which, I hope you will agree is

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-13 Thread Frank Chang
On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei wrote: > > > On 2020/7/14 10:59, Frank Chang wrote: > > On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: >> > From: Frank Chang >> > >> > vsll.vi, vsrl.vi

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-13 Thread LIU Zhiwei
On 2020/7/14 10:59, Frank Chang wrote: On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > From: Frank Chang mailto:frank.ch...@sifive.com>> > >

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-13 Thread Frank Chang
On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the > > shift immediate value to be within the range: [0.. SEW

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-10 Thread Richard Henderson
On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > From: Frank Chang > > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the > shift immediate value to be within the range: [0.. SEW bits]. > Otherwise, it will hit the assertion: > tcg_debug_assert(shift >= 0 && shift < (8 << vece))

[RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

2020-07-10 Thread frank . chang
From: Frank Chang vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the shift immediate value to be within the range: [0.. SEW bits]. Otherwise, it will hit the assertion: tcg_debug_assert(shift >= 0 && shift < (8 << vece)); However, RVV spec does not have such constraint, therefore