From: Frank Chang <frank.ch...@sifive.com> vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the shift immediate value to be within the range: [0.. SEW bits]. Otherwise, it will hit the assertion: tcg_debug_assert(shift >= 0 && shift < (8 << vece));
However, RVV spec does not have such constraint, therefore we have to use helper functions instead. Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index c0b7375927..70d31a5525 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1427,9 +1427,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) +GEN_OPIVI_TRANS(vsll_vi, 1, vsll_vx, opivx_check) +GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check) +GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) -- 2.17.1
